Heterojunction Patents (Class 438/47)
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Publication number: 20140225062Abstract: A nitride semiconductor light emitting element is provided with: a substrate; a nitride semiconductor laminate section on the substrate; a current diffusion layer that is provided on the nitride semiconductor laminate section; a first protection film that is provided on the current diffusion layer; and a first electrode. The nitride semiconductor laminate section has: a first conductivity-type nitride semiconductor layer that is provided on the substrate; an active layer that is provided on the first conductivity-type nitride semiconductor layer; and a second conductivity-type nitride semiconductor layer that is provided on the active layer. The first electrode is electrically connected to the first conductivity-type nitride semiconductor layer. Furthermore, a part of the first electrode is formed above the second conductivity-type nitride semiconductor layer with the first protection film therebetween.Type: ApplicationFiled: July 30, 2012Publication date: August 14, 2014Applicant: Sharp Kabushiki KaishaInventor: Yufeng Weng
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Publication number: 20140225059Abstract: A light-emitting device having an n-type semiconductor layer having a plurality of pits with planar regions between the pits, the pits being characterized by sidewalk that intersect the planar regions is disclosed. A plurality of alternating sub-layers of materials having different bandgaps is deposited on the n-type semiconductor layer. The sub-layers have thicknesses such that the sub-layers form an active layer in the planar regions between the pits and a super lattice on the sidewalls of the pits. A p-type semiconductor layer is deposited on the plurality of alternating sub-layers. One of the sub-layers includes an electron blocking layer. The electron blocking layer is characterized by a first thickness in the substantially planar regions and a second thickness in areas adjacent to the sidewalls of the pits, the second thickness being less than the first thickness.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: BRIDGELUX, INC.Inventors: Long Yang, Steve Lester, Jeff Ramer
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Publication number: 20140217358Abstract: This application discloses a light-emitting diode comprising a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a semiconductor contact layer on the second semiconductor layer. The second semiconductor layer comprises a first sub-layer and a second sub-layer formed above the first sub-layer, wherein the material of the second sub-layer comprises AlxGa1-xN(0<x<1) and the second sub-layer has a surface comprising a structure of irregularly distributed holes.Type: ApplicationFiled: January 23, 2014Publication date: August 7, 2014Applicant: EPISTAR CORPORATIONInventors: Yu-Yao LIN, Tsun-Kai KO, Chien-Yuan TSENG, Yen-Chih CHEN, Chun-Ta YU, Shih-Chun LING, Cheng-Hsiung YEN, Hsin-Hsien WU
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Publication number: 20140209921Abstract: A semiconductor light emitting element includes: an n-type semiconductor layer; a light emitting layer alternately laminating plural barrier layers and plural well layers; and a p-type semiconductor layer, wherein the light emitting layer includes three or more well layers and four or more barrier layers, each well layer being sandwiched by the barrier layers, one barrier layer contacting the n-type semiconductor layer, and another barrier layer contacting the p-type semiconductor layer, the well layers include plural n-side well layers from the n-type semiconductor layer side and one p-side well layer on the p-type semiconductor layer side, and a V-shaped concave portion including inclined surfaces is generated in the light emitting layer, and in at least one of the n-side well layers, a concentration of atoms of In on the inclined surface is not more than 50% of a concentration of atoms of In in the n-side well layer.Type: ApplicationFiled: December 18, 2013Publication date: July 31, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Katsuki KUSUNOKI, Hisao Sato
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Publication number: 20140209857Abstract: In a method of manufacture for a nitride semiconductor light emitting element including: a monocrystalline substrate; and an AlN layer; and a first nitride semiconductor layer of a first electrical conductivity type; and a light emitting layer made of an AlGaN-based material; and a second nitride semiconductor layer of a second electrical conductivity type, a step of forming the AlN layer includes: a first step of supplying an Al source gas and a N source gas into the reactor to generate a group of MN crystal nuclei having Al-polarity to be a part of the AlN layer on the surface of the monocrystalline substrate; and a second step of supplying the Al source gas and the N source gas into the reactor to form the AlN layer, after the first step.Type: ApplicationFiled: July 5, 2012Publication date: July 31, 2014Applicants: RIKEN, PANASONIC CORPORATIONInventors: Takayoshi Takano, Takuya Mino, Norimichi Noguchi, Kenji Tsubaki, Hideki Hirayama
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Patent number: 8790945Abstract: A nitride semiconductor device includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and metal electrodes formed in contact with the silicon substrate. The metal electrodes has first metal layers which are formed in a shape of discrete islands and in contact with the silicon substrate, and second metal layers which are in contact with the silicon substrate exposed among the islands of the first metal layers and are formed to cover the first metal layers. Further, the second metal layers are made of a metal capable of forming ohmic contact with silicon, and the first metal layers are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer.Type: GrantFiled: September 28, 2012Date of Patent: July 29, 2014Assignee: Nichia CorporationInventors: Kentaro Watanabe, Shunsuke Minato, Giichi Marutsuki
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Patent number: 8791479Abstract: Provided are a light emitting device and a method for manufacturing the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and a light extraction layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type semiconductor layer is formed on the active layer. The light extraction layer is formed on the second conductive type semiconductor layer. The light extraction layer has a refractive index smaller than or equal to a refractive index of the second conductive type semiconductor layer.Type: GrantFiled: December 20, 2012Date of Patent: July 29, 2014Assignee: LG Innotek Co., Ltd.Inventor: Dae Sung Kang
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Publication number: 20140206121Abstract: A method of fabricating an organic light emitting device is provided. A first electrode is provided, over which the rest of the device will be fabricated. A first organic layer is deposited over the first electrode via solution processing. The first organic layer includes: i. an organic host material of the first organic layer; ii. a first organic emitting material of the first organic layer; iii. a second organic emitting material of the first organic layer; A second organic layer is deposited over and in direct contact with the first organic layer. The second organic layer includes an organic emitting material of the second organic layer. A second electrode is then deposited over the second organic layer. The device may include other layers.Type: ApplicationFiled: March 19, 2014Publication date: July 24, 2014Applicant: Universal Display CorporationInventors: Kwang Ohk CHEON, Michael INBASEKARAN, Julie J. BROWN
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Patent number: 8785226Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.Type: GrantFiled: September 20, 2013Date of Patent: July 22, 2014Assignee: STC.UNMInventors: Seung Chang Lee, Steven R. J. Brueck
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Patent number: 8784703Abstract: A method of making a colloidal solution of high confinement semiconductor nanocrystals includes: forming a first solution by combining a solvent, growth ligands, and at most one semiconductor precursor; heating the first solution to the nucleation temperature; and adding to the first solution, a second solution having a solvent, growth ligands, and at least one additional and different precursor than that in the first solution to form a crude solution of nanocrystals having a compact homogenous semiconductor region. The method further includes: waiting 0.5 to 20 seconds and adding to the crude solution a third solution having a solvent, growth ligands, and at least one additional and different precursor than those in the first and second solutions; and lowering the growth temperature to enable the formation of a gradient alloy region around the compact homogenous semiconductor region, resulting in the formation of a colloidal solution of high confinement semiconductor nanocrystals.Type: GrantFiled: October 18, 2011Date of Patent: July 22, 2014Assignee: Eastman Kodak CompanyInventors: Keith Brian Kahen, Matthew Holland, Sudeep Pallikkara Kuttiatoor
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Patent number: 8785228Abstract: A method and apparatus for dividing a thin film device having a first layer which is a lower electrode layer, a second layer which is an active layer and a third layer which is an upper electrode layer, the layers each being continuous over the device, into separate cells which are electrically interconnected in series.Type: GrantFiled: April 15, 2010Date of Patent: July 22, 2014Assignee: M-Solv Ltd.Inventor: Adam North Brunton
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Publication number: 20140191187Abstract: A light emitting device comprises an n-type layer, a p-type layer, and an active region sandwiched between the n-type layer and the p-type layer, wherein the active-region has a wavy structure with nano or micro fluctuations in its thickness direction. The n-type layer comprises crystal facets on its upper surface, and the active-region is conformally formed on the upper surface of the n-type layer and substantially follows the shape of the crystal facets so as to form the wavy structure. A method for fabricating the same is also provided.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicant: INVENLUX LIMITEDInventor: JIANPING ZHANG
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Publication number: 20140191200Abstract: An apparatus for depositing one or more organic material layers of an OLED lighting device upon a first region of a substrate and one or more conducting layers upon a second region, wherein the conducting layers partially or completely cover and extend beyond one side of the organic layers, comprising: a reusable mask in contact with the substrate, at least one mask open area having an overhang feature; one or more sources of vaporized organic material, selected to form layers of the OLED lighting device, and the vaporized organic material plume is shaped, on the side corresponding to the mask overhang feature, so as to limit substantial transfer of organic material on said side to angles less than or equal to a selected cutoff angle to the first region; and one or more sources of vaporized conducting material that transfer conducting material to the second region, wherein the second region partially or completely overlaps the first region and extends beyond the first region on the side corresponding to the oType: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: OLEDWorks LLCInventors: John W. Hamer, Michael L. Boroson
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Publication number: 20140191261Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.Type: ApplicationFiled: January 9, 2014Publication date: July 10, 2014Applicant: Sensor Electronic Technology, Inc.Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Patent number: 8772063Abstract: A method for making a light emitting diode is provided. In the method, a substrate having an epitaxial growth surface is provided. A first semiconductor layer, an active layer, a second semiconductor layer are grown on the epitaxial growth surface in the listed sequence. The first semiconductor layer, the active layer, and the second semiconductor layer constitute a source layer. A third optical symmetric layer, a metallic layer, a fourth optical symmetric layer, a first optical symmetric layer, and a second optical symmetric layer are then disposed on a surface of the second semiconductor layer away from the substrate in the listed sequence. A first electrode is applied to electrically connect with the first semiconductor layer and a second electrode is applied to electrically connect with the second semiconductor layer.Type: GrantFiled: December 28, 2012Date of Patent: July 8, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Hao-Su Zhang, Jun Zhu, Qun-Qing Li, Guo-Fan Jin, Shou-Shan Fan
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Patent number: 8772800Abstract: According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.Type: GrantFiled: October 21, 2013Date of Patent: July 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Taisuke Sato, Kotaro Zaima, Jumpei Tajima, Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Shinya Nunoue
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Publication number: 20140183580Abstract: A group III nitride semiconductor light-emitting element having a pn junction hetero structure composed of: an n-type aluminum gallium indium nitride layer; a light-emitting layer disposed contacting the n-type aluminum gallium indium nitride layer and including a gallium indium nitride layer containing crystals having a larger lattice constant than the n-type aluminum gallium indium nitride layer; and a p-type aluminum gallium indium nitride layer provided on the light-emitting layer. Further, the relative atomic concentrations of donor impurities at either interface of the light-emitting layer and within respective layers of the light-emitting element are specified herein.Type: ApplicationFiled: May 16, 2012Publication date: July 3, 2014Applicant: TOYODA GOSEI CO., LTD.Inventor: Hiroshi Udagawa
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Publication number: 20140183445Abstract: An LED package includes a substrate, a buffer layer formed on the substrate, an epitaxial structure formed on the buffer layer, and a plurality of carbon nanotube bundles formed in the epitaxial structure.Type: ApplicationFiled: August 30, 2013Publication date: July 3, 2014Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventors: YA-WEN LIN, CHING-HSUEH CHIU, PO-MIN TU, SHIH-CHENG HUANG
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Publication number: 20140183461Abstract: An organic light emitting display panel includes a first pixel and a second pixel respectively disposed in first and second light emitting areas. A portion of a first hole transport layer and a portion of a first light emitting layer of the first pixel are disposed in the second light emitting area. The portions of the first hole transport layer and the first light emitting layer overlap a second hole transport layer and a second light emitting layer, which are successively stacked. The second hole transport layer and the second light emitting layer block holes and electrons from moving to the portion of the first light emitting layer.Type: ApplicationFiled: July 10, 2013Publication date: July 3, 2014Inventors: Jae Jung Kim, Joon Young Park, Hongkyun Ahn
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Publication number: 20140183447Abstract: According to one embodiment, a semiconductor light emitting element includes an n-type semiconductor layer including a nitride semiconductor, a p-type semiconductor layer and a light emitting layer. The p-type semiconductor layer includes a first p-side layer of Alx1Ga1?x1N (0?x1<1) including Mg, a second p-side layer of Alx2Ga1?x2N (0<x2<1) including Mg and a third p-side layer of Alx3Ga1?x3N (x2<x3<1) including Mg. The light emitting layer is provided between the n-type semiconductor layer and the second p-side layer. The light emitting layer includes barrier layers and well layers. Each of the well layers is provided between the barrier layers. A p-side barrier layer of the barrier layers most proximal to the second p-side layer includes a first layer of Alz1Ga1?z1N (0?z1), and a second layer of Alz2Ga1?z2N (z1<z2<x2).Type: ApplicationFiled: December 12, 2013Publication date: July 3, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hajime NAGO, Shigeya KIMURA, Yoshiyuki HARADA, Shinya NUNOUE
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Patent number: 8765509Abstract: A method for producing a Group III nitride semiconductor light-emitting device includes an n-type layer, a light-emitting layer, and a p-type layer, each of the layers being formed of Group III nitride semiconductor, being sequentially deposited via a buffer layer on a textured sapphire substrate. A buried layer is formed of Group III nitride semiconductor on the buffer layer, at a temperature lower by 20° C. to 80° C. than the temperature of 1000° C. to 1200° C. when the n-type layer is deposited on the buried layer. The texture provided on the sapphire substrate may have a depth of 1 ?m to 2 ?m and a side surface inclined by 40° to 80°. A preventing layer may be formed of GaN at 600° C. to 1050° C. so as to cover the entire top surface of the buffer layer.Type: GrantFiled: September 23, 2011Date of Patent: July 1, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Daisuke Shinoda, Shugo Nitta, Yoshiki Saito
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Patent number: 8766237Abstract: A homo-material heterophased quantum well includes a first structural layer, a second structural layer and a third structural layer. The second structural layer is sandwiched between the first and third structural layers. The first structural layer, second structural layer and third structural layer are formed by growing atoms of a single material in a single growth direction. The energy gap of the second structural layer is smaller than that of the first and third structural layers.Type: GrantFiled: January 19, 2011Date of Patent: July 1, 2014Assignee: National Sun Yat-Sen UniversityInventors: I-Kai Lo, Yu-Chi Hsu, Chia-Ho Hsieh, Wen-Yuan Pang, Ming-Chi Chou
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Patent number: 8765510Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.Type: GrantFiled: October 12, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 8765505Abstract: The present invention relates to a multi-luminous element and a method for manufacturing the same. The present invention provides the multi-luminous element comprising: a buffer layer disposed on a substrate; a first type semiconductor layer disposed on the buffer layer; a first active layer which is disposed on the first type semiconductor layer and is patterned to expose a part of the first type semiconductor layer; a second active layer disposed on the first type semiconductor layer which is exposed by the first active layer; and a second type semiconductor layer disposed on the first active layer and the second active layer, the first and second active layers being repeatedly disposed in the horizontal direction, and the method for manufacturing the same.Type: GrantFiled: March 15, 2011Date of Patent: July 1, 2014Assignee: Korea Photonics Technology InstituteInventors: Seong Ran Jeon, Jae Bum Kim, Seung Jae Lee
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Patent number: 8766294Abstract: A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p- and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end portions of the p- and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.Type: GrantFiled: December 6, 2012Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Keisuke Unosawa
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Publication number: 20140175476Abstract: The process for the manufacture of a light-emitting diode comprises the following stages: the formation of a stack (1) of layers intended to emit light comprising first (2), second (3) and third (4) layers of aluminium gallium nitride, the said second layer (3), positioned between the first and third layers (2, 4), having an aluminium gallium nitride composition different from that of the first and third layers (2, 4); and the implementation of a demixing of the second layer (3) of aluminium gallium nitride carried out after formation of the said second layer.Type: ApplicationFiled: December 26, 2013Publication date: June 26, 2014Inventor: Bruno Daudin
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Publication number: 20140179046Abstract: A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe.Type: ApplicationFiled: December 11, 2013Publication date: June 26, 2014Applicant: The Regents of the University of CaliforniaInventors: Shimon Weiss, Marcel Bruchez, Paul A. Alivisatos
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Publication number: 20140175474Abstract: A method of manufacturing a semiconductor light emitting device, includes: forming a plurality of concave portions on a substrate; injecting silica particles into the plurality of concave portions; and forming a semiconductor layer on the substrate, the semiconductor layer including voids formed in portions of the semiconductor layer, the portions being located above the plurality of concave portions.Type: ApplicationFiled: August 15, 2013Publication date: June 26, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Heon HAN, Jong Pa HONG, Seung Hyun KIM, Yun Hee SHIN, Jeong Wook LEE
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Patent number: 8759131Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.Type: GrantFiled: January 26, 2010Date of Patent: June 24, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
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Patent number: 8759881Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.Type: GrantFiled: December 1, 2010Date of Patent: June 24, 2014Assignee: SoitecInventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
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Patent number: 8759130Abstract: A method for making a light emitting diode includes the following steps. A substrate having a first epitaxial growth surface is provided. A carbon nanotube layer is placed on the first epitaxial growth surface of the substrate. A surface of the first semiconductor layer is exposed by removing the substrate and the carbon nanotube layer. The surface of the first semiconductor layer is defined as a second epitaxial growth surface. An active layer and a second semiconductor layer are grown on the second epitaxial growth surface in that order. A surface of the active layer contacted the first semiconductor layer engages with the second epitaxial growth surface. A part of the first semiconductor layer is exposed by etching a part of the active layer and the second semiconductor layer. A first electrode is applied on the first semiconductor layer and a second electrode is applied on the second semiconductor layer.Type: GrantFiled: December 28, 2012Date of Patent: June 24, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Yang Wei, Shou-Shan Fan
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Patent number: 8759851Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.Type: GrantFiled: July 29, 2013Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20140166977Abstract: A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane).Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: Sensor Electronic Technology, Inc.Inventors: Michael Shur, Remigijus Gaska, Jinwei Yang
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Patent number: 8753911Abstract: LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.Type: GrantFiled: November 13, 2012Date of Patent: June 17, 2014Assignee: RiteDia CorporationInventor: Chien-Min Sung
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Patent number: 8754430Abstract: A light emitting device is disclosed. The light emitting device includes a first conductive type semiconductor layer, an active layer disposed on the first conductive type semiconductor layer, a tunnel junction layer comprising a second conductive type nitride semiconductor layer and a first conductive type nitride semiconductor layer disposed on the active layer, wherein the first conductive type nitride semiconductor layer and the second conductive type nitride semiconductor layer are PN junctioned, a first electrode disposed on the first conductive type semiconductor layer, and a second electrode disposed on the first conductive type nitride semiconductor layer, wherein a portion of the second electrode is in schottky contact with the second conductive type nitride semiconductor layer through the first conductive type nitride semiconductor layer.Type: GrantFiled: February 6, 2012Date of Patent: June 17, 2014Assignee: LG Innotek Co., Ltd.Inventor: Jae Hoon Kim
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Publication number: 20140158977Abstract: A near-infrared light emitting device can include semiconductor nanocrystals that emit at wavelengths beyond 1 ?m. The semiconductor nanocrystals can include a core and an overcoating on a surface of the core.Type: ApplicationFiled: December 10, 2013Publication date: June 12, 2014Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Geoffrey J.S. SUPRAN, Katherine W. SONG, Gyuweon HWANG, Raoul Emile CORREA, Yasuhiro SHIRASAKI, Moungi G. BAWENDI, Vladimir BULOVIC
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Publication number: 20140162389Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.Type: ApplicationFiled: February 12, 2014Publication date: June 12, 2014Applicant: KONINKLIJKE PHILIPS N.V.Inventors: Andrew Y. Kim, Patrick N. Grillot
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Publication number: 20140159081Abstract: A method of forming a semiconductor layer is provided. The method includes forming a plurality of nanorods on a substrate and forming a lower semiconductor layer on the substrate so as to expose at least portions of the nanorods. The nanorods are removed so as to form voids in the lower semiconductor layer, and an upper semiconductor layer is formed on an upper portion of the lower semiconductor layer and the voids.Type: ApplicationFiled: August 29, 2013Publication date: June 12, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong Suk LEE, Ok Hyun KIM, Dong Yul LEE, Dong Ju LEE, Jeong Wook LEE, Heon Ho LEE
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Publication number: 20140154821Abstract: A method for fabricating a vertical light-emitting diode (VLED) structure includes the steps of providing a carrier substrate, and forming a semiconductor structure on the carrier substrate having a p-type confinement layer, a multiple quantum well (MQW) layer in electrical contact with the p-type confinement layer configured to emit electromagnetic radiation, and an n-type confinement layer in electrical contact with the multiple quantum well (MQW) layer. The method also includes the steps of removing the carrier substrate using a laser pulse to expose an inverted surface of the n-type confinement layer, and forming a metal contact on the surface of the n-type confinement layer.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: SemiLEDS Optoelectronics Co., Ltd.Inventors: CHEN-FU CHU, WEN-HUANG LIU, JIUNN-YI CHU, CHAO-CHEN CHENG, HAO-CHUN CHENG, FENG-HSU FAN, Trung Tri Doan
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Publication number: 20140151634Abstract: A light emitting diode structure of (Al,Ga,In)N thin films grown on a gallium nitride (GaN) semipolar substrate by metal organic chemical vapor deposition (MOCVD) that exhibits reduced droop. The device structure includes a quantum well (QW) active region of two or more periods, n-type superlattice layers (n-SLs) located below the QW active region, and p-type superlattice layers (p-SLs) above the QW active region. The present invention also encompasses a method of fabricating such a device.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Shuji Nakamura, Steven P. DenBaars, Shinichi Tanaka, Daniel F. Feezell, Yuji Zhao, Chih-Chien Pan
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Patent number: 8741670Abstract: A method for producing an integrated optical device includes the steps of growing a first stacked semiconductor layer including a first optical waveguiding layer, a first cladding layer, and a side-etching layer; etching the first stacked semiconductor layer through a first etching mask; growing, a second stacked semiconductor layer including a second optical waveguiding layer and a second cladding layer through the first etching mask; and forming a reverse-mesa ridge structure by etching the first and second cladding layers. The step of etching the first stacked semiconductor layer includes a step of forming an overhang by etching the side-etching layer by wet etching. In the step of growing the second stacked semiconductor layer, the second cladding layer is grown at a lower growth temperature and a higher V/III ratio comparing to those in the growth of the second optical waveguiding layer.Type: GrantFiled: January 15, 2013Date of Patent: June 3, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Tomokazu Katsuyama
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Patent number: 8741686Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.Type: GrantFiled: March 15, 2013Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
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Publication number: 20140145144Abstract: A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core.Type: ApplicationFiled: November 20, 2013Publication date: May 29, 2014Applicant: LG DISPLAY CO., LTD.Inventors: Kyung-Seok Jeong, Gee-Sung Chae, Jin-Wuk Kim, Sung-hee Cho
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Patent number: 8735192Abstract: There is provided a nitride semiconductor light emitting device having a light emitting portion coated with a coating film, the light emitting portion being formed of a nitride semiconductor, the coating film in contact with the light emitting portion being formed of an oxynitride. There is also provided a method of fabricating a nitride semiconductor laser device having a cavity with a facet coated with a coating film, including the steps of: providing cleavage to form the facet of the cavity; and coating the facet of the cavity with a coating film formed of an oxynitride.Type: GrantFiled: May 23, 2008Date of Patent: May 27, 2014Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
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Patent number: 8735196Abstract: According to one embodiment, in a method of a nitride semiconductor light emitting device, a nitride semiconductor laminated body is formed on a first substrate having a first size. A first adhesion layer with a second size smaller than the first size is formed on the nitride semiconductor laminated body. A second adhesion layer is formed on a second substrate. The first and the second substrates are bonded while the first and second adhesion layers being overlapped each other. The first substrate is removed so as to generate a recess having a third size equal to or larger than the second size. The first substrate is etched until exposing the nitride semiconductor laminated body while injecting a chemical solution into the recess. The exposed nitride semiconductor laminated body is etched using the chemical solution so as to form a concave-convex portion in the exposed nitride semiconductor laminated body.Type: GrantFiled: March 2, 2012Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Masanobu Ando
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Patent number: 8735197Abstract: This invention discloses a wafer-scaled light-emitting structure comprising a supportive substrate; an anti-deforming layer; a bonding layer; and a light-emitting stacked layer, wherein the anti-deforming layer reduces or removes the deformation like warp caused by thinning of the substrate.Type: GrantFiled: October 29, 2012Date of Patent: May 27, 2014Assignee: Epistar CorporationInventors: Chin-San Tao, Tzu-Chien Hsu, Tsen-Kuei Wang
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Patent number: 8728834Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.Type: GrantFiled: July 2, 2012Date of Patent: May 20, 2014Assignee: Phostek, Inc.Inventor: Yuan-Hsiao Chang
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8729526Abstract: An optical semiconductor device includes a substrate; and an active layer disposed on the substrate, wherein the active layer includes a first barrier layer containing GaAs, a quantum dot layer, which is disposed on the first barrier layer, which includes a quantum dot containing InAs, which includes a side barrier layer which covers at least a part of the quantum dot and a side surface of the quantum dot, and having an elongation strain inherent therein, and a second barrier layer disposed on the quantum dot layer.Type: GrantFiled: December 10, 2010Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventor: Nobuaki Hatori
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Patent number: 8728840Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.Type: GrantFiled: September 5, 2012Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Thomas Gehrke