Including Implantation Of Ion Which Reacts With Semiconductor Substrate To Form Insulating Layer Patents (Class 438/480)
  • Patent number: 10431717
    Abstract: Micro LED displays offer brighter screens and wider color gamuts than that achievable using traditional LED or OLED displays. Various embodiments are directed to LED and micro LED structures having substrates comprising a metal and oxygen, such as gallium and oxygen, and methods of forming the same. An integrated circuit (IC) structure can include a substrate comprising a metal and oxygen and a core over the substrate. The core can include a group III semiconductor material and nitrogen, and the core can be doped with n-type or p-type dopants. An active layer comprising indium can be provide on a surface of the core. The indium concentration can be adjusted to tune a peak emission wavelength of the IC structure. The IC structure can include a cladding on a surface of the active layer. The cladding can be doped with dopants of opposite type than those used to dope the core.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then
  • Patent number: 9054035
    Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 9, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Franz Josef Niedernostheide, Frank Dieter Pfirsch
  • Patent number: 9006083
    Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 14, 2015
    Inventor: Ananda H. Kumar
  • Patent number: 8969181
    Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 3, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Morgan D. Evans, Christopher R. Hatem
  • Patent number: 8956951
    Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 17, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Masahiro Kato, Masayuki Imai
  • Patent number: 8946067
    Abstract: A method of preparing a thin material layer from a semiconductor substrate is presented. The method entails forming a stress-generating epitaxial layer on a base substrate to form a stressed region, and achieving separation along the stressed region to produce a first part and a second part. The stress-generating epitaxial layer may be boron-doped or a Si(1-x)—Gex material. The separation may be achieved with spalling or etching.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 3, 2015
    Inventor: Bing Hu
  • Patent number: 8921209
    Abstract: A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8889530
    Abstract: A highly dislocation free compound semiconductor, e.g. AlxInyGa1-x-yN (0?x, y?1), is formed on a lattice mismatched substrate, e.g. Si, by first depositing a polycrystalline buffer layer on the substrate. A defective layer is then created at or near the interface of the substrate and the polycrystalline buffer layer, e.g. through ion implantation. A monocrystalline template layer of the compound semiconductor is then created on the buffer layer, and an epilayer of the compound semiconductor is grown on the template layer. A compound semiconductor based device structure may be formed in the epilayer.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: November 18, 2014
    Assignee: The Research Foundation of State University of New York
    Inventors: Fatemeh Shahedipour-Sandvik, Di Wu, Jamil Kahn Muhammad
  • Patent number: 8883616
    Abstract: In an implementation, a Germanium on insulator apparatus is fabricated by forming a patterned masking layer on a Silicon on insulator (SOI) layer that leaves a portion of the SOI layer exposed, implanting Germanium onto the exposed portion of the SOI layer to form a Silicon-Germanium island, depositing amorphous Germanium over the Silicon-Germanium island and the patterned masking layer, removing the patterned masking layer and the amorphous Germanium that was deposited onto the patterned masking layer to produce a Silicon-Germanium composite stripe, and annealing the Silicon-Germanium composite stripe to crystallize the amorphous Germanium in the Silicon-Germanium composite stripe.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alexandre M. Bratkovski, Leonid Tsybeskov
  • Patent number: 8828769
    Abstract: A solid-state energy conversion device and method of making is disclosed wherein the solid-state energy conversion device is formed through the conversion of an insulating material. In one embodiment, the solid-state energy conversion device operates as a photovoltaic device to provide an output of electrical energy upon an input of electromagnetic radiation. In another embodiment, the solid-state energy conversion device operates as a light emitting device to provide an output of electromagnetic radiation upon an input of electrical energy. In one example, the photovoltaic device is combined with a solar liquid heater for heating a liquid. In another example, the photovoltaic device is combined with a solar liquid heater for treating water.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: September 9, 2014
    Assignee: University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar
  • Patent number: 8790999
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Tomonari Shioda, Shinya Nunoue
  • Patent number: 8779512
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 15, 2014
    Assignees: NEC Corporation, NLT Technologies, Ltd.
    Inventor: Shigeru Mori
  • Publication number: 20140070215
    Abstract: A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140073119
    Abstract: A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140035104
    Abstract: In an implementation, a Germanium on insulator apparatus is fabricated by forming a patterned masking layer on a Silicon on insulator (SOI) layer that leaves a portion of the SOI layer exposed, implanting Germanium onto the exposed portion of the SOI layer to form a Silicon-Germanium island, depositing amorphous Germanium over the Silicon-Germanium island and the patterned masking layer, removing the patterned masking layer and the amorphous Germanium that was deposited onto the patterned masking layer to produce a Silicon-Germanium composite stripe, and annealing the Silicon-Germanium composite stripe to crystallize the amorphous Germanium in the Silicon-Germanium composite stripe.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Alexandre M. BRATKOVSKI, Leonid Tsybeskov
  • Patent number: 8617962
    Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 31, 2013
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sebastien Kerdiles
  • Patent number: 8609514
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 17, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
  • Patent number: 8603900
    Abstract: Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 10, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Deepak Ramappa
  • Publication number: 20130316522
    Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.
    Type: Application
    Filed: November 18, 2011
    Publication date: November 28, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Isao Yokokawa, Satoshi Oka
  • Patent number: 8587039
    Abstract: A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Patent number: 8575722
    Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: November 5, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
  • Patent number: 8486776
    Abstract: Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L. Saenger
  • Patent number: 8487280
    Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Gary E. Dickerson, Julian G. Blake
  • Patent number: 8466047
    Abstract: A method for processing the surface of a component, or the processing of an optical element through an ion beam, directed onto the surface to be processed, whereby the surface is lowered and/or removed at least partially, and wherein the ions have a kinetic energy of 100 keV or more, as well as optical elements processed in accordance with the method.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 18, 2013
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Martin Weiser, Stefan Burkhart, Holger Maltor
  • Patent number: 8431447
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: April 30, 2013
    Assignees: NEC Corporation, NLT Technologies, Ltd.
    Inventor: Shigeru Mori
  • Patent number: 8421006
    Abstract: A device for generating sprays of charged droplets, and resulting nanoparticles, the device comprising a first needle connected to an electrical potential line to generate a first spray of charged particles from the first needle, and a second needle spaced apart from and facing the first needle, and connected to an electrical line configured to ground the second needle or to apply a voltage to the second needle that is the same polarity as the voltage applied to the first needle. The device also comprising an electric field modifier connected to the first needle, and configured to modify an electrical field to generate a second spray of charged particles from the second needle.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 16, 2013
    Assignee: MSP Corporation
    Inventors: Amir A. Naqwi, Christopher W. Fandrey, Zeeshan H. Syedain
  • Patent number: 8372733
    Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 12, 2013
    Assignees: Soitec, Commissariat à l'Énergie Atomique
    Inventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
  • Patent number: 8361888
    Abstract: The present invention provides a method for manufacturing an SOI wafer wherein an HCl gas is mixed in a reactive gas at a step of forming a silicon epitaxial layer on an entire surface of an SOI layer of the SOI wafer having an oxide film on a terrace portion. As a result, it is possible to provide the method for manufacturing an SOI wafer that can easily grow the silicon epitaxial layer on the SOI layer of the SOI wafer having the oxide film on the terrace portion, suppress warpage of the SOI wafer to be manufactured, reduce generation of particles even at subsequent steps, e.g., device manufacture, and decrease a cost for manufacturing such an SOI wafer.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 29, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Nobuhiko Noto
  • Patent number: 8349667
    Abstract: The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: January 8, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Thierry Poiroux
  • Patent number: 8338277
    Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: December 25, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8318587
    Abstract: It is an object to provide a method for manufacturing an SOI substrate in which reduction in yield can be suppressed while impurity diffusion into a semiconductor film is suppressed. A semiconductor substrate provided with an oxide film is formed by thermally oxidizing the surface of the semiconductor substrate. Plasma is generated under an atmosphere of a gas containing nitrogen atoms and plasma nitridation is performed on part of the oxide film, so that a semiconductor substrate in which an insulating film containing nitrogen atoms is formed over the oxide film is obtained. After bonding the insulating film containing nitrogen atoms and a glass substrate to each other, the semiconductor substrate is split, whereby an SOI substrate in which the insulating film containing nitrogen atoms, the oxide film, a thin semiconductor film are stacked in this order is formed.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Masaki Koyama, Toru Hasegawa
  • Patent number: 8309423
    Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu
  • Patent number: 8304327
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8222124
    Abstract: This method for manufacturing a SIMOX wafer includes: forming a mask layer on one surface side of a silicon single crystal wafer, which has an opening on a region where a BOX layer is to be formed; implanting oxygen ions through the opening of the mask layer into the silicon single crystal wafer to a predetermined depth, and locally forming an oxygen implantation region; annealing the silicon single crystal wafer with the mask layer, and oxidizing the oxygen implantation region so as to form the BOX layer; and removing a coated oxide film that covers the whole silicon single crystal wafer which is formed in the annealing of the silicon single crystal wafer, wherein the mask layer has a lamination comprising an oxide film and either one or both of a polysilicon film and an amorphous silicon film.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 17, 2012
    Assignee: Sumco Corporation
    Inventor: Tetsuya Nakai
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8183133
    Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: May 22, 2012
    Assignee: Sumco Corporation
    Inventors: Satoshi Murakami, Nobuyuki Morimoto, Hideki Nishihata, Akihiko Endo
  • Patent number: 8178932
    Abstract: A semiconductor device includes a first transistor having a threshold voltage (Vth) adjusted to a first Vth by a first dopant having a first peak of concentration at a first depth; and a second transistor having the same channel-type as that of the first transistor and having a Vth adjusted to a second Vth by a second dopant having a second peak of concentration at a second depth equal to the first depth and higher concentration than the first dopant; wherein the first dopant and the second dopant are dopants comprising the same constituent element.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takao
  • Patent number: 8163632
    Abstract: A method for processing the surface of a component, or the processing of an optical element through an ion beam, directed onto the surface to be processed, so that the surface is lowered and/or removed at least partially, wherein the ions have a kinetic energy of 100 keV or more, as well as optical elements processed by the method.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: April 24, 2012
    Assignee: CARL ZEISS SMT GmbH
    Inventors: Martin Weiser, Stefan Burkart, Holger Maltor
  • Publication number: 20120068267
    Abstract: Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Katherine L. Saenger
  • Patent number: 8138029
    Abstract: A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Zhijiong Luo, Qingqing Liang, Haizhou Yin
  • Patent number: 8138063
    Abstract: An object of the present invention is to provide a semiconductor device having a structure which can realize not only suppressing a punch-through current but also reusing a silicon wafer which is used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. The semiconductor device can suppress the punch-through current by forming a semiconductor film in which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted over a substrate having an insulating surface, and forming a channel formation region using a semiconductor film of stacked layers obtained by bonding a single crystal semiconductor film to the semiconductor film by an SOI technique.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiromichi Godo
  • Patent number: 8101528
    Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: January 24, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau
  • Patent number: 8053327
    Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: November 8, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
  • Patent number: 8048784
    Abstract: Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Yong-Hoon Son, Jong-Wook Lee
  • Patent number: 8043929
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: October 25, 2011
    Assignee: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Patent number: 8039658
    Abstract: A method of removing trace levels of arsenic-containing impurities from raw triethylphosphate (TEPO) is disclosed. The method uses adsorption, or adsorption followed by a flash distillation. The method comprises contacting raw triethylphosphate (TEPO) with an adsorbent which selectively adsorbs the arsenic-containing impurities in the raw triethylphosphate (TEPO). The adsorbent is a base promoted alumina containing adsorbent represented by a formula: ZxWy; where x is the weight percentage of Z in the adsorbent ranging from 30% to 99.999%; y is the weight percentage of W in the adsorbent, and x+y=100%; Z is selected from the group consisting of alumina (Al2O3), magnesium-alumina based layered double hydroxide (MgO—Al2O3), alumina-zeolite, and mixtures thereof; and W is selected from the group consisting of at least one basic metal oxide, at least one basic metal carbonate, and mixtures thereof.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: October 18, 2011
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Steven Gerard Mayorga, Heather Regina Bowen, Kelly Ann Chandler
  • Patent number: 8034669
    Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel
  • Patent number: 8034695
    Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshito Suwa, Masataka Takebuchi
  • Patent number: 8030187
    Abstract: A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Bunji Mizuno
  • Patent number: 8003458
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: August 23, 2011
    Assignee: Infineon Technologies AG
    Inventors: Frank Huebinger, Richard Lindsay