Deposition Utilizing Plasma (e.g., Glow Discharge, Etc.) Patents (Class 438/485)
  • Patent number: 7041178
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: May 9, 2006
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Patent number: 7001831
    Abstract: A non-Si non-C-based gas is heated by a thermal catalysis body provided in a gas introduction channel, and the heated non-Si non-C-based gas and a material-based gas comprising Si and/or C are separately introduced into a film deposition space through a showerhead having a plurality of gas effusion ports, and in the film deposition space, a plasma space is formed by a nonplanar electrode connected to a radio frequency power supply, thereby forming a film on a substrate. Formation of high-quality Si-based films and C-based films can thus be accomplished at high deposition rate over large area with uniform film thickness and homogeneous quality. Also, highly efficient devices including photoelectric conversion devices represented by solar cells can be manufactured at low-cost by the use of such films.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: February 21, 2006
    Assignee: Kyocera Corporation
    Inventors: Koichiro Niira, Hirofumi Senta, Hideki Hakuma, Hiroki Okui
  • Patent number: 6987055
    Abstract: The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: January 17, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Blomiley, Gurtej S. Sandhu, Cem Basceri, Nirmal Ramaswamy
  • Patent number: 6979589
    Abstract: An excellent silicon-based thin-film photoelectric conversion device is manufactured simply and efficiently at a low cost. Specifically, a method of manufacturing the silicon-based thin-film photoelectric conversion device including a p-type semiconductor layer, an i-type microcrystalline silicon-based photoelectric conversion layer and an n-type semiconductor layer deposited by plasma CVD includes the steps of: successively depositing the p-type semiconductor layer, the i-type microcrystalline silicon-based photoelectric conversion layer and the n-type semiconductor layer on a substrate within the same plasma CVD film deposition chamber; transferring the substrate out of the film deposition chamber; and subsequently to the step of depositing the p-type semiconductor layer, the i-type microcrystalline silicon-based photoelectric conversion layer and the n-type semiconductor layer, eliminating influences of remaining n-type impurities on a cathode and/or within the film deposition chamber.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: December 27, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsushi Kishimoto, Yusuke Fukuoka, Katsuhiko Nomoto
  • Patent number: 6974762
    Abstract: A method of silanizing the surface of a low-k interlayer dielectric oxides (carbon doped oxides or organo-silicate glasses) to improve surface adhesion to adjacent thin film layers in damascene integration of microelectronic devices. A low-k interlayer dielectric oxide may be exposed to the vapor of a silane-coupling agent in order to modify its surface energy to improve adhesion with adjacent thin film layers. A low-k interlayer dielectric oxide can also be silanized by dipping the low-k interlayer dielectric oxide in a solution of silane-coupling agent. The silane-coupling agent will cause covalent bonds between the low-k interlayer dielectric oxide and the adjacent thin film thereby improving adhesion.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: David H. Gracias, Vijayakumar S. Ramachandrarao
  • Patent number: 6959029
    Abstract: A wide-slit lateral growth projection mask, projection system, and corresponding crystallization process are provided. The mask includes an opaque region with at least one a transparent slit in the opaque region. The slit has a width in the range of 10X to 50X micrometers, with respect to a X:1 demagnification system, and a triangular-shaped slit end. The triangular-shaped slit end has a triangle height and an aspect ratio in the range of 0.5 to 5. The aspect ratio is defined as triangle height/slit width. In some aspects, the triangular-shaped slit end includes one or more opaque blocking features. In another aspect, the triangular-shaped slit end has stepped-shaped sides. The overall effect of the mask is to promote uniformly oriented grain boundaries, even in the film areas annealed under the slit ends.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: October 25, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Apostolos T. Voutsas, Mark A. Crowder, Yasuhiro Mitani
  • Patent number: 6943097
    Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Hyungjun Kim, Stephen M. Rossnagel
  • Patent number: 6930025
    Abstract: In a process for forming on a substrate a transparent conductive film having crystallizability, the process comprises a first step of forming a film at a first film formation rate and a second step of forming a film at a second film formation rate, and the relationship between film formation rates in the respective steps satisfies: 2?(second film formation rate)/(first film formation rate)?100; which provides a process for producing a transparent conductive film by a deposition process advantageous for cost reduction, which can form in a short time a transparent conductive film having an uneven surface profile with a high light-confining effect, and can bring about an improvement in photovoltaic performance and enjoy a high mass productivity when applied to the formation of multi-layer structure of photovoltaic devices.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: August 16, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akiya Nakayama, Hiroshi Echizen, Yasuyoshi Takai, Naoto Okada, Shigeo Kiso
  • Patent number: 6931619
    Abstract: The invention relates to a method of improving control over the dimensions of a patterned photoresist, which enables better control of the critical dimensions of a photomask or reticle which is fabricated using the patterned photoresist. In addition, the method may be used to enable improved control over the dimensions of a semiconductor device fabricated using a patterned photoresist. In particular, a patterned photoresist is treated with an etchant plasma to reshape the surface of the patterned photoresist, where reshaping includes the removal of “t”-topping at the upper surface of the patterned resist, the removal of standing waves present on patterned surfaces, and the removal of feet which may be present at the base of the patterned photoresist, where the photoresist contacts an underlying layer such as an ARC layer.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 16, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Alex Buxbaum, Melvin W. Montgomery
  • Patent number: 6930326
    Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: August 16, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
  • Patent number: 6924212
    Abstract: A preparing method of a semiconductor, particularly a preparing method of a polycrystal semiconductor film which has a good electrical property is disclosed. In order to obtain a non-crystalline silicon film containing a lot of combination of hydrogen and silicon, a forming process of a non-crystalline silicon film by a low temperature gas phase chemical reaction, a process of a heat annealing to produce a lot of dangling bonds of silicon, so as to draw out hydrogen from said non-crystalline silicon film, and a process of applying a laser irradiation to said non-crystal silicon film having a lot of dangling bond of silicon are conducted.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: August 2, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Honyong Zhang, Naoto Kusumoto
  • Patent number: 6855621
    Abstract: The method of the present invention is a method of forming a silicon-based semiconductor layer by introducing a source gas into a vacuum vessel and forming a silicon-based semiconductor layer containing a microcrystal on a substrate introduced into the vacuum vessel by plasma CVD, which comprises a first step of forming a first region with a source gas containing halogen atoms, and a second step of forming a second region on the first region under a condition where the source gas containing halogen atoms in the second step is lower in gas concentration than that of the first step, thereby providing a method of forming a silicon-based semiconductor layer having an excellent photoelectric characteristic at a film forming rate of an industrially practical level and a photovoltaic element using the silicon-based semiconductor layer formed by the method.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: February 15, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Masafumi Sano, Akira Sakai, Yasuyoshi Takai, Ryo Hayashi, Toshihiro Yamashita
  • Patent number: 6846728
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: January 25, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Patent number: 6828179
    Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: December 7, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
  • Publication number: 20040214413
    Abstract: By-products inside a furnace body of a CVD film forming apparatus after gas cleaning is performed in the furnace body are provided from being generated. The gas cleaning is performed in the furnace body by a plasma of a gas containing a halogen system gas and an Ar gas in an atmosphere in which the temperature of a heater disposed in the furnace body is approximately 500° C. or lower. Thereafter, a rise of the temperature of the heater is started. While the temperature of the heater is maintained constant, a film forming gas is introduced into the furnace body during a time period before the raised temperature reaches a temperature at which radicals or ions of a halogen system element are activated.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 28, 2004
    Applicant: Trecenti Technologies, Inc.
    Inventors: Tomoyasu Nakamine, Kenichi Yamaguchi, Kenichi Satoh
  • Patent number: 6803309
    Abstract: A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least about 400° C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: October 12, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shih-Wei Chou, Chii-Ming Wu
  • Patent number: 6800539
    Abstract: In a discharge space, a substrate 201 and a cathode 206 are disposed a distance d (cm) apart from each other, and gas containing one or more silicon compounds and hydrogen are introduced into the discharge space, and a product Pd of a film forming pressure P (Pa) and d, and a hydrogen flow rate M (SLM) are set so as to meet a relation: 80M+200≦Pd≦160M+333, and an RF power is applied to generate a plasma and a non-monocrystal silicon thin film is formed on the substrate 201 in the discharge space. Thereby, there is provided a thin film formation method making it possible to form an amorphous silicon film in which both a uniform film forming rate of a film distribution facilitating an implementation of a large area and a high conversion efficiency can be obtained while achieving an increase in the film forming rate.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: October 5, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiro Yajima, Masahiro Kanai, Shuichiro Sugiyama
  • Patent number: 6794274
    Abstract: A method for fabricating polycrystalline silicon film on a substrate adds a semitransparent film between the substrate and the silicon film. When the laser irradiates the silicon film, the semitransparent film absorbs a portion of the laser energy, and the semitransparent film is kept at a high temperature during solidification of the silicon film. The silicon film will be kept in a molten state for a long time. Therefore, more time is available for crystal grain growth. The crystal grain size of the polycrystalline silicon film in this method is much larger than the size in normal substrate heating methods.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: September 21, 2004
    Inventor: Wen-Chang Yeh
  • Patent number: 6794275
    Abstract: In a process for forming a silicon-based film on a substrate according to the present invention, the substrate has a temperature gradient in the thickness direction thereof in the formation of the silicon-based film and the temperature gradient is made such that a deposition surface of the substrate has a higher temperature than a backside or the direction of the temperature gradient is reversed. With this configuration, the present invention provides a silicon-based thin film having good properties at a high deposition rate and provides a semiconductor device including it. The present invention also provides a semiconductor device including the silicon-based thin films that has good adhesion and weather-resisting properties and that can be manufactured in a short tact time.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: September 21, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Shotaro Okabe, Masafumi Sano, Akira Sakai, Yuzo Koda, Ryo Hayashi, Shuichiro Sugiyama, Koichiro Moriyama
  • Patent number: 6774018
    Abstract: A plasma is produced in a treatment space by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes separated by a dielectric material, a vapor precursor is mixed with the plasma, and a substrate material is coated by vapor deposition of the vaporized substance at atmospheric pressure in the plasma field. The use of vaporized silicon-based materials, fluorine-based materials, chlorine-based materials, and organo-metallic complex materials enables the manufacture of coated substrates with improved properties with regard to moisture-barrier, oxygen-barrier, hardness, scratch- and abrasion-resistance, chemical-resistance, low-friction, hydrophobic and/or oleophobic, hydrophilic, biocide and/or antibacterial, and electrostatic-dissipative/conductive characteristics.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: August 10, 2004
    Assignee: Sigma Laboratories of Arizona, Inc.
    Inventors: Michael G. Mikhael, Angelo Yializis, Richard E. Ellwanger
  • Publication number: 20040152287
    Abstract: An amorphous or polycrystalline silicon film that does not facilitate the reduction of neighboring oxide may be deposited during semiconductor device/integrated circuit fabrication.
    Type: Application
    Filed: January 31, 2003
    Publication date: August 5, 2004
    Inventors: Adrian B. Sherrill, Weimin Han, Pauline N. Jacob
  • Patent number: 6759267
    Abstract: A method of programming a first memory cell in an array of at least four memory cells in a semiconductor device, each memory cell including a polysilicon gate, first and second spaced-apart diffused regions, a silicide layer provided over the polysilicon gate, an oxide spacer provided contiguous with a vertical sidewall of the polysilicon gate, and a layer of phase change material provided over at least a portion of the silicide layer, contiguous with the oxide spacer, and over the first diffused region.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: July 6, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsu-Shun Chen
  • Publication number: 20040121565
    Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.
    Type: Application
    Filed: June 17, 2003
    Publication date: June 24, 2004
    Inventors: Karsten Wieczorek, Manfred Horstmann, Thomas Feudel
  • Patent number: 6754552
    Abstract: A plurality of measuring devices to obtain numerical information necessary for control in process control of plasma utilizing equipment are connected to a first communication link, a plurality controllers to conduct numerical operations according to the numerical information are connected to a second communication link, and a plurality of control devices to receive control numerical information generated by the controllers to conduct necessary control.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: June 22, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masaharu Nishiumi, Hiromichi Enami
  • Publication number: 20040106269
    Abstract: A thin film deposition method uses a vacuum confinement cup that employs a dense hot filament and multiple gas inlets. At least one reactant gas is introduced into the confinement cup both near and spaced apart from the heated filament. An electrode inside the confinement cup is used to generate plasma for film deposition. The method is used to deposit advanced thin films (such as silicon based thin films) at a high quality and at a high deposition rate.
    Type: Application
    Filed: July 10, 2003
    Publication date: June 3, 2004
    Inventors: Xunming Deng, Henry S. Povolny
  • Publication number: 20040097056
    Abstract: In a process and device for depositing an at least partially crystalline silicon layer a plasma is generated and a substrate (24) is exposed under the influence of the plasma to a silicon-containing source fluid for deposition of silicon therefrom. A pressure drop is applied between a location (12) where the source fluid is supplied and the substrate (24). In addition to the source fluid an auxiliary fluid is also injected which is able to etch non-crystalline silicon atoms. The substrate (24) is exposed to both the source fluid and the auxiliary fluid.
    Type: Application
    Filed: September 29, 2003
    Publication date: May 20, 2004
    Inventors: Edwards Aloys Gerard Hamers, Arno Hendrikus Marie Smets, Mauritius Cornelius Maria Van De Sanden, Dani?euml;l Cornelis Schram
  • Patent number: 6737305
    Abstract: A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (Chemical Vapor Deposition, CVD); forming a second a-Si layer by using a high deposition rate (HDR); and forming an N+Mixed a-Si layer. When the first a-Si layer is formed in the present invention, the flux ratio of H2/SiH4 is adjusted to a range from 0.40 to 1.00 to increase the number of defects in the first a-Si layer. When the TFT is irradiated by the light, the photo leakage current generated in the channel layer is trapped in the defects in the first a-Si layer. Therefore, the TFT photo leakage current can be significantly reduced.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: May 18, 2004
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Yu-Chou Lee, Yi-Tsai Hsu
  • Publication number: 20040092086
    Abstract: A plasma 10 is generated within a film formation chamber 2, and mainly a nitrogen gas 11 is excited within the film formation chamber 2. Then, the excited nitrogen gas 11 is mixed with a diborane gas 13 diluted with a hydrogen gas, and evaporated carbon obtained by controlled heating of a winding-shaped carbon heater 14a, to react them, thereby forming a boron carbonitride film 15 on a substrate 4. Thus, the boron carbonitride film 15 excellent in moisture absorption resistance, excellent in mechanical and chemical resistance, high in thermal conductivity, and having a low relative dielectric constant &kgr; can be formed stably with good adhesion, and speedily over a uniform large area, regardless of the type of the film.
    Type: Application
    Filed: September 23, 2003
    Publication date: May 13, 2004
    Inventors: Hitoshi Sakamoto, Noriaki Ueda, Takashi Sugino
  • Patent number: 6730547
    Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: May 4, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Allen McTeer
  • Patent number: 6716725
    Abstract: A wafer W is placed on a lower electrode 108 provided inside a processing chamber 102 of a CVD apparatus 100 and is heated to achieve a temperature equal to or greater than 350° C. and lower than 450° C. SiH4 and SiF4 with both their flow rates set at 20 sccm, B2H6 with its flow rate set at 7 sccm, O2 with its flow rate set at 200 sccm and Ar with its flow rate set at 400 sccm are introduced into the processing chamber 102, and a pressure within the range of 0.01 Torr˜10 Torr is set. 20 W/cm2 power at a frequency of 27.12 MHz and 10 W/cm2 power at a frequency of 400 kHz are respectively applied to an upper electrode 116 and the lower electrode 108 to generate plasma, and a layer insulating film 204 constituted of an SiOB film containing F is formed on the wafer W.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: April 6, 2004
    Assignee: Tokyo Electron Limited
    Inventor: Hiraku Ishikawa
  • Publication number: 20040053479
    Abstract: The objective of the present invention is to provide a plasma CVD method and plasma CVD apparatus, which makes it possible to form thin films of excellent uniform thickness on both surfaces of a substrate without the step of turning a substrate over.
    Type: Application
    Filed: July 22, 2003
    Publication date: March 18, 2004
    Inventor: Norikazu Ito
  • Patent number: 6703264
    Abstract: A method of manufacturing a semiconductor device that forms laminate layers includes the steps of reducing contamination containing the single bond of carbon on at least one part of a surface on which the laminate films are formed by activated hydrogen before the laminate films are formed, and forming the laminate films on the surface on which the laminate films are formed.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: March 9, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsunori Sakama, Takeshi Fukada
  • Patent number: 6689668
    Abstract: Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 10, 2004
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventors: Mohamed el-Hamdi, Tony T. Phan, Luther Hendrix, Bradley T. Moore
  • Patent number: 6680262
    Abstract: A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming a dielectric layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: January 20, 2004
    Assignee: Intel Corporation
    Inventors: Ebrahim Andideh, Kevin L. Peterson
  • Patent number: 6677222
    Abstract: A first layer made of polysilicon is formed on the surface of an underlying substrate. The surface of the first layer is exposed to an environment which etches silicon oxide. If the surface of the first layer is covered with a silicon oxide film, the silicon oxide film is removed. An energy is supplied to the first layer, the energy allowing silicon crystal to re-grow. Solid phase growth of silicon occurs in the first layer to planarize the surface thereof. A polysilicon film having small root mean square of roughness can be formed.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: January 13, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasuyoshi Mishima, Katsuyuki Suga, Michiko Takei, Akito Hara
  • Publication number: 20030224562
    Abstract: A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (Chemical Vapor Deposition, CVD); forming a second a-Si layer by using a high deposition rate (HDR); and forming an N+Mixed a-Si layer. When the first a-Si layer is formed in the present invention, the flux ratio of H2/SiH4 is adjusted to a range from 0.40 to 1.00 to increase the number of defects in the first a-Si layer. When the TFT is irradiated by the light, the photo leakage current generated in the channel layer is trapped in the defects in the first a-Si layer. Therefore, the TFT photo leakage current can be significantly reduced.
    Type: Application
    Filed: January 27, 2003
    Publication date: December 4, 2003
    Inventors: YU-CHOU LEE, YI-TSAI HSU
  • Patent number: 6653212
    Abstract: A thin film forming apparatus S having a vacuum chamber 1, a substrate 10, a thermal catalyst 5, and a heating means 5a for heating this thermal catalyst 5, wherein a gas introduction system 3 for feeding the gas is connected in the vacuum chamber 1, the gas is fed from this gas introduction system 3 to the vacuum chamber 1, and thin films are formed on the surface of the substrate 10 by utilizing a thermal decomposition reaction or catalytic reaction by the thermal catalyst 5, the gas introduction system 3 is for introducing a carrier gas containing hydrogen and a material gas for forming the thin film on the substrate 10, and the carrier gas is constantly fed into the vacuum chamber 1 at least during the formation of the thin film.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: November 25, 2003
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto
  • Patent number: 6649495
    Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: November 18, 2003
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Yuhko Nishimoto, Tomomi Suzuki, Hiroshi Ikakura, Kazuo Maeda
  • Patent number: 6638839
    Abstract: A thin film deposition method uses a vacuum confinement cup that employs a dense hot filament and multiple gas inlets. At least one reactant gas is introduced into the confinement cup both near and spaced apart from the heated filament. An electrode inside the confinement cup is used to generate plasma for film deposition. The method is used to deposit advanced thin films (such as silicon based thin films) at a high quality and at a high deposition rate.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: October 28, 2003
    Assignee: The University of Toledo
    Inventors: Xunming Deng, Henry S. Povolny
  • Patent number: 6632726
    Abstract: To perform a film formation process, source RF power is applied to a coil to generate a plasma in a processing chamber. Subsequently, O2 gas and SiH4 gas are introduced into the processing chamber. Bias RF power is then applied to a support member to cause permeation of a wafer W by the plasma. At the end of the film formation, the application of the bias RF power to the support member is stopped while the O2 gas and the SiH4 gas are kept introduced into the processing chamber. After that, the introduction of the SiH4 gas is stopped, and the introduction of the O2 gas is also stopped. Then, the application of the source RF power to the coil is stopped. This can reduce plasma damage to the substrate to be processed.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 14, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Michio Aruga, Atsushi Tabata
  • Publication number: 20030176011
    Abstract: A non-Si non-C-based gas is heated by a thermal catalysis body provided in a gas introduction channel, and the heated non-Si non-C-based gas and a material-based gas comprising Si and/or C are separately introduced into a film deposition space through a showerhead having a plurality of gas effusion ports, and in the film deposition space, a plasma space is formed by a nonplanar electrode connected to a radio frequency power supply, thereby forming a film on a substrate. Formation of high-quality Si-based films and C-based films can thus be accomplished at high deposition rate over large area with uniform film thickness and homogeneous quality. Also, highly efficient devices including photoelectric conversion devices represented by solar cells can be manufactured at low-cost by the use of such films.
    Type: Application
    Filed: February 20, 2003
    Publication date: September 18, 2003
    Applicant: KYOCERA CORPORATION
    Inventors: Koichiro Niira, Hirofumi Senta, Hideki Hakuma, Hiroki Okui
  • Publication number: 20030162373
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Application
    Filed: March 6, 2003
    Publication date: August 28, 2003
    Applicant: Matsushita Elec. Ind. Co. Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Publication number: 20030157754
    Abstract: A hydrogenation method that utilizes plasma directly exposes a crystalline semiconductor film to the plasma, and therefore involves the problem that the crystalline semiconductor film is damaged by the ions generated simultaneously in the plasma. If a substrate is heated to 400° C. or above to recover this damage, hydrogen is re-emitted from the crystalline semiconductor film.
    Type: Application
    Filed: November 5, 2002
    Publication date: August 21, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Taketomi Asami, Hidehito Kitakado, Yasuyuki Arai
  • Publication number: 20030153165
    Abstract: The method of the present invention is a method of forming a silicon-based semiconductor layer by introducing a source gas into a vacuum vessel and forming a silicon-based semiconductor layer containing a microcrystal on a substrate introduced into the vacuum vessel by plasma CVD, which comprises a first step of forming a first region with a source gas containing halogen atoms, and a second step of forming a second region on the first region under a condition where the source gas containing halogen atoms in the second step is lower in gas concentration than that of the first step, thereby providing a method of forming a silicon-based semiconductor layer having an excellent photoelectric characteristic at a film forming rate of an industrially practical level and a photovoltaic element using the silicon-based semiconductor layer formed by the method.
    Type: Application
    Filed: October 24, 2001
    Publication date: August 14, 2003
    Inventors: Takaharu Kondo, Masafumi Sano, Akira Sakai, Yasuyoshi Takai, Ryo Hayashi, Toshihiro Yamashita
  • Publication number: 20030143822
    Abstract: A silicon-based film is formed superimposing a direct-current potential on the high-frequency power to set the potential of the high-frequency power feed section to a potential which is lower by V1 than the ground potential; the V1 satisfying |V2|≦|V1|≦50×|V2|, where V2 is the potential difference from the ground potential, produced in the electrode in the state the plasma has taken place under the same conditions except that the direct-current potential is not superposed on the high-frequency power and the electrode is brought into a non-grounded state. This can provide a silicon-based film having superior characteristics at a high film formation rate, and a semiconductor device making use of this silicon-based film, having superior adherence, environmental resistance, and can enjoy a short tact time at the time of manufacture.
    Type: Application
    Filed: June 12, 2002
    Publication date: July 31, 2003
    Inventors: Takaharu Kondo, Masafumi Sano, Akira Sakai, Tadashi Sawayama, Ryo Hayashi, Shuichiro Sugiyama, Hiroyuki Ozaki, Yoshinori Sugiura
  • Publication number: 20030096098
    Abstract: A non-single crystalline semiconductor material includes coordinatively irregular structures characterized by distorted chemical bonding, reduced dimensionality and novel electronic properties. A process for forming the material permits variation of the size, concentration and spatial distribution of coordinatively irregular structures. The electronic properties of the material can be changed by controlling the characteristics of the coordinatively irregular structures.
    Type: Application
    Filed: October 5, 2001
    Publication date: May 22, 2003
    Inventors: Stanford R. Ovshinsky, Boil Pashmakov, David V. Tsu
  • Patent number: 6566159
    Abstract: A method of manufacturing a tandem thin-film solar cell is provided, the solar cell including a plurality of photoelectric conversion units stacked on a substrate, the photoelectric conversion units each having a p-type layer, an i-type photoelectric conversion layer and an n-type layer deposited in this order from a light-incident side of the solar cell, and at least a rear unit among the photoelectric conversion units that is furthest from the light-incident side being a crystalline unit including a crystalline i-type photoelectric conversion layer. The manufacturing method includes the steps of forming at least one of the units on the substrate by plasma CVD and immediately thereafter forming an i-type boundary layer to a thickness of at most 5 nm by plasma CVD, and thereafter removing the substrate into the atmosphere to expose a surface of the i-type boundary layer to the atmosphere and then forming a crystalline unit on the i-type boundary layer by plasma CVD.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: May 20, 2003
    Assignee: Kaneka Corporation
    Inventors: Toru Sawada, Masashi Yoshimi
  • Patent number: 6562702
    Abstract: Provided is a method and apparatus for the production of a semiconductor device, the method and the apparatus producing a high quality and highly functional semiconductor device efficiently at low temperatures in a short time and also a high quality and highly functional semiconductor device produced by the method and apparatus. The semiconductor device is produced by forming a film of a nitride compound on a substrate having heat resistance at 600° C. or less, wherein the nitride compound includes one or more elements selected from group IIIA elements of the periodic table and a nitrogen atom and produces photoluminescence at the band edges at room temperature.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: May 13, 2003
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Shigeru Yagi
  • Patent number: 6563133
    Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B2H6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/M2 at room temperature, 900 mJ/M2 at 150° C., and 1800 mJ/M2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: May 13, 2003
    Assignee: Ziptronix, Inc.
    Inventor: Qin-Yi Tong
  • Patent number: 6548380
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: April 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi