Abstract: Provided is a photoelectric conversion element including a photoconductor containing a complex of a conductive polymer and/or polymer semiconductor and a protein containing at least one dye having a long-lived excited state.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) device are provided. In one embodiment, the MEMS device fabrication method includes forming a via opening extending through a sacrificial layer and into a substrate over which the sacrificial layer has been formed. A body of electrically-conductive material is deposited over the sacrificial layer and into the via opening to produce an unpatterned transducer layer and a filled via in ohmic contact with the unpatterned transducer layer. The unpatterned transducer layer is then patterned to define, at least in part, a primary transducer structure. At least a portion of the sacrificial layer is removed to release at least one movable component of the primary transducer structure. A backside conductor, such as a bond pad, is then produced over a bottom surface of the substrate and electrically coupled to the filled via.

Abstract: A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process.

Abstract: A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate.

Abstract: A ferromagnetic tunnel junction structure comprising a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the tunnel barrier layer includes a crystalline non-magnetic material having constituent elements that are similar to those of an crystalline oxide that has spinel structure as a stable phase structure; the non-magnetic material has a cubic structure having a symmetry of space group Fm-3m or F-43m in which atomic arrangement in the spinel structure is disordered; and an effective lattice constant of the cubic structure is substantially half of the lattice constant of the oxide of the spinel structure.

Abstract: A method for fabricating an image panel for a hyperspectral camera that is configured to scan a scene and obtain spectral image data over as defined range of wavelengths. At least one companion sensor is first fabricated on a planar imaging surface of a silicon die. At least as region of the silicon die is then back thinned to a diffraction thickness that is suitable for a diffraction slit. A diffraction slit is then formed in the thinned region so that the diffraction slit penetrates the silicon die in the thinned region, and the diffraction slit is co-planar with the imaging surface of the silicon die.

Abstract: An embedded micro-electro-mechanical system (MEMS) (100) comprising a semiconductor chip (101) embedded in an insulating board (120), the chip having a cavity (102) including a radiation sensor MEMS (105), the opening (104) of the cavity at the chip surface covered by a plate (110) transmissive to the radiation (150) sensed by the MEMS. The plate surface remote from the cavity having a bare central area, to be exposed to the radiation sensed by the MEMS in the cavity, and a peripheral area covered by a metal film (111) touching the plate surface and a layer (112) of adhesive stacked on the metal film.

Abstract: A method of manufacturing an organic light emitting diode (OLED) display includes forming an upper electrode power source line outside of a pixel area over a substrate, forming a lower electrode in the pixel area, forming at least one layer of an organic material layer in the pixel area and areas outside of the pixel area, forming an upper electrode in the pixel area, selectively removing portions of the organic material layer that are exposed outside of the upper electrode, thereby exposing the upper electrode power source line, and coating a conductive material between the upper electrode and the upper electrode power source line in a normal pressure condition such that the conductive material overlaps the upper electrode and the upper electrode power source line, thereby forming a connection portion.

Abstract: Provided is a semiconductor device of normally-off operation type having a low on-resistance. An epitaxial substrate for it includes: a base substrate; a channel layer made of a first group-III nitride having a composition of Inx1Aly1Gaz1N at least containing Al and Ga and x1=0 and 0?y1?0.3; and a barrier layer made of a second group-III nitride having a composition of Inx2Aly2Gaz2N at least containing In and Al. The composition of the second group-III nitride is, in a ternary phase diagram for InN, AlN, and GaN, in a certain range that is determined in accordance with the composition of the first group-III nitride. The barrier layer has a thickness of 3 nm or less. A low-crystallinity insulating layer is further formed on the barrier layer. The low-crystallinity insulating layer is made of silicon nitride and has a thickness of 3 nm or less.

Abstract: Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell.

Abstract: A method for manufacturing a semiconductor light emitting element (1) which includes a first step of forming a first n-type semiconductor layer (12c) on a substrate (11) and a second step of sequentially forming a regrowth layer (12d) of the first n-type semiconductor layer (12c), a second n-type semiconductor layer (12b), a light emitting layer (13), and a p-type semiconductor layer (14) on the first n-type semiconductor layer (12c). In the step of forming the second n-type semiconductor layer (12b), a step (1) of supplying Si less than that forming the regrowth layer (12d) as a dopant to form a first layer of the second n-type semiconductor layer and a step (2) of supplying the Si more than that in the step (1) to form a second layer of the second n-type semiconductor layer are performed in this order.

Abstract: A housing for integrated devices that includes an air-release mechanism is disclosed. This is achieved, in various embodiments, by forming a vent hole in a package substrate, and arranging a package lid over the package substrate. The vent hole allows air to be released from within the cavity package, thereby ensuring that the package lid remains stably affixed to the package substrate despite increased temperatures during processing. The vent hole may be sealed upon mounting the package onto a mounting substrate.

Abstract: A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.

Abstract: A method for making a current-perpendicular-to-the-plane (CPP) magnetoresistive (MR) sensor that has a reference layer with low coercivity includes first depositing, within a vacuum chamber, a seed layer and an antiferromagnetic layer on a substrate without the application of heat. The substrate with deposited layers is then heated to between 200-600° C. for between 1 to 120 minutes. The substrate with deposited layers is then cooled, preferably to room temperature (i.e., below 50° C., but to at least below 100° C., in the vacuum chamber. After cooling of the antiferromagnetic layer, the ferromagnetic reference layer is deposited on the antiferromagnetic layer. Then the substrate with deposited layers is removed from the vacuum chamber and subjected to a second annealing, in the presence of a magnetic field, by heating to a temperature between 200-400° C. for between 0.5-50 hours.

Abstract: In at least one embodiment of the invention, a method of manufacturing an integrated circuit including a microelectromechanical system (MEMS) device includes forming a first structural layer above at least one semiconductor device formed on a substrate. The method includes forming a second structural layer above the first structural layer. The second structural layer has a thickness substantially greater than a thickness of the first structural layer. The MEMS device comprises at least one portion of at least one of the first and second structural layers. In at least one embodiment of the invention, the method is carried out at one or more temperatures less than a tolerable threshold temperature for the at least one semiconductor device.

Abstract: A photoelectric device is disclosed. The photoelectric device includes a semiconductor substrate, first and second semiconductor stacks having opposite conductive types and alternately arranged on a first surface of the semiconductor substrate, and a gap insulation layer formed between the first and second semiconductor stacks. An undercut may be formed in the gap insulation layer. A method of manufacturing a photoelectric device is also disclosed.

Abstract: A micro-electromechanical system (MEMS) device can include a substrate and a first beam suspended relative to a substrate surface. The first beam can include a first portion and a second portion that are separated by an isolation joint made of an insulative material. The first and second portions can each include a first semiconductor and a first dielectric layer. The MEMS device can also include a second beam suspended relative to the substrate surface. The second beam can include a second semiconductor and a second dielectric layer to promote curvature of the second beam. The MEMS device can also include a third beam suspended relative to the substrate surface. The third beam consists essentially of a first material. The second beam is configured to move relative to the third beam in response to an acceleration along an axis perpendicular to the surface of the substrate.

Abstract: A method of forming a photosensitive pattern on a substrate with a photosensitive layer disposed thereon may include moving at least one of the substrate and a set of micro-mirrors in a first direction, the set of micro-mirrors being disposed above the substrate and being arranged as an array, the array having a first edge extending in a second direction, the second direction being at an acute angle with respect to the first direction. The method may also include selectively turning on one or more micro-mirrors of the set of micro-mirrors according to a position of the set of micro-mirrors relative to the photosensitive layer, thereby irradiating one or more spot beams on the photosensitive layer. The photosensitive layer exposed by the spot beams is developed to form a photosensitive pattern having an edge portion extending in a third direction crossing the first and second directions.

Abstract: A method of manufacturing a quantum dot layer, and a quantum dot optoelectronic device including the quantum dot layer. The method includes sequentially stacking a self-assembled monolayer, a sacrificial layer, and a quantum dot layer on a source substrate; disposing a stamp on the quantum dot layer; picking up the sacrificial layer, the quantum dot layer and the stamp; and removing the sacrificial layer from the quantum dot layer using a solution that dissolves the sacrificial layer.

Abstract: A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer.

Abstract: A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer.

Abstract: A chip package with isolated pin, isolated pad or isolated chip carrier and a method of making the same are disclosed. In one embodiment a chip package includes a chip, a package encapsulating the chip, pads or pins disposed on a first side of the package and an isolation pad or an isolation pin disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package.

Abstract: Described is a combinational array gas sensor.

Abstract: The present invention generally relates to a magnetic sensor in a read head having a hard or soft bias layer that is uniform in thickness within the sensor stack. The method of making such sensor is also disclosed. The free layer stripe height is first defined, followed by defining the track width, and lastly the pinned layer stripe height is defined. The pinned layer and the hard or soft bias layer are defined in the same process step. This approach eliminates a partial hard or soft bias layer and reduces potential instability issues.

Abstract: The purpose of the present invention is to favorably modify a transparent conductive film and provide a transparent conductive film with few grain boundaries. In the manufacturing method for the transparent conductive film of the present invention, a transparent conductive film 3 is formed on a substrate 2 inside a vacuum chamber 10, after which radiant heat is imparted from a surface modifying device 4 arranged near the substrate 2 to modify the transparent conductive film 3, and the substrate 2 having the modified transparent conductive film 3 is removed from the vacuum chamber 10.

Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

Abstract: A solid-state energy conversion device and method of making is disclosed wherein the solid-state energy conversion device is formed through the conversion of an insulating material. In one embodiment, the solid-state energy conversion device operates as a photovoltaic device to provide an output of electrical energy upon an input of electromagnetic radiation. In another embodiment, the solid-state energy conversion device operates as a light emitting device to provide an output of electromagnetic radiation upon an input of electrical energy. In one example, the photovoltaic device is combined with a solar liquid heater for heating a liquid. In another example, the photovoltaic device is combined with a solar liquid heater for treating water.

Abstract: A semiconductor package includes a wiring board, an electronic component mounted on the wiring board, and an enclosing frame arranged on an upper surface of the electronic component. The enclosing frame includes a basal portion, which has the form of a closed frame and extends along the upper surface of the electronic component, and an adhesion portion, which is wider than the basal portion and is arranged on the upper surface of the basal portion. A cap is adhered to an upper surface of the adhesion portion. A molding resin contacts a lower surface of the adhesion portion and seals the electronic component and the wiring board that are exposed from the enclosing frame.

Abstract: An image sensor includes an epi-layer of a first conductivity type formed in a substrate, a photodiode formed in the epi-layer, and a first doping region of a second conductivity type formed under the photodiode to separate the first doping region from the photodiode.

Abstract: The present invention provides a MEMS and a sensor having the MEMS which can be formed without a process of etching a sacrifice layer. The MEMS and the sensor having the MEMS are formed by forming an interspace using a spacer layer. In the MEMS in which an interspace is formed using a spacer layer, a process for forming a sacrifice layer and an etching process of the sacrifice layer are not required. As a result, there is no restriction on the etching time, and thus the yield can be improved.

Abstract: A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

Abstract: According to an aspect of the invention, an imaging device includes a plurality of photoelectric conversion elements and a read-out portion. The photoelectric conversion elements are arranged above a substrate. The read-out portion reads out signal corresponding to charges which are generated from each of the photoelectric conversion elements. Each of the photoelectric conversion elements includes a first electrode that collects the charge, a second electrode that is disposed opposite to the first electrode, a photoelectric conversion layer that generates the charges and disposed between the first electrode and the second electrode, and an electron blocking layer that is disposed between the first electrode and the photoelectric conversion layer. Distance between the first electrodes of adjacent photoelectric conversion elements is 250 nm or smaller. Each of the electron blocking layers has a change in surface potential of ?1 to 3 eV from a first face to a second face.

Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.

Abstract: The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an embodiment, the first bond ring is a eutectic bond and the second bond ring is at least one of an organic material and a eutectic bond. The second bond ring encircles the first bond ring. The first bond ring provides a hermetic region of the device. In a further embodiment, a plurality of wafers are bonded which include a third bond ring disposed at the periphery of the wafers.

Abstract: An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes.

Abstract: A pH sensor may include a reference electrode including a p-channel field effect transistor (FET) whose gate includes a diamond surface having a hydrogen ion insensitive terminal, and a working electrode.

Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

Abstract: A method of manufacturing a solid-state image sensor, comprising preparing a semiconductor substrate including a photoelectric converter and an insulating film which includes an opening and is formed in a region above the photoelectric converter, depositing a material having a refractive index higher than the insulating film in the opening, and annealing the material deposited in the opening by irradiating the material with one of light and radiation, wherein a light waveguide which is configured to guide an incident light to the photoelectric converter is formed through the depositing and the annealing.

Abstract: A light receiving device includes a microlens 21 located in each of regions corresponding to pixels, the microlens being disposed on a rear surface of an InP substrate 1. The microlens is formed by using a resin material having a range of a transmittance of light in the wavelength region between 0.7 and 3 ?m of 25% or less, the transmittance being 70% or more.

Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.

Abstract: Passivated emitter rear local epitaxy (PERL-e) thin Si solar cells may be formed with a heavily doped epitaxial back surface field (BSF) layer, which is patterned to form well spaced point contacts to the silicon base on the rear of the solar cell. The back side of the cell may be finished with a dielectric passivation layer and a metallization layer for making electrical contact to the cell. PERL-e thick Si solar cells may be formed with heavily doped epitaxial films as the back point contacts, where the point contacts are defined by the provision of a selectively patterned thermal oxide on the rear wafer surface. Furthermore, absorption of longer wavelength, infrared (IR), light in thin silicon solar cells may be improved by the addition of a dielectric stack on the rear surface of the solar cell (a back reflector).

Abstract: A method for fabricating a multiple MEMS device. A semiconductor substrate having a first and second MEMS device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel, can be provided. The first MEMS can be encapsulated within the first cavity and the second MEMS device can be encapsulated within the second cavity. These devices can be encapsulated within a provided first encapsulation environment at a first air pressure, encapsulating the first MEMS device within the first cavity at the first air pressure. The second MEMS device within the second cavity can then be subjected to a provided second encapsulating environment at a second air pressure via the channel of the second cavity.

Abstract: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node.

Abstract: In at least one embodiment, an infrared (IR) sensor comprising a thermopile is provided. The thermopile comprises a substrate and an absorber. The absorber is positioned above the substrate and a gap is formed between the absorber and the substrate. The absorber receives IR from a scene and generates an electrical output indicative of a temperature of the scene. The absorber is formed of a super lattice quantum well structure such that the absorber is thermally isolated from the substrate. In another embodiment, a method for forming an infrared (IR) detector is provided. The method comprises forming a substrate and forming an absorber with a plurality of alternating first and second layers with a super lattice quantum well structure. The method further comprises positioning the absorber about the substrate such that a gap is formed to cause the absorber to be suspended about the substrate.

Abstract: In a method for manufacturing a chemical sensor with multiple sensor cells, a substrate is provided and an expansion inhibitor is applied to the substrate for preventing a sensitive material to be applied to an area on the substrate for building a sensitive film of a sensor cell to expand from said area. The sensitive material is provided and the sensitive film is built by contactless dispensing the sensitive material to said area.

Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.