Abstract: In producing a thin film transistor (TFT), an silicon oxide film is formed as an under film on a glass substrate, and then an amorphous silicon film is formed therein. A metal element which promotes crystallization of silicon is disposed in contact with a surface of the amorphous silicon film. A thermal processing for the amorphous silicon film is performed at a crystallization temperature of the amorphous silicon film or higher. At the thermal processing, a glass substrate is placed on an object having constant flatness. Cooling is performed to obtain a crystalline silicon film wherein the substrate is not distorted and deformed.

Abstract: On a silicon substrate 1 is provided a silicon oxide film 2, on which a polycrystalline silicon film 3 is formed by a low pressure CVD method at a monosilane partial pressure of no more than 10 Pa and a film formation temperature of no lower than 600° C. The polycrystalline silicon film is doped with an impurity such as phosphorus in a concentration of 1×1020 atoms/cm3 to 1×1021 atoms/cm3 to form a phosphosilicate glass film 6, and after removing it, the polycrystalline silicon film is thermally oxidized in an oxidative atmosphere to form a dielectric film 5 on the surface. A polycrystalline silicon film 4 is formed on the dielectric film 5, which is treated as the oriented polycrystalline silicon film 3a to form an oriented polycrystalline silicon film 4a. The oriented polycrystalline silicon film 4a as an upper electrode and the oriented polycrystalline silicon film 3a as a lower electrode are wired to obtain a semiconductor device having a capacitor.

Abstract: A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600° C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized.

Abstract: In one aspect, the invention includes a method of forming a silicon-comprising material having a roughened outer surface. A semiconductive substrate is provided which comprises conductively doped silicon. A layer comprising silicon and germanium is formed over the substrate. The layer is exposed to conditions which cause crystalline grains within it to increase in size until roughness of a surface of the layer is increased. Dopant is out-diffused from the conductively doped silicon and into the crystalline grains of the layer to conductively dope the layer. In another aspect, the invention includes a method of forming a capacitor construction. A substrate is provided and a conductively doped silicon-comprising material is formed to be supported by the substrate. A layer is formed against the conductively doped silicon-comprising material. The layer has an outermost surface, and comprises silicon and germanium. The layer is subjected to conditions which increase a roughness of the outermost surface.

Abstract: A method for forming hemispherical silicon grains on selected surfaces of a silicon layer includes the steps of forming a doped polysilicon layer over a substrate, and then forming amorphous spacers on the sidewalls of the doped polysilicon layer. Thereafter, an ion implantation is carried out to transform the upper portion of the doped polysilicon into an amorphous silicon layer. Finally, hemispherical silicon grains are formed on the upper surface of the amorphous layer lying above the polysilicon layer and the exposed surface of the amorphous spacers.

Abstract: A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical grain structure and distributed at the surface area of the hemispherical grain region.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: A method for producing a polycrystalline silicon structure and a polycrystalline silicon layer to be produced by the method of first forming a primary silicon structure in an amorphous or polycrystalline form, and doping the structure with a dopant, in particular with oxygen, in a concentration exceeding the solubility limit. In a subsequent heat treatment, dopant precipitations are formed which control grain growth in a secondary structure being produced. Such a contact polycrystalline silicon structure can be used, in particular, as a connection of a monocrystalline silicon region.

Abstract: In a method of manufacturing a semiconductor device, an insulating film having an opening is formed on an amorphous film 103 containing silicon therein. After catalytic elements are introduced from the opening, the amorphous film 103 is crystallized. Thereafter elements (phosphorus) selected from Group XV are introduced from the opening, and then a heat treatment is conducted to obtain a film having crystallinity. Thereafter, a portion of the film containing silicon into which the catalytic elements and phosphorus is introduced are removed.

Abstract: A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.

Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, By existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Abstract: A flash memory has diffused layers extending in a column direction to form channel regions between each two of the diffused layers, field oxide films extending in a row direction to divide the channel regions into separate channels arranged in a matrix, a floating gate disposed for each channel as a split gate, and a strip control gates extending in the row direction and overlying each row of the split floating gate. Each of the floating gates has a lower layer having a lower impurity concentration and an upper layer having a higher impurity concentration. The lower impurity concentration of the lower layer prevents fluctuations in device characteristics while the higher concentration of the upper layer enhances etch rates in two etching process for forming the floating gates of a matrix.

Abstract: A method of manufacturing a thin-film solar cell, comprising the steps or: forming an amorphous silicon film on a substrate; holding a metal element that accelerates the crystallization of silicon in contact with the surface of the amorphous silicon film; subjecting the amorphous silicon film to a heat treatment to obtain a crystalline silicon film; depositing a silicon film to which phosphorus has been added in close contact with the crystalline silicon film; and subjecting the crystalline silicon film and the silicon film to which phosphorus has been added to a heat treatment.

Abstract: The present invention provides a method for depositing polycrystal Si films, including n-type and p-type polycrystal Si films, using a material gas, a doping gas, and hydrogen gas. This method comprises a film-forming time-period having:(a) a time-period for depositing a film;(b) a time-period for diffusing dopants in the deposited film; and(c) a time-period for treating the film surface with hydrogen plasma. According to this method, an n-type or p-type polycrystal Si film with excellent crystallinity can be provided using the material gas and the doping gas. Further, this method is able to proceed at a low temperature and achieve satisfactory structural relaxation of the resulting film.

Abstract: A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening.

Abstract: A method of forming a silicon layer having a roughened outer surface includes, a) providing a substantially amorphous silicon layer over a substrate, the amorphous silicon layer having an outer surface; b) providing a seeding layer over the amorphous silicon layer outer surface; and c) annealing the amorphous silicon layer and seeding layer under temperature and pressure conditions effective to transform said amorphous layer into a silicon layer having a roughened outer surface. The amorphous silicon layer is preferably provided by providing a first silicon source gas (i.e., silane) within a chemical vapor deposition reactor under first reactive temperature and pressure conditions effective to deposit a substantially amorphous first silicon layer on the substrate. After the amorphous silicon layer deposition, a second silicon source gas (i.e.

Abstract: An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon remains a high resistance and a good insulator.

Abstract: A semiconductor processing method of providing a doped polysilicon layer atop a substrate includes, a) depositing a layer of substantially amorphous silicon having a dopant concentration of less than or equal to about 1.times.10.sup.16 atoms/cm.sup.3 over a substrate to a thickness of less than or equal to about 30 Angstroms; b) depositing a layer of silicon over the amorphous silicon layer in a manner which in situ dopes such layer to a dopant concentration of greater than about 1.times.10.sup.16 atoms/cm.sup.3 ; and c) providing the deposited silicon layers to be polycrystalline. Preferably, the substantially amorphous layer is entirely undoped as-deposited. The invention is believed to have greatest applicability to provision of thin film doped polysilicon layers having thicknesses of less than or equal to about 100 Angstroms. Accordingly, the combined thickness of the deposited silicon layers is preferably less than or equal to about 100 Angstroms.

Abstract: A MOS transistor structure is provided in which the source/drain contacts are to raised polysilicon and are located entirely over field isolation. Contact integrity is maintained because the contact is located on field oxide, rather than in direct contact with the substrate junction diffusion area. Conventional contact metal spiking into the junction area is also eliminated. Contact overetch during formation of the contact opening can be increased to insure a clean contact surface because the contact is made to the raised poly regions. Furthermore, the contact barrier is no longer essential for maintaining contact reliability, because the contact is located away from the active junction.

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.

Abstract: A method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The method comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 .OMEGA.-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600.degree. to 900.degree. C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500.

Abstract: A method and apparatus of forming local interconnects in a MOS process deposits a layer of polysilicon over an entire region after several conventional MOS processing steps. The region is then masked to provide protected regions and unprotected regions. The mask may be used to define local interconnects and other conductive elements such as the source and drain contact regions for a MOS transistor. After masking, the region is bombarded with atoms to enhance the oxidation potential of the unprotected regions. The masking is removed and the substrate is then exposed to oxidizing conditions which cause the unprotected regions to rapidly oxidize to form a thick oxide layer. The formerly protected polysilicon regions may then be doped to render them conductive.

Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer. The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.