Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.

Abstract: A method of MBE growth of a semiconductor layer structure comprises growing a first (Al,Ga)N layer (step 13) over a substrate at the first substrate temperature (T1) using ammonia as the nitrogen precursor. The substrate is then cooled (step 14) to a second-substrate temperature (T2) which is lower than the first substrate temperature. An (In,Ga)N quantum well structure is then grown (step 15) over the first (Al,Ga)N layer by MBE using ammonia as the nitrogen precursor. The supply of ammonia to the substrate is maintained continuously during the first growth step, the cooling step, and the second growth step. After completion of the growth of the (In,Ga)N quantum well structure, the substrate may be heated to a third temperature (T3) which is greater than the second substrate temperature (T2). A second (Al,Ga)N layer is then grown over the (In,Ga)N quantum well structure (step 17).

Abstract: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.

Abstract: A method for the production of an SiC single crystal includes the steps of growing a first SiC single crystal in a first direction of growth on a first seed crystal formed of an SiC single crystal, disposing the first SiC single crystal grown on the first seed crystal in a direction parallel or oblique to the first direction of growth and cutting the disposed first SiC single crystal in a direction of a major axis in a cross section perpendicular to the first direction of growth to obtain a second seed crystal, using the second seed crystal to grow thereon in a second direction of growth a second SiC single crystal to a thickness greater than a length of the major axis in the cross section, disposing the second SiC single crystal grown on the second seed crystal in a direction parallel or oblique to the second direction of growth and cutting the disposed second SiC single crystal in a direction of a major axis in a cross section perpendicular to the second direction of growth to obtain a third seed crystal, u

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.

Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.

Abstract: A method of forming a deposited film according to the present invention includes: introducing a starting gas into a discharge space in a reaction vessel; and applying electric power to generate discharge to decompose the starting gas, wherein, when a self-bias voltage value which is generated at an electrode applied with first electric power reaches a preset threshold, second electric power higher than the first electric power is applied to the electrode to change the self-bias voltage value to another self-bias voltage value larger in absolute value than the threshold, and the deposited film is formed.

Abstract: A single crystalline structure includes a first insulation interlayer pattern, a first epitaxial layer pattern, a second insulation interlayer pattern, and a second epitaxial layer pattern. The first insulation interlayer pattern includes a contact hole that exposes a single crystalline seed. The first epitaxial layer pattern fills up the contact hole. The second insulation interlayer pattern is formed on the first insulation interlayer pattern and the first epitaxial layer pattern. The second insulation interlayer pattern has a trench that partially exposes the first epitaxial layer pattern and has an end disposed over an upper surface of the first epitaxial layer pattern. The second epitaxial layer pattern fills up the trench. Thus, voids are not generated in the second epitaxial layer pattern and a semiconductor device having the single crystalline structure exhibits improved reliability.

Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

Abstract: A method of assembling large numbers of nanoscale structures in pre-determined ways using fluids or capillary lithography to control the patterning and arrangement of the individual nanoscale objects and nanostructures formed in accordance with the inventive method are provided. In summary, the current method uses the controlled dispersion and evaporation of fluids to form controlled patterns of nanoscale objects or features anchored on a substrate, such as nanoscale fibers like carbon nanotubes.

Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.

Abstract: A method of manufacturing an electromagnetic (EM) waveguide capable of guiding a wave along a pre-defined propagation path is described. The method includes providing a core region that extends along the propagation path and printing a colloidal crystal comprised of first particles on the waveguide core region.

Abstract: A semiconductor substrate (1) of the present invention is made of nitrides of group III metals having wurtzite crystal structure and is grown in vapor phase either on a (0001) oriented foreign substrate (2), lattice mismatched to the semiconductor substrate materials, or on existing (0001) oriented highly dislocated layer (3) of the semiconductor substrate materials and has a highly reduced dislocation density.

Abstract: There is provided a method for preparing an AlGaN crystal layer having an excellent surface flatness. A buffer layer effective in stress relaxation is formed on a template substrate having a surface layer that is flat at a substantially atomic level and to which in-plane compressive stress is applied, and an AlGaN layer is formed on the buffer layer, so that an AlGaN layer can be formed that is flat at a substantially atomic level. Particularly when the surface layer of the template substrate includes a first AlN layer, a second AlN layer may be formed thereon at a temperature of 600° C. or lower, while a mixed gas of TMA and TMG is supplied in a TMG/TMA mixing ratio of 3/17 or more to 6/17 or less, so that a buffer layer effective in stress relaxation the can be formed in a preferred manner.

Abstract: The present invention provides for photonic crystals comprising nanostructures grown on a conducting or insulating substrate, and a method of making the same. The photonic crystals can be used in components such as artificial photonic crystals for photonic devices and circuits.

Abstract: The present invention relates to a two-wavelength semiconductor laser device, more particularly, to a fabrication method of a multi-wavelength semiconductor laser device. In this method, a substrate having an upper surface separated into at least first and second areas is provided. Then, a first dielectric mask on the substrate is formed to expose only the first area. Then, epitaxial layers for a first semiconductor laser are grown on the first area of the substrate. Then, a second dielectric mask on the substrate is formed to expose only the second area. Then, epitaxial layers for a second semiconductor laser are grown on the second area of the substrate.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: An epitaxial silicon wafer includes a bulk wafer having a first doping concentration, a first epitaxial layer formed over the bulk wafer, the first epitaxial layer having a second doping concentration which is higher than the first doping concentration, and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial layer having a third doping concentration which is lower than the second doping concentration.

Abstract: A method of growing a crystal (for example, a GaN system compound semiconductor crystal) on a substrate at least includes forming a first crystalline layer (a GaN system buffer layer), forming a second crystalline layer (a GaN system intermediate layer) and forming a third crystalline layer (a GaN system thick film layer). The three crystalline layers are respectively reared on conditions different from one another.

Abstract: A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Abstract: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another.

Abstract: In a semiconductor light emitting device such as a semiconductor laser using nitride III-V compound semiconductors and having a structure interposing an active layer between an n-side cladding layer and a p-side cladding layer, the p-side cladding layer is made of an undoped or n-type first layer 9 and a p-type second layer 12 that are deposited sequentially from nearer to remoter from the active layer. The first layer 9 is not thinner than 50 nm. The p-type second layer 12 includes a p-type third layer having a larger band gap inserted therein as an electron blocking layer. Thus the semiconductor light emitting device is reduced in operation voltage while keeping a thickness of the p-side cladding layer necessary for ensuring favorable optical properties.

Abstract: The present red light-emitting device includes a substrate with a first window layer, a silicon dioxide layer positioned on the first window layer, a plurality of silicon nanocrystals distributed in the silicon dioxide layer, a second window layer, a transparent conductive layer and a first ohmic contact electrode positioned in sequence on the silicon dioxide layer, and a second ohmic contact electrode positioned on the bottom surface of the substrate. The present method forms a sub-stoichiometric silica (SiOx) layer on a substrate, wherein the numerical ratio (x) of oxygen atoms to silicon atoms is smaller than 2. A thermal treating process is then performed in an oxygen atmosphere to transform the SiOx layer into a silicon dioxide layer with a plurality of silicon nanocrystals distributed therein. The thickness of the silicon dioxide layer is between 1 and 10,000 nanometers, and the diameter of the silicon nanocrystal is between 3 and 5 nanometers.

Abstract: The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, prevent worsening of surface and interface roughness during heat treatment of a device production process and so forth. A production method of a semiconductor substrate W, in which SiGe layers 2 and 3 are formed on an Si substrate 1, is comprised of a heat treatment step in which heat treatment is performed either during or after the formation of the SiGe layers by epitaxial growth, at a temperature that exceeds the temperature of the epitaxial growth, and a polishing step in which irregularities in the surface formed during the heat treatment are removed by polishing following formation of the SiGe layers.

Abstract: There are now provided thin-film solar cells and method of making. The devices comprise a low-cost, low thermal stability substrate with a semiconductor body deposited thereon by a deposition gas. The deposited body is treated with a conversion gas to provide a microcrystalline silicon body. The deposition gas and the conversion gas are subjected to a pulsed electromagnetic radiation to effectuate deposition and conversion.

Abstract: A vertical-cavity, surface-emission-type laser diode includes an optical cavity formed of an active region sandwiched by upper and lower reflectors, wherein the lower reflector is formed of a distributed Bragg reflector and a non-optical recombination elimination layer is provided between an active layer in the active region and the lower reflector.

Abstract: A method includes epitaxially growing a semiconductor layer with a free surface and performing an anneal that reduces atomic roughness on the free surface. The free surface has an orientation with respect to lattice axes of the layer for which atoms in flat regions of the free surface have more chemical bonds to the layer than do, at least, some of the atoms at edges of monolayer steps on the free surface.

Abstract: The invention includes methods of forming epitaxially-grown semiconductive material having a flattened surface, and methods of incorporating such material into trenched regions and elevated/source drain regions. A method of forming epitaxially-grown semiconductive material having a flattened surface can include the following. Initially, a single crystal first semiconductor material is provided. A second semiconductive material is epitaxially grown from a surface of the first semiconductor material. The epitaxial growth is stopped, and subsequently an upper surface of the second semiconductor material is exposed to at least one hydrogen isotope to reduce curvature of (i.e., flatten) a surface of the second semiconductor material.

Abstract: A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.

Abstract: High quality epitaxial layers of monocrystalline perovskite materials (18) can be grown overlying monocrystalline substrates (12) such as gallium arsenide wafers by forming a metal template layer (16) on the monocrystalline substrate. The structure includes a metal-containing layer (16) to mitigate unwanted oxidation of underlying layers and a low-temperature seed layer (19) that prevents degradation of an epitaxial layer (14) during growth of the perovskite layer (18).

Abstract: Field-Effect Transistor Based on Embedded Cluster Structures and Process for Its Production In field-effect transistors, semiconductor clusters, which can extend from the source region to the drain region and which can be implemented in two ways, are embedded in one or a plurality of layers. In a first embodiment, the semiconductor material of the adjacent channel region can be strained by the clusters and the effective mass can thus be reduced by altering the energy band structure and the charge carrier mobility can be increased. In a second embodiment, the clusters themselves can be used as a canal region. These two embodiments can also appear in mixed forms. The invention can be applied to the Si material system with SiGe clusters or to the GaAs material system with InGaAs clusters or to other material systems.

Abstract: A main surface of a base substrate of sapphire is selectively formed an irregular region on the main surface. Then, a semiconductor layer of gallium nitride is grown to fill recessed portions in the irregular region of the base substrate and make the upper surface even. Then, a laser beam is irradiated upon the interface between the semiconductor layer and the irregular region of the base substrate to separate the semiconductor layer from the base substrate. As a result, a nitride semiconductor substrate is produced from the semiconductor layer.

Abstract: A method of manufacturing a semiconductor device, which method comprises the step of epitaxially growing a stack comprising an n-type doped layer of a semiconductor material followed by at least one further layer of a semiconductor material, the stack being grown in one continuous cycle.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: The invention provides a method of pattering a substrate, in which a first material in solution is deposited on the substrate. The composition of the solution of the first material is selected so it dries to leave a residue of the first material on the substrate, the residue comprising a thin film in the centre and a ridge around the perimeter. The residue is etched to remove the thin film, leaving the ridge on the substrate. After etching the ridge is hydrophobic and the substrate is hydrophilic. An aqueous solution of a second material is then deposited on both sides of the ridge. After the aqueous solution has dried, the ridge is removed, leaving a layer of the second material on the substrate, the layer having a narrow gap therethrough. The layer may be used for the source and drain electrodes of an organic thin film transistor.

Abstract: A extreme ultraviolet (EUV) mask blank having a reflective stack formed by depositing repeated periods of a silicon layer, a first barrier layer, a molybdenum layer, and a second barrier layer using atomic layer deposition is discussed. Precursors using silane and hydrogen are used to form the silicon layer. The first and second barrier layers are preferably different thicknesses of the same material and can be formed using precursors including diborane and methane. In one embodiment, the molybdenum layer is formed using precursors including hydrogen and molybdenum pentachloride or molybdenum pentaiodide. An EUV mask used to pattern a photoresist layer to form an integrated circuit is manufactured from the EUV mask blank.

Abstract: In a method of manufacturing oxide thin film by adsorbing or depositing oxide forming starting material on a substrate followed by oxide formation, by using water in a liquid state to manufacture the oxide thin film, the advantages of the ALD method are utilized while resolving the tendency to leave impurities in the oxide film produced that is a drawback thereof, so that oxide thin film can be obtained having a reduced concentration of impurities.

Abstract: A production method of silicon which comprises the steps of bringing a silane into contact with a surface of a substrate so as to cause silicon to be deposited while the surface of the substrate is heated to and kept at a temperature lower than the melting point of the silicon, and raising the temperature of the surface of the substrate so as to cause a portion or all of the deposited silicon to melt and drop from the surface of the substrate and be recovered.

Abstract: A method of coating a semiconductor substrate material with a coating material consisting of the steps of mixing an adhesion promoter with a coating material and applying the mixture to a semiconductor substrate material. The invention also includes means for coating a semiconductor substrate material with a coating material comprising means for mixing adhesion promoters with coating materials and means for applying the mixture of adhesion promoters and coating materials to a semiconductor substrate.

Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.

Abstract: A method and an apparatus for growing a layer on one surface of a wafer by liquid phase deposition are provided. At first, a first wafer is putted on a first wafer-holder by its first surface. Then, a growth-liquid vessel having a first opening at the bottom is mounted on the first wafer-holder. Thereafter, a growth liquid is poured into the growth-liquid vessel to expose a second surface of the first wafer to the growth liquid for growing the layer on the second surface of the first wafer. Then, the, first wafer is taken out from the first wafer-holder to obtain a wafer with a layer grown only on one surface.

Abstract: A substrate for a semiconductor device includes a crystalline silicon substrate; an insulative silicon compound layer thereon and a crystalline insulation layer on the insulative silicon compound layer, wherein the insulative silicon compound layer contains not more than 10 at % of component element of a material constituting the crystalline insulation layer, the component element being provided in the insulative silicon compound layer by diffusion.

Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Abstract: A substrate such as a sapphire substrate or the like is set to a molecular beam epitaxy (MBE) apparatus. Next, the temperature of the substrate is elevated to the temperature which is lower than the temperature at which a predetermined ZnO based oxide semiconductor layer (i.e. function layer) is grown (S1). Then, raw materials containing oxygen radical is irradiated to the substrate to grow a buffer layer made of ZnO based oxide semiconductor (S2). Subsequently, the irradiation of oxygen radical is stopped so as to eliminate the influence of oxygen onto the buffer layer (S3). Then, the temperature of the substrate is elevated to the temperature at which the predetermined ZnO based oxide semiconductor layer is grown (S4). After that, raw materials containing oxygen radical is irradiated so as to sequentially grow a ZnO based oxide semiconductor layer as a function layer (S5).

Abstract: The present invention provides a method for producing a Group III nitride compound semiconductor, which method permits only minimal reaction of the semiconductor with a hetero-substrate during epitaxial growth and induces no cracks in the Group III nitride compound semiconductor even when the semiconductor is cooled to room temperature. The method includes a buffer layer formation step for forming a gas-etchable buffer layer on the hetero-substrate, and a semiconductor formation step for epitaxially growing the Group III nitride compound semiconductor on the buffer layer through a vapor phase growth method, wherein at least a portion of the buffer layer is gas-etched during or after the semiconductor formation step.

Abstract: The present invention provides for a high quality Group III-V compound semiconductor, a method of manufacturing the same, and a light emitting element with an excellent emission characteristic which incorporates such a Group III-V compound semiconductor.