Differential Etching Patents (Class 438/494)
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Patent number: 11894421Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.Type: GrantFiled: August 9, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.VInventors: Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
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Patent number: 11888031Abstract: In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.Type: GrantFiled: November 30, 2021Date of Patent: January 30, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Hong Yu, Judson R. Holt, Zhenyu Hu
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Patent number: 11462632Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.Type: GrantFiled: December 22, 2020Date of Patent: October 4, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Arkadiusz Malinowski, Alexander M. Derrickson, Ali Razavieh, Halting Wang
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Patent number: 11418009Abstract: A light-emitting device includes a vertical-cavity surface-emitting laser, the resonant cavity of which is transverse multimode supporting transverse modes having rotational symmetry of order two about a main optical axis, and an index-contrast grating including a plurality of pads. The pads include: a central pad, a plurality of peripheral pads, which are periodically arranged along one or more lines that are concentric with respect to the central pad, and which are arranged so that the grating has, with respect to the main optical axis, a rotational symmetry of uneven order higher than or equal to three.Type: GrantFiled: March 6, 2019Date of Patent: August 16, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Corrado Sciancalepore
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Patent number: 11404367Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.Type: GrantFiled: July 13, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu, Chung-Ju Lee
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Patent number: 11183564Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.Type: GrantFiled: June 21, 2018Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Payam Amin, Roza Kotlyar, Patrick H. Keys, Hubert C. George, Kanwaljit Singh, James S. Clarke, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts
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Patent number: 11171209Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.Type: GrantFiled: August 22, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
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Patent number: 11133416Abstract: In an embodiment, a device includes: a fin extending from a substrate; a gate stack over a channel region of the fin; and a source/drain region in the fin adjacent the channel region, the source/drain region including: a first epitaxial layer contacting sidewalls of the fin, the first epitaxial layer including silicon and germanium doped with a dopant, the first epitaxial layer having a first concentration of the dopant; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and germanium doped with the dopant, the second epitaxial layer having a second concentration of the dopant, the second concentration being greater than the first concentration, the first epitaxial layer and the second epitaxial layer having a same germanium concentration.Type: GrantFiled: August 23, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Ting Lin, Hsueh-Chang Sung, Yen-Ru Lee
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Patent number: 10872771Abstract: A method of depositing a material film on a substrate within a reaction chamber by a cyclical deposition process is disclosed. The method may include: contacting the substrate with a first vapor phase reactant and purging the reaction chamber with a first main purge. The method also includes: contacting the substrate with a second vapor phase reactant by two or more micro pulsing processes, wherein each micro pulsing process comprises: contacting the substrate with a micro pulse of a second vapor phase reactant; and purging the reaction chamber with a micro purge, wherein each of the micro pulses of the second vapor phase reactant provides a substantially constant concentration of the second vapor phase reactant into the reaction chamber. The method may also include; purging the reaction chamber with a second main purge. Device structures including a material film deposited by the methods of the disclosure are also disclosed.Type: GrantFiled: January 8, 2019Date of Patent: December 22, 2020Assignee: ASM IP Holding B. V.Inventors: Petri Raisanen, Mark Olstad, Jose Alexandro Romero, Dong Li, Ward Johnson, Peijun Chen
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Patent number: 9784896Abstract: A pattern structure includes a plurality of pattern structure units arranged substantially on a same plane, where each of the pattern structure units has a first surface and a second surface, which are opposite to each other, and a microstructure is defined on the first surface of each of the pattern structure units, and a flattening layer disposed on the second surface of each of the plurality of pattern structure units, where the flattening layer connects the pattern structure units with each other, and a vertical step difference exists between second surfaces of the pattern structure units.Type: GrantFiled: June 8, 2015Date of Patent: October 10, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaeseung Chung, Dongouk Kim, Joonyong Park, Jihyun Bae, Bongsu Shin, Sunghoon Lee, Sukgyu Hahm, Jong G. Ok, Ilsun Yoon
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Patent number: 9607825Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: GrantFiled: April 8, 2014Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Patent number: 9209289Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a substrate structure, wherein the substrate structure includes a substrate and a fin-shaped barrier layer formed on a surface of the substrate; forming a quantum well (QW) material layer on a surface of the fin-shaped barrier layer; and forming a barrier material layer on the QW material layer.Type: GrantFiled: April 29, 2014Date of Patent: December 8, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: De Yuan Xiao
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Patent number: 9171751Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.Type: GrantFiled: April 29, 2014Date of Patent: October 27, 2015Assignee: Avogy, Inc.Inventors: Donald R. Disney, Andrew P. Edwards, Hui Nie, Richard J. Brown, Isik C. Kizilyalli, David P. Bour, Linda Romano, Thomas R. Prunty
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Patent number: 9029246Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.Type: GrantFiled: July 30, 2013Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
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Patent number: 9023733Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.Type: GrantFiled: September 26, 2013Date of Patent: May 5, 2015Assignees: IMEC, Tokyo Electron LimitedInventors: Boon Teik Chan, Shigeru Tahara
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Patent number: 9012310Abstract: Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues.Type: GrantFiled: June 11, 2012Date of Patent: April 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Yi-Fang Pai
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Publication number: 20150091057Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: ASM IP Holding B.V.Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
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Patent number: 8945305Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.Type: GrantFiled: August 31, 2010Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Publication number: 20150014816Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.Type: ApplicationFiled: December 30, 2013Publication date: January 15, 2015Applicant: ASM IP Holding B.V.Inventors: Keith Doran Weeks, John Tolle, Matthew G. Goodman, Sandeep Mehta
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Patent number: 8900978Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.Type: GrantFiled: May 30, 2013Date of Patent: December 2, 2014Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: Nicolas Loubet, Douglas LaTulipe, Alexander Reznicek
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Publication number: 20140342535Abstract: A semiconductor substrate preventing a void from being generated in an epitaxial film buried in a trench. An N-type first epitaxial film and first trenches are formed on an N+-type substrate body. A P-type second epitaxial film is buried in the first trenches. An N+-type third epitaxial film having the same composition as the first epitaxial film is formed on the first and second epitaxial films to form second trenches. A fourth epitaxial film is grown on the entire interior of the second trenches. The formation of the first and second trenches and the burying of the second and fourth epitaxial films are performed in a plurality of steps. Thus, the aspect ratio of the first and second trenches when the second and fourth epitaxial films are buried can be reduced. As a result, the second and fourth epitaxial films can be buried in the first and second trenches without causing a void.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Syouji NOGAMI, Tomonori YAMAOKA, Shoichi YAMAUCHI, Nobuhiro TSUJI, Toshiyuki MORISHITA
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Publication number: 20140332833Abstract: Provided is a hetero-substrate that may include a base substrate, a buffer layer disposed on the base substrate, and a first semiconductor layer disposed on the buffer layer, the first semiconductor layer including a nitride semiconductor. A defect blocking layer is disposed on the first semiconductor layer. The defect blocking layer may include a plurality of metal droplets. A second semiconductor layer may be disposed on the defect blocking layer, the second semiconductor layer including a nitride semiconductor.Type: ApplicationFiled: December 6, 2013Publication date: November 13, 2014Inventor: Chisun KIM
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Publication number: 20140327118Abstract: A method of fabricating a power semiconductor device includes the following steps. Firstly, a substrate is provided. A first epitaxial layer is formed over the substrate. A first trench is formed in the first epitaxial layer. A second epitaxial layer is refilled into the first trench. The first epitaxial layer and the second epitaxial layer are collaboratively defined as a first semiconductor layer. A third epitaxial layer is formed over the substrate, and a second trench is formed in the third epitaxial layer. A first doping region is formed in a sidewall of the second trench. An insulation layer is refilled into the second trench. The insulation layer, the first doping region and the third epitaxial layer are collaboratively defined as a second semiconductor layer. The power semiconductor device fabricated by the fabricating method can withstand high voltage and has low on-resistance.Type: ApplicationFiled: August 14, 2013Publication date: November 6, 2014Applicant: MOSEL VITELIC INC.Inventors: Chien-Ping Chang, Chien-Chung Chu
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Publication number: 20140312355Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.Type: ApplicationFiled: April 19, 2013Publication date: October 23, 2014Applicant: AVOGY, INC.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Hui Nie, Quentin Diduck, Ozgur Aktas
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Publication number: 20140295652Abstract: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventors: Hui Nie, Andrew P. Edwards, Donald R. Disney, Isik C. Kizilyalli
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Publication number: 20140252412Abstract: The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration of less than approximately 1% aids in control of the phosphorus dopant diffusion. Phosphorus dopant diffusion is also controlled by an anneal step which promotes uniform doping through both source and drain, as well as lightly-doped drain regions.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiang Tsai, Su-Hao Liu
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Patent number: 8809170Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.Type: GrantFiled: May 19, 2011Date of Patent: August 19, 2014Assignee: ASM America Inc.Inventor: Matthias Bauer
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Publication number: 20140183554Abstract: A Schottky barrier diode includes: an n+ type silicon carbide substrate; an n? type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate and includes an electrode area and a terminal area positioned outside of the electrode area; a first trench and a second trench disposed on the n? type epitaxial layer in the terminal area; a p area disposed under the first trench and the second trench; a Schottky electrode disposed on the n? type epitaxial layer in the electrode area; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first trench and the second trench are adjacently positioned to form a step.Type: ApplicationFiled: October 29, 2013Publication date: July 3, 2014Applicant: HYUNDAI MOTOR COMPANYInventors: Kyoung-Kook HONG, Jong Seok LEE, Dae Hwan CHUN, Youngkyun JUNG
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Publication number: 20140179087Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.Type: ApplicationFiled: May 3, 2013Publication date: June 26, 2014Applicant: QuNano ABLInventor: QuNano AB
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Patent number: 8679952Abstract: A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.Type: GrantFiled: March 18, 2011Date of Patent: March 25, 2014Assignee: Mitsubishi Electric CorporationInventors: Nobuyuki Tomita, Kenichi Hamano, Masayoshi Tarutani, Yoichiro Mitani, Takeharu Kuroiwa, Masayuki Imaizumi, Hiroaki Sumitani, Kenichi Ohtsuka, Tomoaki Furusho, Takao Sawada, Yuji Abe
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Patent number: 8637373Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.Type: GrantFiled: March 2, 2012Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hoi-Sung Chung, Dong-Suk Shin, Dong-Hyuk Kim, Myung-Sun Kim
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Patent number: 8637362Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.Type: GrantFiled: July 13, 2012Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Publication number: 20140024204Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.Type: ApplicationFiled: July 17, 2013Publication date: January 23, 2014Applicant: IMECAInventors: Andriy Hikavyy, Benjamin Vincent, Roger Loo
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Publication number: 20130323915Abstract: A method of forming a silicon film includes a first film forming process, an etching process, a doping process, and a second film forming process. In the first film forming process, a silicon film doped with impurities containing boron is formed so as to embed a groove provided on an object to be processed. In the etching process, the silicon film formed in the first film forming process is etched. In the doping process, the silicon film etched in the etching process is doped with impurities containing boron. In the second film forming process, a silicon film doped with impurities containing boron is formed so as to embed the silicon film that is doped in the doping process.Type: ApplicationFiled: May 24, 2013Publication date: December 5, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Katsuhiko KOMORI, Akinobu KAKIMOTO, Mitsuhiro OKADA, Nobuhiro TAKAHASHI
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Publication number: 20130200391Abstract: A gallium nitride-based structure includes a substrate, a first layer of gallium nitride disposed on a growth surface of the substrate, and a second gallium nitride layer disposed on the first gallium nitride layer. The first layer includes a region in which a plurality of voids is dispersed. The second layer has a lower defect density than the gallium nitride of the interfacial region. The gallium nitride-based structure is fabricated by depositing GaN on the growth surface to form the first layer, forming a plurality of gallium nitride nanowires by removing gallium nitride from the first layer, and growing additional GaN from facets of the nanowires. Gallium nitride crystals growing from neighboring facets coalesce to form a continuous second layer, below which the voids are dispersed in the first layer. The voids serve as sinks or traps for crystallographic defects, and also as expansion joints that ameliorate thermal mismatch between the Ga.N and the underlying substrate.Type: ApplicationFiled: September 28, 2011Publication date: August 8, 2013Applicant: North Carolina State UniversityInventors: Salah M. Bedair, Nadia A. El-Masry, Pavel Frajtag
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Patent number: 8501597Abstract: A method of fabricating a group III-nitride semiconductor includes the following steps of: forming a first patterned mask layer with a plurality of first openings deposited on an epitaxial substrate; epitaxially growing a group III-nitride semiconductor layer over the epitaxial substrate and covering at least part of the first patterned mask layer; etching the group III-nitride semiconductor layer to form a plurality of second openings, which are substantially at least partially aligned with the first openings; and epitaxially growing the group III-nitride semiconductor layer again.Type: GrantFiled: July 27, 2011Date of Patent: August 6, 2013Assignee: Academia SinicaInventors: Yuh-Jen Cheng, Ming-Hua Lo, Hao-Chung Kuo
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Publication number: 20130193558Abstract: The non-polar or semi-polar group III nitride layer disclosed in a specific example of the present invention can be used for substrates for various electronic devices, wherein problems of conventional polar group III nitride substrates are mitigated or solved by using the nitride substrate of the invention, and further the nitride substrate can be manufactured by a chemical lift-off process.Type: ApplicationFiled: November 4, 2011Publication date: August 1, 2013Applicant: Korea Photonics Technology InstituteInventors: Jin Woo Ju, Jong Hyeob Baek, Hyung Jo Park, Sang Hern Lee, Tak Jung, Ja Yeon Kim, Hwa Seop Oh, Tae Hoon Chung, Yoon Seok Kim, Dae Woo Jeon
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Publication number: 20130178050Abstract: A method for manufacturing a gallium nitride (GaN) wafer is provided. In the method for manufacturing the GaN wafer according to an embodiment, an etch stop layer is formed on a substrate, and a first GaN layer is formed on the etch stop layer. A portion of the first GaN layer is etched with a silane gas, and a second GaN layer is formed on the etched first GaN layer. A third GaN layer is formed on the second GaN layer.Type: ApplicationFiled: December 13, 2012Publication date: July 11, 2013Inventors: Yong-Jin Kim, Dong-Kun Lee, Doo-Soo Kim, Ho-Jun Lee, Kye-Jin Lee
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Patent number: 8460977Abstract: A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.Type: GrantFiled: December 28, 2011Date of Patent: June 11, 2013Assignee: Cree, Inc.Inventors: Qingchun Zhang, Anant K. Agarwal
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Publication number: 20130122694Abstract: Exemplary embodiments of the present invention provide a method of fabricating a semiconductor substrate, the method including growing a first compound semiconductor layer on a first surface of a substrate, etching the first compound semiconductor layer using HF, KOH, or NaOH to roughen a first surface of the first compound semiconductor layer, forming cavities in the first compound semiconductor layer, separating the first compound semiconductor layer from the first surface of the substrate, flattening the first surface of the substrate after separating the first compound semiconductor layer, and growing a second compound semiconductor layer on the flattened first surface of the substrate.Type: ApplicationFiled: December 31, 2012Publication date: May 16, 2013Applicant: Seoul Opto Device Co., Ltd.Inventor: Seoul Opto Device Co., Ltd.
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Patent number: 8426295Abstract: To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed.Type: GrantFiled: October 6, 2011Date of Patent: April 23, 2013Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi, Yoshitaka Yamamoto
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Publication number: 20120295427Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicant: ASM AMERICA, INC.Inventor: Matthias Bauer
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Patent number: 8241940Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.Type: GrantFiled: February 12, 2011Date of Patent: August 14, 2012Assignee: Solexel, Inc.Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D Kamian, Jay Ashjaee, Takao Yonehara
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Patent number: 8227305Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.Type: GrantFiled: March 17, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 8128981Abstract: A biosensor having a first conductive component is described, wherein the first conductive component includes at least one boundary formed by a first processing technique and at least one boundary formed by a second processing technique not the same as the first processing technique. The biosensor can also have a second conductive component including at least one boundary formed by the first processing technique and at least one boundary formed by a third processing technique not the same as the first processing technique. Further, the biosensor has a third conductive component including at least one boundary formed by the second processing technique and at least one boundary formed by the third processing technique not the same as the second processing technique.Type: GrantFiled: April 10, 2007Date of Patent: March 6, 2012Assignee: Nipro Diagnostics, Inc.Inventors: Natasha Popovich, Dennis Slomski, David Deng
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Patent number: 8043898Abstract: A method of manufacturing a semiconductor package is provided, which can improve the quality of plating through reduction of plating deviation, and improve molding and soldering efficiencies in forming a molding compound and packaging the semiconductor package onto a printed circuit board.Type: GrantFiled: December 20, 2007Date of Patent: October 25, 2011Assignee: Col Tech Co., LtdInventors: Ji-Yong Lee, Kwang-Wook Choi
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Patent number: 8019458Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: GrantFiled: August 6, 2008Date of Patent: September 13, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Patent number: 7960255Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.Type: GrantFiled: September 22, 2008Date of Patent: June 14, 2011Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V.Inventors: Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Markus Müller
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Patent number: 7955959Abstract: A method for manufacturing GaN-based film LED based on masklessly transferring photonic crystal structure is disclosed. Two dimensional photonic crystals are formed on a sapphire substrate. Lattice quality of GaN-based epitaxy on the sapphire substrate is improved, and the internal quantum efficiency of GaN-based LED epitaxy is increased. After the GaN-based film is transferred onto heat sink substrate, the two dimensional photonic crystals structure is masklessly transferred onto the light exiting surface of the GaN-based film by using different etching rates between the GaN material and the SiO2 mask, so that light extraction efficiency of the GaN-based LED is improved. That is, the GaN-based film LED according to the invention has a relatively high illumination efficiency and heat sink.Type: GrantFiled: September 23, 2010Date of Patent: June 7, 2011Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.Inventors: Jyh Chiarng Wu, Xuejiao Lin, Qunfeng Pan, Meng Hsin Yeh, Huijun Huang
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Patent number: 7923372Abstract: A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of the etch mask patterns, the spacers including a material substantially the same as that of the first pad layer, forming a second hard mask over the resulting substrate structure until gaps between the etch mask patterns are filled, the second hard mask including a material different from that of the first hard mask but substantially the same as that of the second pad layer, planarizing the second hard mask until the first pad layer is exposed, removing the first pad layer and the spacers, and etching the etch target layer using the remaining first and second hard masks as an etch barrier layer.Type: GrantFiled: December 29, 2006Date of Patent: April 12, 2011Assignee: Hynix Semiconductor Inc.Inventors: Young-Jun Kim, Sang-Wook Park