Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a bulk layer between front and back surface layers. The wafer is subjected to a heat-treatment in an atmosphere to form crystal lattice vacancies. A surface of the wafer is oxidized by heating in the presence of an oxygen-containing atmosphere to effect the vacancy concentration profile. The wafer is cooled at a rate which allows some, but not all, the crystal lattice vacancies to diffuse to the surfaces such that the concentration of vacancies in the bulk layer is greater than in the surface layers. The vacancy concentration profile shape is determined in part by the heat-treatment atmosphere, in part by the surface oxidation, and in part by the cooling rate.

Abstract: In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50).

Abstract: The formation of microelectronic structures in trenches and vias of an integrated circuit wafer are described using nanocrystal solutions. A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface. In the process, nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. Heating is also carried out concurrently with nanocrystals solution deposition. Copper nanocrystals of less than about 5 nanometers are particularly well suited for formation of interconnects at temperatures of less than 350 degrees Celsius.

Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: A first semiconductor film made of a nitride semiconductor is grown through epitaxial growth on a light transmitting substrate. A thermal decomposition layer is disposed in a space between the substrate and the first semiconductor film by irradiating laser light to the first semiconductor film from the back surface of the substrate. After a second semiconductor film made of a nitride semiconductor is grown through epitaxial growth while the first semiconductor film is placed on the substrate, the temperature of the substrate is lowered to room temperature. Then, by separating and removing the substrate from the first and second semiconductor films, it is possible to obtain a nitride semiconductor substrate having an area substantially as large as the area of the substrate.

Abstract: An MOS heterostructure includes: a single crystal silicon substrate; an insulating film formed on the substrate; and a conductive film formed on the insulating film. The substrate includes a plurality of terraces and steps, which have been formed as a result of rearrangement of silicon atoms on the surface of the substrate. Each of the step is located in a boundary between an adjacent pair of the terraces. The insulating film contains crystalline silicon dioxide that has grown epitaxially over the steps.

Abstract: A solution containing a cyclic silane compound, which does not contain carbon, and/or a silane compound modified by boron or phosphorus is applied onto a substrate and a silicon precursor film is formed, and the film is then transformed into semiconductor silicon by heat and/or light treatment. Thereby, it is possible to easily produce a silicon film having satisfactory characteristics as an electronic material at low costs, differing from the vacuum process, such as by CVD methods.

Abstract: The present invention provides a method of forming a functional film pattern which allows the forming of fine film patterns with simplified steps. The present invention also provides a method of forming a functional film pattern where such defects as disconnection and short circuit rarely occurs, and forming a pattern which has a large thickness and is good for exhibiting a function such as electric conduction can be formed.

Abstract: A solar battery is provided having a structure in which at least two semiconductor thin-films are disposed one over the other between a pair of electrodes, each semiconductor thin-film differing from the other in the impurity concentration thereof and/or the type of semiconductor. Formation of at least one of the semiconductor thin-films consists of coating a liquid coating composition containing a silicon compound so as to form a coating film and a step of converting the coating film into a silicon film by heat treatment and/or light treatment.

Abstract: A system and method for providing substantially defect free rapid thermal processing. The present invention includes a wafer processing system used to process semiconductor wafers into electronic devices. In accordance with the present invention, once the wafer is processed, a shield can be inserted into the reactor to a position between the reactor heating surface and the wafer. The shield causes the temperature of the wafer to be reduced. Once the temperature of the wafer has been reduced to below a predetermined critical temperature, the robot picks up the wafer and removes the wafer from the processing chamber.

Abstract: The present invention provides a means for obtaining dielectric thin films on a substrate, e.g., silicon, by 1) low temperature (500° C. or less) deposition of a dielectric material onto a surface, followed by 2) high temperature post-deposition annealing. The deposition can take place in an oxidative environment, followed by annealing, or alternatively the deposition can take place in a non-oxidative environment (e.g., N2), followed by oxidation and annealing.

Abstract: A single crystal silicon is produced using a Czocharalski (CZ) method. Silicon nitride powder is put in the bottom of a quartz crucible to provide a nitrogen concentration in the single crystal silicon of not less than about 1×1013 atoms/cm3. A poly-silicon raw material is then charged in the crucible. A pulling rate for the single crystal silicon is low so that an oxidation induced stacking faults ring exists or disappears at the center. Maintaining the nitrogen concentration of the single crystal silicon to not less than 1×1013 atoms/cm3 decrease the vacancy cluster and existinguish the dislocation cluster. Wafers prepared from the single crystal silicon have very high quality with minimal defects.

Abstract: An object is to provide a method of activating impurity elements added to a semiconductor film, and a method of gettering, in a process of manufacturing a semiconductor device using a substrate having a low resistance to heat, such as glass without changing the shape of the substrate, by using a short time heat treatment process. Another object is to provide a heat treatment apparatus that makes this type of heat treatment process possible. A unit for supplying a gas from the upstream side of a reaction chamber, a unit for heating the gas in the upstream side of the reaction chamber, a unit for holding a substrate to be processed in the downstream side of the reaction chamber, and a unit for circulating the gas from the downstream side of the reaction chamber to the upstream side are prepared. The amount of electric power used in heating the gas can be economized by circulating the gas used to heat the substrate to be processed.

Abstract: An epitaxial semiconductor crystal plate or wafer capable of attaining increased reliability with enhanced luminance, a manufacturing method thereof, as well as a light-emitting diode (LED). It has been found that epitaxial wafers with enhanced illuminance and increased yield of manufacture can be fabricated by specifically arranging a double-heterostructure epitaxial wafer such that the interface between its p-type clad layer 2 and p-type GaAlAs active layer 3 and that between an n-type GaAlAs clad layer 4 and p-type GaAlAs active layer 3 measure 1×1017 cm−3 or less in oxygen concentration. Also, in order to cause the oxygen concentration near the p-type GaAlAs active layer 3 in layers of the epitaxial wafer to be less than or equal to 1×1017 cm−3, it may be preferable that a nondoped GaAs polycrystal for use as a preselected original material in liquid-phase epitaxial growth be less than or equal to 1×1016 cm−3 or there about.

Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an uneven distribution of crystal lattice defects. The crystal lattice defects are substitutionally or interstitially included nitrogen or vacancies.

Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.

Abstract: A method for producing a semiconductor wafer includes the deposition of an epitaxial layer onto a substrate wafer in a deposition reactor. The semiconductor wafer, following the deposition of the epitaxial layer, undergoes treatment in an ozone-containing atmosphere.

Abstract: There are disposed two homogenizers for controlling an irradiation energy density in the longitudinal direction of a laser light transformed into a linear one which is inputtted into the surface to be irradiated. Also, there is disposed one homogenizer for controlling an irradiation energy density in a width direction of the linear laser light. According to this, the uniformity of laser annealing can be improved by the minimum number of homogenizers.

Abstract: In the fabrication of capacitors, a TiO2 film is formed from a TiN film by means of heat-treatment within an atmosphere which does not contain oxygen. This serves to prevent the polysilicon which forms the bottom electrode from being oxidized during heat-treatment. Thus, once the bottom electrode has been formed on the silicon wafer, a TiN film and RuO2 film are formed, and the silicon wafer is heat-treated in an atmosphere which does not contain oxygen. In this manner, a dielectric film that is a TiO2 film and a top electrode that is a ruthenium film are obtained.

Abstract: An apparatus for growing a mixed compound semiconductor layer utilizing three or more source gases. The apparatus includes a horizontal type reactor chamber. The reactor chamber includes a partition plate separating an upstream region of the reactor chamber into an upper region and a lower region. The upper and lower regions are joined together forming a growth region in a downstream region of the reactor chamber. First and second inlet ports are provided at an upstream end of the lower region for admitting first and second source gases, respectively. A third inlet port is provided at an upstream end of the upper region for admitting a third source gas. An outlet port is provided at a downstream end of the growth region for exhaust. A substrate stage is arranged in the growth region so that the substrate surface is exposed to the growth region and forms a smooth surface for allowing a laminar gas flow.

Abstract: A lamination machine includes means for using gas pressure to bring a coverlay and a microelectronic package into intimate contact and means for heating a coverlay adhesive in order to seal the coverlay to the package. A method of laminating a coverlay to a microelectronic package using the lamination machine includes using gas pressure to bring a coverlay into intimate contact with a microelectronic package. The method also includes heating an adhesive on the coverlay in order to adhere the coverlay to the package. Once the coverlay is laminated to the package, the package can be encapsulated with a curable encapsulant composition. The method may also include decreasing the pressure in the chamber disposed above the package to reduce voids and bubble and/or regulating the pressure in a bladder disposed in a chamber below the package.

Abstract: There is disclosed a method for producing an epitaxial silicon single crystal wafer comprising the steps of growing a silicon single crystal ingot wherein nitrogen is doped by Czochralski method, slicing the silicon single crystal ingot to provide a silicon single crystal wafer, and forming an epitaxial layer in the surface layer portion of the silicon single crystal wafer. There can be manufactured easily and in high productivity an epitaxial silicon monocrystal wafer which has high gettering capability when a substrate having a low boron concentration is used, a low concentration of heavy metal impurity, and an excellent crystallinity.

Abstract: A process for removing copper from a boron doped, polished silicon wafer which contains copper on its polished surface and in its interior. In the process, the wafer is annealed at a temperature of at least about 75.degree. C. to increase the concentration of copper on the polished surface of the wafer and decrease the concentration of copper in the interior of the wafer. The polished surface of the annealed wafer is then cleaned to reduce the concentration of copper thereon. In addition, the annealing step is carried out at a temperature and a time such that the concentration of copper on the polished surface of the silicon will not increase by a factor of more than two upon storage of the annealed and cleaned wafer at room temperature for a period of 5 months.

Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.

Abstract: After p-type gallium nitride compound semiconductor layers, to which p-type impurity is added, are formed by virtue of chemical vapor deposition, the p-type gallium nitride compound semiconductor layers are thermally annealed at more than 400.degree. C. or more than 700.degree. C. while supplying a flow of an inert gas in parallel to a substrate surface at a predetermined flow rate or more. Otherwise, the p-type gallium nitride compound semiconductor layers are thermally annealed at more than 400.degree. C. or more than 700.degree. C. in an inert gas atmosphere having a predetermined pressure or more. According to the annealing process, the p-type impurity can be more effectively activated, so that p-type gallium nitride compound semiconductor layers which have fewer crystal defects, etc. and have lower resistivity can be formed.

Abstract: An insulating film is formed on a surface of a semiconductor substrate. Then a photoresist pattern including only one wedge-like area is formed on a surface of the insulating film. Next, a groove part is formed in the insulating film, using the photoresist pattern as a mask. Next, a titanium layer and a polycrystal-structured aluminum layer are embedded in the entire groove part. A monocrystal-structured aluminum layer is formed by heating the polycrystal-structured aluminum layer at 500 to 600.degree. C. and then cooling it down gradually. No monocrystal silicon to serve as a seed is needed in a bed. Therefore, for example, monocrystallization can be carried out even in second and third layers of multilayer wiring. This realizes a manufacturing method of wiring composed of a highly reliable monocrystal conductive film, which is widely applicable and especially appropriate to wiring of a semiconductor device.

Abstract: A silicon thin film is formed by coating on a substrate a solution of polysilane represented by the general formula --(SiR.sup.1.sub.2).sub.n --, where R.sup.1 substituents are selected from the group consisting of hydrogen, an alkyl group having two or more carbon atoms and a .beta.-hydrogen, a phenyl group and a silyl group, and thermally decomposing the polysilane to deposit silicon.

Abstract: A method is provided for producing an n-type or p-type epitaxial layer using a doped substrate material. The method includes growing a substrate (12), preferably from a material to which an epitaxial layer can be lattice-matched. The substrate (12) is doped with a predetermined concentration of dopant (14). Preferably, the dopant (14) possesses the ability to rapidly diffuse through a material. An epitaxial layer (16) is grown upon the doped substrate (12). The epitaxial layer (16) and the doped substrate are annealed, thereby causing the dopant (14) to diffuse from the substrate (14) into the epitaxial layer (16).

Abstract: A method for increasing the surface area of a polysilicon storage node electrode, used as a component for a DRAM stacked capacitor structure, has been developed. The method features forming a metal silicide layer, on the top surface of the polysilicon storage node electrode, locally consuming regions of underlying polysilicon during the metal silicide formation. Removal of the metal silicide layer, from the surface of the polysilicon storage node electrode, results in a roughened surface, comprised of crevices in the top surface of the polysilicon storage node electrode, in regions in which localized metal silicide formation had occurred. The crevices in the top surface of the polysilicon storage node electrode result in surface area increases, when compared to counterparts fabricated using smooth polysilicon surfaces.

Abstract: Dielectrics represented by (Sr.sub.x Bi.sub.1-x)Bi.sub.2 Ta.sub.2 O.sub.y, wherein 0<x<1, and y represents the total number of oxygen atoms bonded to the respective metals, and thin films thereof, can be prepared by repeating the steps of applying compositions for forming the Sr--Bi--Ta--O-based dielectric thin films on substrates, drying and conducting a first-firing a plurality of times until the desired film thickness is achieved, and then conducting a second-firing for crystallization and compositions for forming Bi-based ferroelectric thin films and target materials for forming Bi-based ferroelectric thin films, both represented by the metal composition ((Sr.sub.a (Ba.sub.b, Pb.sub.c)).sub.x Bi.sub.y (Ta and/or Nb).sub.z wherein 0.4.ltoreq.X<1.0, 1.5.ltoreq.Y.ltoreq.3.5, Z=2, 0.7X.ltoreq.a<X, and 0<b+c.ltoreq.0.

Abstract: A monitor wafer used to determine the cleanliness of a wafer fabrication environment requires a surface having a minimum of light scattering anomalies so that contamination deposited by the environment is not confused with light scattering anomalies initially on the monitor wafers. In the present invention, ingots of a single-crystal semiconductor are grown at a reduced pull rate and wafers produced from the ingot are annealed within a preferred temperature range that varies with the pull rate to produce wafers having reduced light-scattering anomalies on their surfaces. The number of light-scattering anomalies increases at a slower rate upon repetitive cleaning cycles than does the number of light-scattering anomalies of prior art wafers.