Introduction Of Conductivity Modifying Dopant Into Semiconductive Material Patents (Class 438/510)
  • Patent number: 8796765
    Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos, Olivier Gagliano, Marc Mantelli
  • Publication number: 20140210001
    Abstract: A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventor: Shinya Yamazaki
  • Publication number: 20140209973
    Abstract: A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Inventors: Johannes Georg Laven, Roman Baburske, Christian Jaeger, Hans-Joachim Schulze
  • Publication number: 20140210058
    Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, SK hynix Inc.
    Inventors: Jong Ho LEE, Kyung Do KIM
  • Patent number: 8785307
    Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: July 22, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Xian Liu, Mandana Tadayoni, Chien-Sheng Su, Nhan Do
  • Patent number: 8779462
    Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Hans-Joerg Timme, Frank Pfirsch
  • Patent number: 8772910
    Abstract: A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski
  • Patent number: 8772141
    Abstract: A method for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski
  • Publication number: 20140179089
    Abstract: The process for the production of at least one silicon-based nanoelement (4), in particular a nanowire, comprises the following stages: providing a substrate comprising, at the surface, a first layer (1) comprising electrically doped silicon; forming, on the first layer (1), a second layer (2) based on silicon oxide with carbon atoms (3) dispersed in the said second layer (2); and exposing the first and second layers (1, 2) to an oxidizing atmosphere, so as to oxidize at least a first section (1a) of the first layer (1) at the interface of the said first layer (1) with the second layer (2) and to form the said at least one nanoelement (4) at the said first section (1a).
    Type: Application
    Filed: December 19, 2013
    Publication date: June 26, 2014
    Inventors: Vincent Larrey, Laurent Vandroux, Audrey Berthelot, Marie-Helene Vaudaine
  • Publication number: 20140167149
    Abstract: A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 19, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jang Uk LEE
  • Patent number: 8747551
    Abstract: After adding phosphorus (P) and germanium (Ge) into a silicon melt or adding phosphorus into a silicon/germanium melt, a silicon monocrystal is grown from the silicon melt by a Czochralski method, where a phosphorus concentration [P]L(atoms/cm3) in the silicon melt, a Ge concentration in the silicon monocrystal, an average temperature gradient Gave (K/mm) and a pull speed V (mm/min) are controlled to satisfy a formula (1) as follows, a phosphorus concentration [P](atoms/cm3) and the Ge concentration [Ge](atoms/cm3) in the silicon monocrystal satisfy a relationship according to a formula (2) as follows while growing the silicon monocrystal, where dSi(?) represents a lattice constant of silicon, rSi(?) represents a covalent radius of silicon, rP(?) represents a covalent radius of phosphorus, and rGe(?) represents a covalent radius of Ge: [ P ] L + ( 0.3151 × [ Ge ] + 3.806 × 10 18 ) / 1.5 < 0.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: June 10, 2014
    Assignee: Sumco Techxiv Corporation
    Inventors: Shinichi Kawazoe, Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa
  • Publication number: 20140154876
    Abstract: A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region.
    Type: Application
    Filed: February 5, 2014
    Publication date: June 5, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung TSAI, Tsan-Chun WANG, Su-Hao LIU, Tsz-Mei KWOK, Chii-Ming WU
  • Patent number: 8728926
    Abstract: The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: May 20, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhongshan Hong
  • Patent number: 8722456
    Abstract: The embodiments disclosed a method for preparing a p-type ZnO-based material, the method conducted in a metal organic chemical vapor deposition (MOCVD) system, including cleaning a surface of a substrate and placing the substrate in a growth chamber of the metal organic chemical vapor deposition system, vacuumizing the growth chamber to 10?3-10?4 Pa, heating the substrate to 200-700° C., introducing an organic Zn source, an organic Na source and oxygen, and depositing the p-type ZnO-based material on the substrate. Na-doping is capable of greatly improving hole concentration and p-type stability in the ZnO-based material, and use of Na-doping technology in combination with MOCVD equipment provides a p-type ZnO-based material having excellent crystal quality and electrical and optical qualities.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: May 13, 2014
    Assignee: Hangzhou Bluelight Opto-Electronic Material Co., Ltd.
    Inventors: Zhizhen Ye, Yangfan Lu, Kewei Wu, Jingyun Huang, Qikuo Ye
  • Publication number: 20140117490
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Terence B. Hook, Veeraraghavan S. Basker, Chun-Chen Yeh
  • Publication number: 20140117529
    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Kyle Armstrong, Michael D. Hyatt, Michael Dean Van Patten, David A. Kewley, Ming-Chuan Yang
  • Patent number: 8709925
    Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: April 29, 2014
    Assignee: The Regents of the University of California
    Inventors: John F. Kaeding, Hitoshi Sato, Michael Iza, Hirokuni Asamizu, Hong Zhong, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8709924
    Abstract: Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 29, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Seon-Mee Cho, Majeed A. Foad
  • Publication number: 20140103436
    Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8691675
    Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Damon B. Farmer, Lidija Sekaric
  • Publication number: 20140091380
    Abstract: In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 8680645
    Abstract: A semiconductor device having a semiconductor die is provided. The semiconductor die includes a main horizontal surface, an outer edge, an active area, and a peripheral area. The peripheral area includes a dielectric structure surrounding the active area and extending from the main horizontal surface into the semiconductor die. The dielectric structure includes, in a horizontal cross-section, at least one substantially L-shaped portion that is inclined against the outer edge. Further, a method for forming a semiconductor device is provided.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20140077268
    Abstract: According to various embodiments, a distributed heating transistor includes: a plurality of active regions where transistor action occurs including a heat source; and at least one inactive region where transistor action does not occur and no heat source is present, wherein adjacent active regions are separated by the at least one inactive region. The distributed heating transistor may be configured as field effect transistors (FETs), and bipolar junction transistors (BJTs). Methods for forming the distributed heating transistors are also provided.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 20, 2014
    Applicant: U.S. Government as represented by the Secretary of the Army
    Inventors: Ali Darwish, Hingloi Alfred Hung
  • Patent number: 8674408
    Abstract: An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8664632
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
  • Publication number: 20140057422
    Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventors: XIAN LIU, MANDANA TADAYONI, CHIEN-SHENG SU, NHAN DO
  • Publication number: 20140054667
    Abstract: A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventor: Yuri Tkachev
  • Patent number: 8658508
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8659029
    Abstract: A low contact resistance semiconductor structure includes a substrate, a semiconductor stacked layer, a low contact resistance layer and a transparent conductive layer. The low contact resistance layer is formed on one side of a P-type GaN layer of the semiconductor stacked layer. The low contact resistance layer is formed at a thickness smaller than 100 Angstroms and made of a material selected from the group consisting of aluminum, gallium, indium, and combinations thereof. Through the low contact resistance layer, the resistance between the P-type GaN layer and transparent conductive layer can be reduced and light emission efficiency can be improved when being used on LEDs. The method of fabricating the low contact resistance semiconductor structure of the invention forms a thin and consistent low contact resistance layer through a Metal Organic Chemical Vapor Deposition (MOCVD) method to enhance matching degree among various layers.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 25, 2014
    Assignee: Lextar Electronics Corporation
    Inventors: Te-Chung Wang, Fu-Bang Chen, Hsiu-Mu Tang
  • Publication number: 20140051238
    Abstract: A first resist layer (46a) and a second resist layer (46b) that is thicker than the first resist layer (46a) are formed using a multi-gradient mask, a conductive film (44) is isotropically etched with both resist layers (46a, 46b) as masks, gate electrodes (34a, 34b) are formed narrower than the resist layers (46a, 46b) at locations corresponding to first and second semiconductor layers (31a, 31b), overhang portions (47) of the resist layers (46a, 46b) are configured at the sides of the gate electrodes (34a, 34b), then the entire first resist layer (46a) is removed and the second resist layer (46b) is thinned into a thin film; and an impurity is injected into the first semiconductor layer (31a) with the gate electrode (34b) as a mask, and into the second semiconductor layer (31b) with the second resist layer (46b) as a mask.
    Type: Application
    Filed: May 2, 2012
    Publication date: February 20, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Masaki Saitoh
  • Publication number: 20140030878
    Abstract: An object of the present invention is to amplify the current which varies by a factor of several orders of magnitude with a constant gain without using a complicated circuit. In order to solve the problem, with a semiconductor device includes a first semiconductor region of a first conductivity, a second semiconductor region which is an opposite conductivity opposite to the first conductivity and is in contact with the first semiconductor region and a third semiconductor region which is the first conductivity and is in contact with the second semiconductor region at the second surface, a fourth semiconductor region in contact with the second semiconductor region is provided so as to be separated from the third semiconductor region and enclose the third semiconductor region and an impurity concentration of the fourth semiconductor region is larger than that of the second semiconductor region.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yutaka Hayashi, Yasushi Nagamune, Toshitaka Ota
  • Publication number: 20140024205
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 23, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 8629030
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8623748
    Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Zhongze Wang
  • Publication number: 20130330899
    Abstract: A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Ming Cai, Kevin K. Chan, Dechao Guo, Ravikumar Ramachandran, Liyang Song, Chun-Chen Yeh
  • Patent number: 8597978
    Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
  • Patent number: 8592873
    Abstract: Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Kim, Daehyun Jang, Myoungbum Lee, Kihyun Hwang, Sangryol Yang, Yong-Hoon Son, Ju-Eun Kim, Sunghae Lee, Dongwoo Kim, JinGyun Kim
  • Patent number: 8592794
    Abstract: A resistance random access memory element includes a first electrode, an insulating layer, a diffusing metal layer, and a second electrode superimposed in sequence. The insulating layer includes a plurality of pointed electrodes. A method for making a resistance random access memory element includes growing and forming an insulating layer on a surface of a first electrode. A diffusing metal layer is formed on a surface of the insulating layer. A second electrode is mounted on a surface of the diffusing metal layer. A negative pole and a positive pole of a driving voltage are connected with the first and second electrodes, respectively. The diffusing metal in the diffusing metal layer is oxidized into metal ions by the driving voltage. The metal ions are driven into the insulating layer and form a plurality of pointed electrodes after reduction.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: November 26, 2013
    Assignee: National Sun Yat-Sen University
    Inventors: Ting-Chang Chang, Po-Chun Yang, Yu-Shih Lin, Shih-Ching Chen, Fu-Yen Jian
  • Publication number: 20130307080
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Roger Wang
  • Patent number: 8586460
    Abstract: Methods of enabling the use of high wavelength lasers to create shallow melt junctions are disclosed. In some embodiments, the substrate may be preamorphized to change its absorption characteristics prior to the implantation of a dopant. In other embodiments, a single implant may serve to amorphize the substrate and provide dopant. Once the substrate is sufficiently amorphized, a laser melt anneal may be performed. Due to the changes in the absorption characteristics of the substrate, longer wavelength lasers may be used for the anneal, thereby reducing cost.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 19, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Deepak Ramappa
  • Patent number: 8586458
    Abstract: Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes are provided.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon-mi Yoon, Seong-jae Choi, Hyeon-jin Shin, Jae-young Choi, Sung-jin Kim, Young-hee Lee
  • Patent number: 8580658
    Abstract: Methods for forming graphite-based structures, in which a substrate is patterned to form a plurality of elements on the substrate, are provided. A trench separates a first element from an adjacent element in the plurality. The surface of the first element and the surface of the trench (i) are respectively characterized by different first and second elevations and (ii) are separated by a side wall of the first element. Orthogonal projections of the surface of the first element and the surface of the trench onto a common plane are contiguous or overlapping. In the method, a first graphene layer on the entire first surface and a second graphene layer on the entire second surface are concurrently generated. The second graphene layer has a thickness that is less than a difference between the first and second elevations. Thus, a graphite-based structure having isolated first and second graphene layers is formed.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: November 12, 2013
    Assignee: Solan, LLC
    Inventor: Mark Alan Davis
  • Patent number: 8574363
    Abstract: After adding phosphorus (P) and germanium (Ge) into a silicon melt or adding phosphorus into a silicon/germanium melt, a silicon monocrystal is grown from the silicon melt by a Czochralski method, where a phosphorus concentration [P]L (atoms/cm3) in the silicon melt, a Ge concentration in the silicon monocrystal, an average temperature gradient Gave (K/mm) and a pull speed V (mm/min) are controlled to satisfy a formula (1) as follows, the phosphorus concentration [P] (atoms/cm3) in the silicon monocrystal is 4.84×1019 atoms/cm3 or more and 8.49×1019 atoms/cm3 or less, and the phosphorus concentration [P] (atoms/cm3) and the Ge concentration [Ge] (atoms/cm3) in the silicon monocrystal satisfy a relationship according to a formula (2) as follows while growing the silicon monocrystal. [P]L+(0.3151×[Ge]+3.806×1019)/1.5<0.5×(Gave/V+43)×1019??(1) [Ge]?6.95×[P]+5.90×1020??(2).
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 5, 2013
    Assignee: Sumco Techxiv Corporation
    Inventors: Shinichi Kawazoe, Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa
  • Publication number: 20130285123
    Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8569831
    Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Lars P. Heineck, Shyam Surthi, Jaydip Guha
  • Publication number: 20130270572
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Applicant: HRL LABORATORIES, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Publication number: 20130273700
    Abstract: Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates. The bodies of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that formed by etching holes in the layer in which word lines are formed. Gate electrodes and gate dielectrics may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes.
    Type: Application
    Filed: January 2, 2013
    Publication date: October 17, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Peter Rabkin, Masaaki Higashitani
  • Publication number: 20130260542
    Abstract: The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines SRAM NMOSFETs regions and SRAM PMOSFETs regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the SRAM PMOSFETs regions and using the pre-implantation photo mask to pre-implanting the third-group elements.
    Type: Application
    Filed: December 20, 2012
    Publication date: October 3, 2013
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Liujiang YU
  • Publication number: 20130255738
    Abstract: Phononic structures, devices related to phononic structures, and methods related to fabrication of the phononic structures are described. The phononic structure can include a sheet of material, where the sheet of material can include a plurality of regions. Adjacent regions in the sheet of material can have dissimilar phononic patterns.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 3, 2013
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Slobodan MITROVIC, Jen-Kan YU, James R. HEATH
  • Publication number: 20130256789
    Abstract: A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: SUNG-NIEN TANG, HSIU-WEN HSU