Abstract: Methods and apparatus for a carbon ion source head. An ionization chamber is configured to receive a process gas containing carbon and a noble carrier gas; a cathode is disposed in the ionization chamber and configured to emit electrons in thermionic emission; a graphite coating is provided on at least a portion of the cathode; and an outlet on the ionization chamber is configured to output carbon ions. A method for ion implantation of carbon is disclosed. Additional alternative embodiments are disclosed.

Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.

Abstract: According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.

Abstract: Disclosed is a photosensitive resin composition which exhibits positive or negative photosensitivity and is used as a mask in an ion implantation step, the photosensitive resin composition including, as a resin, (A) a polysiloxane. The photosensitive resin composition of the present invention has high heat resistance and is capable of controlling a pattern shape, and also has excellent ion implantation mask performance, thus enabling application to a low-cost high-temperature ion implantation process.

Abstract: New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols.

Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.

Abstract: An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts.

Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.

Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: A single crystal semiconductor substrate is irradiated with ions that are generated by exciting a hydrogen gas and are accelerated with an ion doping apparatus, thereby forming a damaged region that contains a large amount of hydrogen. After the single crystal semiconductor substrate and a supporting substrate are bonded, the single crystal semiconductor substrate is heated to be separated along the damaged region. While a single crystal semiconductor layer separated from the single crystal semiconductor substrate is heated, this single crystal semiconductor layer is irradiated with a laser beam. The single crystal semiconductor layer undergoes re-single-crystallization by being melted through laser beam irradiation, thereby recovering its crystallinity and planarizing the surface of the single crystal semiconductor layer.

Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.

Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

Abstract: An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Abstract: An improved method of tilting a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. The mask and substrate are tilted at a first angle relative to the incoming ion beam. After the substrate is exposed to the ion beam, the mask and substrate are tilted at a second angle relative to the ion beam and a subsequent implant step is performed. Through the selection of the aperture size and shape, the cross-section of the mask, the distance between the mask and the substrate and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions.

Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.

Abstract: A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus.

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.

Abstract: After adding phosphorus (P) and germanium (Ge) into a silicon melt or adding phosphorus into a silicon/germanium melt, a silicon monocrystal is grown from the silicon melt by a Czochralski method, where a phosphorus concentration [P]L(atoms/cm3) in the silicon melt, a Ge concentration in the silicon monocrystal, an average temperature gradient Gave (K/mm) and a pull speed V (mm/min) are controlled to satisfy a formula (1) as follows, a phosphorus concentration [P](atoms/cm3) and the Ge concentration [Ge](atoms/cm3) in the silicon monocrystal satisfy a relationship according to a formula (2) as follows while growing the silicon monocrystal, where dSi(?) represents a lattice constant of silicon, rSi(?) represents a covalent radius of silicon, rP(?) represents a covalent radius of phosphorus, and rGe(?) represents a covalent radius of Ge: [ P ] L + ( 0.3151 × [ Ge ] + 3.806 × 10 18 ) / 1.5 < 0.

Abstract: Systems and methods for preparing films using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure and including ions having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include the ions being covalently bonded to each other, to the embedded structure, or to the substrate, whereas the ions instead may be free to diffuse through the substrate in the absence of the embedded structure. The embedded structure may inhibit or impede the ions from diffusing through the substrate, such that the ions instead covalently bond to each other, to the embedded structure, or to the substrate. The film may include, for example, diamond-like carbon, graphene, or SiC having a pre-selected phase.

Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.

Abstract: An ion implantation apparatus includes a beamline device for transporting ions from an ion source to an implantation processing chamber. The implantation processing chamber includes a workpiece holder for mechanically scanning a workpiece with respect to a beam irradiation region. The beamline device may be operated under a first implantation setting configuration suitable for transport of a low energy/high current beam for high-dose implantation into the workpiece, or a second implantation setting configuration suitable for transport of a high energy/low current beam for low-dose implantation into the workpiece. A beam center trajectory being a reference in a beamline is equal from the ion source to the implantation processing chamber in the first implantation setting configuration and the second implantation setting configuration.

Abstract: An electro-static discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first silicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses.

Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.

Abstract: Methods of implanting dopant ions in a substrate include depositing a sacrificial material on a substrate. Dopant ions are implanted into the substrate while sputtering the sacrificial material, without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after the implanting of the dopant ions. Some methods include forming a sacrificial material over a substrate and implanting dopant ions into the substrate while removing substantially all the sacrificial material from the substrate. Substantially no sputtering of the substrate occurs during the implanting of the dopant ions. Methods of doping a substrate include implanting dopant ions into a substrate having a sacrificial material thereon and sputtering the sacrificial material while implanting the dopant ions without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after implanting the dopant ions.

Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion regions in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

Abstract: An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: One method of implanting a workpiece involves implanting the workpiece with an n-type dopant in a first region with center and a periphery. The workpiece also is implanted with a p-type dopant in a second region complementary to the first region. This second region also has a center and a periphery. The periphery of the first region and the periphery of the second region at least partially overlap. A dose at the periphery of the first region or second region is less than a dose at the center of the first region or second region. The region of overlap may function as a junction where charge carriers cannot pass.

Abstract: Solar cells in accordance with the present invention have reduced ohmic losses. These cells include photo-receptive regions that are doped less densely than adjacent selective emitter regions. The photo-receptive regions contain multiple four-sided pyramids that decrease the amount of light lost to the solar cell by reflection. The smaller doping density in the photo-receptive regions results in less blue light that is lost by electron-hole recombination. The higher doping density in the selective emitter region allows for better contacts with the metallic grid coupled to the multiple emitter regions. Preferably, the selective emitter and photo-receptive regions are both implanted using a narrow ion beam containing the dopants.

Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.

Abstract: A method and apparatus are disclosed for controlling a semiconductor process temperature. In one embodiment a thermal control device includes a heat source and a housing comprising a vapor chamber coupled to the heat source. The vapor chamber includes an evaporator section and a condenser section. The evaporator section has a first wall associated with the heat source, the first wall having a wick for drawing a working fluid from a lower portion of the vapor chamber to the evaporator section. The condenser section coupled to a cooling element. The vapor chamber is configured to transfer heat from the heat source to the cooling element via continuous evaporation of the working fluid at the evaporator section and condensation of the working fluid at the condenser section. Other embodiments are disclosed and claimed.

Abstract: The present invention discloses a method of adding an additional mask in the ion-implantation process. It relates to technical field of ion implantation. This invention comprises: a mask plate is added upon the said MPW and the nitrogen element is implanted in the said MPW; the implanted nitrogen element is used for amorphizing the upper surface of the MPW. The advantageous effects of the above technical solution are as follows: the steps of the production process are simplified; the ion implantation mask will achieve 4 different doping concentrations of the ion implantation when the wafer is implanted. It means that it is possible to form 4 different gate oxide layers of different in thickness. However, it is essential to apply the photomask three times to achieve the same effect in the process of prior art. Consequently, the method of the present invention can reduce both the cost and the term of production process.

Abstract: A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.

Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

Abstract: An improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for processing a substrate. The method may comprise ion implanting a substrate disposed downstream of the ion source with ions generated in an ion source; and disposing a first portion of a mask in front of the substrate to expose the first portion of the mask to the ions, the mask being supported by the first and second mask holders, the mask further comprising a second portion wound in the first mask holder.

Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.

Abstract: The present invention relates generally to methods for high throughput and controllable creation of high performance semiconductor substrates for use in devices such as high sensitivity photodetectors, imaging arrays, high efficiency solar cells and the like, to semiconductor substrates prepared according to the methods, and to an apparatus for performing the methods of the invention.

Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.

Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.

Abstract: In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin.

Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.