Of Compound Semiconductor Patents (Class 438/518)
  • Patent number: 8084282
    Abstract: Wafer-level bonding of the hybrid laser portion of a silicon photonics platform is done by forming a weakened level in a semiconductive pillar that supports laser-active layers by ion implantation into the semiconductive pillar without penetrating the laser-active layers, and by separating the laser-active layers from the semiconductive pillar by cracking the weakened level by an epitaxial lift-off processes.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: John Heck, Richard Jones, Matthew N. Sysak
  • Patent number: 8062918
    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: November 22, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Michael Miller, Prashant Phatak, Tony Chiang, Xiying Chen, April Schricker, Tanmay Kumar
  • Patent number: 8043947
    Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 25, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Angelo Pinto, Weize Xiong, Manfred Ramin
  • Patent number: 8039375
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: October 18, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
  • Patent number: 8030665
    Abstract: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are laminated to form a stack of nitride semiconductor on the first face of the substrate 1. A first bonding layer including more than one metal layer is formed on the p-type nitride semiconductor layer 8. A supporting substrate having a first and second face has a thermal expansion coefficient that is larger than that of the nitride semiconductor and is equal or smaller than that of the substrate 1 for growing nitride semiconductor. A second bonding layer including more than one metal layer is formed on the first face of the supporting substrate. The first bonding layer 9 and the second bonding layer 11 are faced with each other and, then, pressed with heat to bond together.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: October 4, 2011
    Assignee: Nichia Corporation
    Inventors: Shinichi Nagahama, Masahiko Sano, Tomoya Yanamoto, Keiji Sakamoto, Masashi Yamamoto, Daisuke Morita
  • Patent number: 8012837
    Abstract: A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Chiharu Ota, Takuma Suzuki, Hiroshi Kono, Makoto Mizukami, Takashi Shinohe
  • Patent number: 8003452
    Abstract: A compound semiconductor device includes a carrier transit layer formed over a substrate; a carrier supply layer formed over the carrier transit layer; a first metal film and a second metal film formed over the carrier supply layer; a first Al comprising film formed over the first metal film; a second Al comprising film formed over the second metal film; a first Au comprising film formed over the first metal film and is free of direct contact with the first Al comprising film; a second Au comprising film formed over the second metal film and free of direct contact with the second Al comprising film; and a gate electrode that is located over the carrier supply layer between the first metal film and the second metal film.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Limited
    Inventor: Toshihiro Ohki
  • Publication number: 20110195563
    Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.
    Type: Application
    Filed: October 6, 2010
    Publication date: August 11, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Okuno, Yoichiro Tarui
  • Patent number: 7977223
    Abstract: A method of forming a nitride semiconductor through ion implantation and an electronic device including the same are disclosed. In the method, an ion implantation region composed of a line/space pattern is formed on a substrate at an ion implantation dose of more than 1E17 ions/cm2 to 5E18 ions/cm2 or less and an ion implantation energy of 30˜50 keV, and a metal nitride thin film is grown on the substrate by epitaxial lateral overgrowth, thereby decreasing lattice defects in the metal nitride thin film. Thus, the electronic device has improved efficiency.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Korea University Industrial & Academic Collaboration Foundation
    Inventors: Dong-Jin Byun, Bum-Joon Kim, Jung-Geun Jhin, Jong-Hyeob Baek
  • Publication number: 20100327288
    Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Applicant: PFC DEVICE CORPORATION
    Inventors: Kou-Liang CHAO, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
  • Patent number: 7834422
    Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallized to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: November 16, 2010
    Assignee: Qucor Pty. Ltd.
    Inventors: Soren Andresen, Andrew Steven Dzurak, Eric Gauja, Sean Hearne, Toby Felix Hopf, David Norman Jamieson, Mladen Mitic, Steven Prawer, Changyi Yang
  • Patent number: 7785993
    Abstract: A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: August 31, 2010
    Assignee: NXP B.V.
    Inventors: Bartlomiej J Pawlak, Philippe Meunier-Beillard
  • Patent number: 7767583
    Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: August 3, 2010
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak Ramappa, Thirumal Thanigaivelan
  • Patent number: 7759186
    Abstract: Methods for producing a junction termination extension surrounding the edge of a cathode or anode junction in a semiconductor substrate, where the junction termination extension has a controlled arbitrary lateral doping profile and a controlled arbitrary lateral width, are provided. A photosensitive material is illuminated through a photomask having a pattern of opaque and clear spaces therein, the photomask being separated from the photosensitive material so that the light diffuses before striking the photosensitive material. After processing, the photosensitive material so exposed produces a laterally tapered implant mask. Dopants are introduced into the semiconductor material and follow a shape of the laterally tapered implant mask to create a controlled arbitrary lateral doping profile and a controlled lateral width in the junction termination extension in the semiconductor.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: July 20, 2010
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Eugene A. Imhoff, Francis J. Kub, Karl D. Hobart
  • Patent number: 7754590
    Abstract: Some embodiments of the invention relate to manufacturing a semiconductor device with an implantation layer on a semiconductor substrate including a method of manufacturing such an implantation layer, wherein said implantation layer is formed in an implantation step at a predetermined depth of penetration, determined from a top surface of said semiconductor substrate, using a particle beam, by increasing its path distance to a main implantation peak and correspondingly increasing the energy level of said particle beam for producing an undamaged implantation layer having a thickness that is increased significantly compared with the thickness of an implantation layer that would be produced at said predetermined depth of penetration using a particle beam with non-increased path distance and energy level.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 13, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Holger Schulze, Andreas Kyek
  • Patent number: 7754589
    Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: July 13, 2010
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Liutauras Storasta
  • Patent number: 7737011
    Abstract: It is an object to provide a method for improving the quality of an SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and an SiC semiconductor device fabricated by the method. A method for improving the quality of an SiC layer by eliminating or reducing some carrier trapping centers comprising the steps of: (a) carrying out ion implantation of carbon atoms (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. A semiconductor device according to the invention is fabricated by the method.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: June 15, 2010
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Liutauras Storasta
  • Patent number: 7700467
    Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: April 20, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Scott Gregory Bushman, Periannan Chidambaram
  • Patent number: 7691729
    Abstract: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed of the stem and the cap. The method for producing this nitride semiconductor, laser light source has a cleaning step of cleaning the surface of the laser chip, the stem, or the cap. In the cleaning step, the laser chip, the stem, or the cap is exposed with ozone or an excited oxygen atom, or baked by heat. The method also has, after the cleaning step, a capping step of encapsulating the laser chip in the sealed container composed of the stem and the cap. During the capping step, the cleaned surface of the laser chip, the stem, or the cap is kept clean.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: April 6, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Daisuke Hanaoka, Masaya Ishida, Atsushi Ogawa, Yoshihiko Tani, Takuro Ishikura
  • Patent number: 7615401
    Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: November 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Hee Park, Ju-Chul Park, Jun-Soo Bae, Bong-Jin Kuh, Yong-Ho Ha
  • Patent number: 7601621
    Abstract: A method of forming surface irregularities comprises preparing a GaN substrate; forming a mask on a surface of the GaN substrate, the mask defining a surface-irregularity formation region; and wet-etching portions of the surface of the GaN substrate by using the mask as an etching mask. The wet-etching of the GaN substrate is performed until the end of one surface of the GaN substrate to be formed by the wet-etching using the mask meets the end of another surface of the GaN substrate to be formed by the wet-etching using the mask, the another surface being adjacent to the one surface.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: October 13, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Pun Jae Choi, Masayoshi Koike, Lee Jong Ho
  • Publication number: 20090250705
    Abstract: A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C.
    Type: Application
    Filed: November 7, 2008
    Publication date: October 8, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tomokatsu WATANABE, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
  • Publication number: 20090230513
    Abstract: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded.
    Type: Application
    Filed: November 15, 2007
    Publication date: September 17, 2009
    Applicant: SAMSUNG CORNING PRECISION GLASS CO., LTD.
    Inventors: Young Zo Yoo, Hyun Min Shin, Jun Sung Choi
  • Patent number: 7575988
    Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: August 18, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Konstantin Bourdelle, Carlos Mazure, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Olivier Rayssac
  • Patent number: 7557021
    Abstract: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: July 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Amitabh Jain
  • Patent number: 7482214
    Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: January 27, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Timothy A. Rost
  • Publication number: 20080311686
    Abstract: A method of making a semiconductor thin film bonded to a handle substrate includes implanting a semiconductor substrate with a light ion species while cooling the semiconductor substrate, bonding the implanted semiconductor substrate to the handle substrate to form a bonded structure, and annealing the bonded structure, such that the semiconductor thin film is transferred from the semiconductor substrate to the handle substrate.
    Type: Application
    Filed: August 2, 2006
    Publication date: December 18, 2008
    Inventors: Anna Fontcuberta i Morral, Sean M. Olson
  • Publication number: 20080286953
    Abstract: In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention provides an SOI substrate having a desired shape even when a step is produced on a surface to be bonded. Between steps on the surface to be bonded, dummy patterns 302 are formed at predetermined intervals, and thus the warp of the substrate to be bonded can be suppressed, the adhesion between the bonded substrates can be ensured, and an SOI layer having a desired shape can be obtained.
    Type: Application
    Filed: March 26, 2008
    Publication date: November 20, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7419892
    Abstract: Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, and annealing the semiconductor layer and the protective layer to activate the implanted ions. An opening is formed in the protective layer to expose the implanted region of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: September 2, 2008
    Assignee: Cree, Inc.
    Inventors: Scott T. Sheppard, Adam Saxler
  • Patent number: 7417248
    Abstract: A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: August 26, 2008
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Publication number: 20080194086
    Abstract: There is provided a method of introducing impurity capable of efficiently realizing a shallow impurity introduction. The impurity introducing method includes a first step of making a surface of a semiconductor layer to be amorphous by reacting plasma composed of particles which are electrically inactive in the semiconductor layer to a surface of a solid base body including the semiconductor layer, and a second step of introducing impurity to the surface of the solid base body. After performing the first step, by performing the second step, an amorphous layer with fine pores is formed on the surface of the solid base body including the semiconductor layer, and impurity are introduced in the amorphous layer to form an impurity introducing layer.
    Type: Application
    Filed: May 31, 2005
    Publication date: August 14, 2008
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Katsumi Okashita, Cheng-Guo Jin, Hiroyuki Ito
  • Patent number: 7410876
    Abstract: A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode; (c) creating first (219) and second (220) spacer structures adjacent to first and second sides of the gate electrode, wherein the first and second spacer structures overlap the first and second pre-amorphization implant regions; and (d) creating source (217) and drain (218) regions in the substrate adjacent, respectively, to the first and second spacer structures.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: August 12, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Byoung W. Min, Jon D. Cheek, Venkat R. Kolagunta
  • Publication number: 20080179703
    Abstract: The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
    Type: Application
    Filed: September 12, 2007
    Publication date: July 31, 2008
    Inventors: Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel
  • Patent number: 7405131
    Abstract: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.
    Type: Grant
    Filed: July 16, 2005
    Date of Patent: July 29, 2008
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)
    Inventors: Yung Fu Chong, Brian Joseph Greene
  • Patent number: 7378334
    Abstract: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are laminated to form a stack of nitride semiconductor on the first face of the substrate 1. A first bonding layer including more than one metal layer is formed on the p-type nitride semiconductor layer 8. A supporting substrate having a first and second face has a thermal expansion coefficient that is larger than that of the nitride semiconductor and is equal or smaller than that of the substrate 1 for growing nitride semiconductor. A second bonding layer including more than one metal layer is formed on the first face of the supporting substrate. The first bonding layer 9 and the second bonding layer 11 are faced with each other and, then, pressed with heat to bond together.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: May 27, 2008
    Assignee: Nichia Corporation
    Inventors: Shinichi Nagahama, Masahiko Sano, Tomoya Yanamoto, Keiji Sakamoto, Masashi Yamamoto, Daisuke Morita
  • Patent number: 7378681
    Abstract: A method for reducing surface recombination in an area next to a mesa in devices containing active and passive sections. This is obtained by growing, by metalorganic vapor phase epitaxy (MOVPE), a thin epitaxial layer of material with larger bandgap than a waveguide material and preferably smaller surface recombination rate than the waveguide material. This thin layer is preferably non-intentionally doped to avoid creating a surface leakage path, thin enough to allow for carrier to diffuse to and thermalize in the waveguide layer and thick enough to prevent carriers to tunnel through it.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 27, 2008
    Assignee: Agility Communications, Inc.
    Inventor: Patrick Abraham
  • Publication number: 20080116494
    Abstract: The invention relates to a method for manufacturing a semiconductor device. A silicon substrate comprising at least one structured area in which a dopant is implanted is provided. A contact modifying material is provided on the surface of the at least one structured area. A silicide layer is formed on the surface of the at least one structured area, the silicide layer comprising at least one of titan silicide, titan nitride silicide and cobalt silicide.
    Type: Application
    Filed: November 20, 2006
    Publication date: May 22, 2008
    Inventors: Matthias Goldbach, Dietmar Henke, Sven Schmidbauer
  • Patent number: 7364993
    Abstract: A semiconductor material with photoconductive properties and a method of the semiconductor, wherein a base material is grown and then annealed post-growth at a temperature of 475° C. or less. It has been found that be annealing at temperatures of 475° C., or less the carrier lifetime of the material and the resistivity can be optimized so as to obtain semiconductor with useful photoconductive properties.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: April 29, 2008
    Assignee: TeraView Limited
    Inventors: Michael J. Evans, William R. Tribe
  • Publication number: 20080003752
    Abstract: A method for fabricating a transistor having a Group III-V semiconductor substrate with an oxygen-free dielectric disposed between the substrate and a gate is described.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Matthew V. Metz, Mark L. Doczy, Suman Datta
  • Patent number: 7276431
    Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: October 2, 2007
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Patent number: 7268065
    Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Patent number: 7172933
    Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
  • Patent number: 7084051
    Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved. The invention provides a manufacturing method for a semiconductor substrate with the steps of: forming a SiGe film on the top surface of a substrate having a silicon monocrystal layer in the (111) or (110) plane direction as the surface layer; introducing buried crystal defects into the above described substrate by carrying out ion implantation and annealing treatment; and forming a semiconductor film on the above described SiGe film.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: August 1, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takashi Ueda
  • Patent number: 7078300
    Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.
    Type: Grant
    Filed: September 27, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Evgeni Gousev, Huiling Shang, Christopher P. D'Emic, Paul M. Kozlowski
  • Patent number: 7056815
    Abstract: A method for forming a semi-conductor material is provided that comprises forming a donor substrate constructed of GaAs, providing a receiver substrate, implanting nitrogen into the donor substrate to form an implanted layer comprising GaAs and nitrogen. The implanted layer is bonded to the receiver substrate and annealed to form GaAsN and nitrogen micro-blisters in the implanted layer. The micro-blisters allow the implanted layer to be cleaved from the donor substrate.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: June 6, 2006
    Assignee: The Regents of the University of Michigan
    Inventors: Xiaojun Weng, Rachel S. Goldman
  • Patent number: 7041530
    Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 9, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Nunoshita, Ichiro Yamashita, Shigeo Yoshii
  • Patent number: 7029969
    Abstract: A semiconductor device and its manufacturing method in which the trade-off relationship between channel resistance and JFET resistance is improved. The same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET including SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: April 18, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi, Hiroshi Sugimoto, Tetsuya Takami
  • Patent number: 6949453
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: September 27, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Jiutao Li
  • Patent number: 6946372
    Abstract: A method of manufacturing a gallium nitride (GaN)-based semiconductor light emitting device includes forming a contact resistance improved layer on a p-type GaN-based semiconductor layer with at least one metal selected from the group of Au, Mg, Mn, Mo, Pd, Pt, Sn, Ti and Zn, heat-treating the p-type GaN-based semiconductor layer so that elements in the contact resistance improved layer diffuse into the p-type GaN-based semiconductor layer and that Ga elements in the p-type GaN-based semiconductor layer dissolve into the contact resistance improved layer, and removing the contact resistance improved layer remaining on the p-type GaN-based semiconductor layer.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: September 20, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Hyun Kyung Kim
  • Patent number: 6939731
    Abstract: When a p-type MgxZn1-xO-type layer is grown based on a metal organic vapor-phase epitaxy process, the p-type MgxZn1-xO-type layer is annealed in an oxygen-containing atmosphere during and/or after completion of the growth of the p-type MgxZn1-xO-type layer. In addition, a vapor-phase epitaxy process of a semiconductor layer is proceed while irradiating ultraviolet light to the surface of a substrate to be grown and source gasses. In addition, when a MgxZn1-xO-type buffer layer that is oriented so as to align the c-axis thereof to a thickness-wise direction is formed by an atomic layer epitaxy process, a metal monoatomic layer is grown at first. In addition, a ZnO-base semiconductor active layer is formed by using a semiconductor material mainly composed of ZnO containing Se or Te. A light emitting device is formed by using these techniques.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 6, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Jun-ya Ishizaki