Providing Nondopant Ion (e.g., Proton, Etc.) Patents (Class 438/520)
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Patent number: 7494852Abstract: A method of forming a surface Ge-containing channel which can be used to fabricate a Ge-based field effect transistor (FET) which can be applied to semiconductor-on-insulator substrates (SOIs) is provided. The disclosed method uses Ge-containing ion beams, such as cluster ion beams, to create a strained Ge-containing rich region at or near a surface of a SOI substrate. The Ge-containing rich region can be present continuously across the entire surface of the semiconductor substrate, or it can be present as a discrete region at a predetermined surface portion of the semiconductor substrate.Type: GrantFiled: January 6, 2005Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Bruce B. Doris, Devendra K. Sadana
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Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
Patent number: 7479431Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.Type: GrantFiled: December 17, 2004Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer -
Patent number: 7465633Abstract: Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.Type: GrantFiled: January 12, 2007Date of Patent: December 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-whan Song, Chang-kyun Kim
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Patent number: 7422936Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.Type: GrantFiled: August 25, 2004Date of Patent: September 9, 2008Assignee: Intel CorporationInventors: Chris E. Barns, Matt Prince, Mark L. Doczy, Justin K. Brask, Jack Kavalieros
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Patent number: 7417248Abstract: A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).Type: GrantFiled: June 5, 2006Date of Patent: August 26, 2008Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 7396747Abstract: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.Type: GrantFiled: August 16, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Juan Cai, Kevin K. Chan, Patricia M. Mooney, Kern Rim
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Patent number: 7381584Abstract: A CMOS image sensor and method for fabricating the same is disclosed that reconditions, repairs and/or protects a surface of a photodiode area and improves characteristics of the image sensor. The method includes forming a photodiode area and a plurality of transistors, implanting a predetermined ion into a surface of the photodiode area, and forming a surface oxide film on the surface of the photodiode area by oxidation. Therefore, it is possible to recover or repair the photodiode surface damaged during various fabrication processes, reduce or minimize surface leakage of the photodiode during subsequent processes, and improve image sensor characteristics by increasing incident light on the photodiode.Type: GrantFiled: August 31, 2005Date of Patent: June 3, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Keun Hyuk Lim
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Patent number: 7338822Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.Type: GrantFiled: May 6, 2004Date of Patent: March 4, 2008Assignee: Cree, Inc.Inventors: Yifeng Wu, Gerald H. Negley, David B. Slater, Jr., Valeri F. Tsvetkov, Alexander Suvorov
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Patent number: 7303967Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.Type: GrantFiled: June 23, 2004Date of Patent: December 4, 2007Assignee: Hynix Semiconductor Inc.Inventor: Seung Hoon Sa
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Patent number: 7294527Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide.Type: GrantFiled: October 27, 2005Date of Patent: November 13, 2007Assignee: Micron Technology Inc.Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore
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Patent number: 7276431Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: February 25, 2005Date of Patent: October 2, 2007Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7273800Abstract: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.Type: GrantFiled: November 1, 2004Date of Patent: September 25, 2007Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Juan Cai, Kevin K. Chan, Patricia M. Mooney, Kern Rim
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Patent number: 7268065Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: GrantFiled: June 18, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Publication number: 20070166933Abstract: Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.Type: ApplicationFiled: January 12, 2007Publication date: July 19, 2007Inventors: Ki-whan Song, Chang-kyun Kim
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Patent number: 7226848Abstract: A method of hydrogen sintering a substrate including a semiconductor device formed thereon comprises the steps of exciting a processing gas comprising a noble gas and a hydrogen gas to form a plasma comprising hydrogen radicals and hydrogen ions, and exposing the substrate to the plasma. A preferred method comprises forming a gate insulation film on a substrate, forming a polysilicon electrode on the gate insulation film, and exposing the polysilicon electrode to an atmosphere comprising hydrogen radicals and hydrogen ions.Type: GrantFiled: December 25, 2002Date of Patent: June 5, 2007Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
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Patent number: 7163878Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).Type: GrantFiled: November 4, 2005Date of Patent: January 16, 2007Assignee: Texas Instruments IncorporatedInventors: Puneet Kohli, Mark Rodder, Rick Wise, Amitabh Jain
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Patent number: 7118979Abstract: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.Type: GrantFiled: November 5, 2003Date of Patent: October 10, 2006Assignee: Texas Instruments IncorporatedInventors: Kaiping Liu, Zhiqiang Wu, Majid Movahed Mansoorz
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Patent number: 7094671Abstract: A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).Type: GrantFiled: March 22, 2004Date of Patent: August 22, 2006Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 7078300Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.Type: GrantFiled: September 27, 2003Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Evgeni Gousev, Huiling Shang, Christopher P. D'Emic, Paul M. Kozlowski
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Patent number: 7018885Abstract: Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of an ion for adjusting the threshold voltage into the bottom of the channel region, occurring in a subsequent annealing process, and prohibit behavior of the ion at the channel region when a high voltage is applied to a P well. Further, the anti-diffusion layer serves as a layer to gather defects, etc. existing in the semiconductor substrate. Also, as the amount of channel ion could be adjusted by controlling the implantation depth of the inert ion, it is possible to control the threshold voltage of the device depending on higher integration.Type: GrantFiled: March 10, 2005Date of Patent: March 28, 2006Assignee: Hynix Semiconductor Inc.Inventor: Noh Yeal Kwak
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Patent number: 6998303Abstract: An insulating film made of zirconia or hafnia is formed on the surface of a semiconductor substrate. A partial surface area of the insulating film is covered with a mask pattern. By using the mask pattern as a mask, ions are implanted into a region of the insulating film not covered with the mask pattern to give damages to the insulating film. By using the mask pattern as a mask, a portion of the insulating film is etched.Type: GrantFiled: August 5, 2003Date of Patent: February 14, 2006Assignee: Fujitsu LimitedInventors: Yoshihiro Sugita, Yusuke Morisaki, Kiyoshi Irino, Shiqin Xiao, Takayuki Ohba
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Patent number: 6989319Abstract: Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer.Type: GrantFiled: November 24, 2003Date of Patent: January 24, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Mark Ramsbey, Sameer Haddad, Vei-Han Chan, Yu Sun, Chi Chang
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Patent number: 6981240Abstract: A full phase shifting mask (FPSM) can define substantially all of the features of an integrated circuit using pairs of shifters having opposite phase. In particular, cutting patterns for working with the polysilicon, or gate, layers and active layers of static random access memory (SRAM) cells are considered. To resolve phase conflicts between shifters, one or more cutting patterns can be selected. These cutting patterns include cuts on contact landing pads. This cut simplifies the FPSM layout while ensuring greater critical dimension control of the more important features and reducing mask misalignment sensitivity.Type: GrantFiled: January 10, 2003Date of Patent: December 27, 2005Assignee: Synopsys, Inc.Inventors: Christophe Pierrat, Michel Luc Côté
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Patent number: 6967147Abstract: Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.Type: GrantFiled: November 16, 2000Date of Patent: November 22, 2005Assignee: Infineon Technologies AGInventors: Helmut Horst Tews, Jochen Beintner
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Patent number: 6946337Abstract: Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of an ion for adjusting the threshold voltage into the bottom of the channel region, occurring in a subsequent annealing process, and prohibit behavior of the ion at the channel region when a high voltage is applied to a P well. Further, the anti-diffusion layer serves as a layer to gather defects, etc. existing in the semiconductor substrate. Also, as the amount of channel ion could be adjusted by controlling the implantation depth of the inert ion, it is possible to control the threshold voltage of the device depending on higher integration.Type: GrantFiled: July 10, 2003Date of Patent: September 20, 2005Assignee: Hynix Semiconductor Inc.Inventor: Noh Yeal Kwak
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Patent number: 6916693Abstract: In a crystallization process of an amorphous semiconductor film, a first crystalline semiconductor film having crystalline regions, and dotted with amorphous regions within the crystalline regions, is obtained by performing heat treatment processing after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. The amorphous regions are kept within a predetermined range by regulating the heat treatment conditions at this point. Laser annealing is performed on the first crystalline semiconductor film, to form a second crystalline semiconductor film. Electrical characteristics for a TFT manufactured based on the second crystalline semiconductor film can be obtained having less dispersion.Type: GrantFiled: March 5, 2001Date of Patent: July 12, 2005Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Hideto Ohnuma, Chiho Kokubo, Koichiro Tanaka, Naoki Makita, Shuhei Tsuchimoto
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Patent number: 6897118Abstract: A method for forming a highly activated ultra shallow ion implanted semiconductive elements for use in sub-tenth micron MOSFET technology is described. A key feature of the method is the ability to activate the implanted impurity to a highly active state without permitting the dopant to diffuse further to deepen the junction. A selected single crystalline silicon active region is first amorphized by implanting a heavy ion such as silicon or germanium. A semiconductive impurity for example boron is then implanted and activated by pulsed laser annealing whereby the pulse fluence, frequency, and duration are chosen to maintain the amorphized region just below it's melting temperature. It is found that just below the melting temperature there is sufficient local ion mobility to secure the dopant into active positions within the silicon matrix to achieve a high degree of activation with essentially no change in concentration profile.Type: GrantFiled: February 11, 2004Date of Patent: May 24, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chyiu-Hyia Poon, Byung Jin Cho, Yong Feng Lu, Alex See, Mousumi Bhat
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Patent number: 6855994Abstract: A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.Type: GrantFiled: November 29, 1999Date of Patent: February 15, 2005Assignee: The Regents of the University of CaliforniaInventors: Ya-Chin King, Tsu-Jae King, Chen Ming Hu
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Patent number: 6849527Abstract: The mobility enhancement of a strained silicon layer is augmented through incorporation of carbon into a strained silicon lattice to which strain is also imparted by an underlying silicon germanium layer. The presence of the relatively small carbon atoms effectively increases the spacing within the strained silicon lattice and thus imparts additional strain. This enhancement may be implemented for any MOSFET device including silicon on insulator MOSFETs, and is preferably selectively implemented for the PMOS components of CMOS devices to achieve approximately equal carrier mobility for the PMOS and NMOS devices.Type: GrantFiled: October 14, 2003Date of Patent: February 1, 2005Assignee: Advanced Micro DevicesInventor: Qi Xiang
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Patent number: 6838395Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.Type: GrantFiled: December 30, 2002Date of Patent: January 4, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Teruhito Ohnishi, Ken Idota, Tohru Saitoh, Akira Asai
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Patent number: 6828169Abstract: A method of forming a group-III nitride semiconductor layer on a light-emitting device. First, a substrate is provided. Next, a buffer layer is formed on the substrate. A hydrogen treatment is performed on the buffer layer. Finally, a group-III nitride semiconductor layer is formed on the buffer layer. According to the present invention, a hydrogen treatment is performed on the buffer to prevent corrosion during subsequent process and remove particles from the buffer layer. Thus, the structure of the epitaxy layer following formed on the buffer layer is enhanced.Type: GrantFiled: June 17, 2003Date of Patent: December 7, 2004Assignee: Vetra Technology, Inc.Inventors: Kazutaka Terashima, Mu-Jen Lai, Chiung-Yu Chang
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Patent number: 6806153Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.Type: GrantFiled: June 17, 2003Date of Patent: October 19, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Manfred Horstmann, Thomas Feudel
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Patent number: 6803275Abstract: Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.Type: GrantFiled: December 3, 2002Date of Patent: October 12, 2004Assignee: FASL, LLCInventors: Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Inkuk Kang, Tazrien Kamal, Amir H. Jafarpour
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Patent number: 6797594Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: GrantFiled: February 14, 2001Date of Patent: September 28, 2004Assignee: Renesas Technology Corp.Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
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Patent number: 6787436Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.Type: GrantFiled: May 15, 2002Date of Patent: September 7, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Matthew S. Buynoski, Witold Maszara
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Publication number: 20040135208Abstract: A semiconductor substrate of the present invention is a DSP wafer or Semi-DSP wafer (FIG. 2) having a flatness of an SFQR value ≦70 (nm) and containing boron at a concentration not lower than 5×1016 (atoms/cm3) nor higher than 2×1017 (atoms/cm3) within 95% or more of rectangular regions of 25×8 (mm2) arranged on a front face of the substrate. Specifically, a silicon crystal layer by an epitaxial growth is formed on a front face of a silicon substrate having the above substrate boron concentration.Type: ApplicationFiled: December 24, 2003Publication date: July 15, 2004Applicant: FUJITSU LIMITEDInventors: Katsuto Tanahashi, Hiroshi Kaneta, Tetsuo Fukuda
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Patent number: 6759312Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.Type: GrantFiled: October 16, 2002Date of Patent: July 6, 2004Assignee: The Regents of the University of CaliforniaInventors: Wladyslaw Walukiewicz, Kin M. Yu
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Patent number: 6720241Abstract: In a method for manufacturing a semiconductor device, impurity ion is implanted into a semiconductor layer so as to form an ion implantation region in the semiconductor layer, and at least the ion implantation region is turned amorphous. Then, an insulating film is formed on the semiconductor layer at a temperature at which the ion implantation region is not crystallized, and then the semiconductor layer is annealed in a non-oxidizing atmosphere so as to activate the impurity ion implanted into the semiconductor layer.Type: GrantFiled: June 17, 2002Date of Patent: April 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michikazu Matsumoto, Naohisa Sengoku, Ayumi Kobayashi
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Patent number: 6713323Abstract: A semiconductor device is manufactured by a method in which the number of heat treatments at a high temperature (600° C. or higher) is reduced to thereby achieve a process at a low temperature (600° C. or lower), and a simplified process and improvement in throughput are realized. An impurity region to which a rare gas element (also called a rare gas) is added is formed on a semiconductor film of a crystalline structure by using a mask. Gettering is performed in such a manner that a metallic element contained in the semiconductor film is caused to segregate in the impurity region by heat treatment. The impurity region is thereafter used as a source or drain region.Type: GrantFiled: January 29, 2002Date of Patent: March 30, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Takashi Hamada, Satoshi Murakami
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Patent number: 6703294Abstract: A method for producing a crystalline layer of SiC having at least a region thereof doped with boron atoms comprises a step a) of ion implantation of boron into a layer (1) of crystalline SiC and a step b) of heating the SiC-layer for annealing it for making the boron implanted therein electrically active. The method further comprises a step c) of implanting carbon atoms in said layer (1) for forming carbon interstitials in excess with respect to carbon vacancies present in the SiC-layer before carrying out step b).Type: GrantFiled: October 21, 1996Date of Patent: March 9, 2004Assignee: Cree, Inc.Inventors: Adolf Schöner, Kurt Rottner
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Patent number: 6703291Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.Type: GrantFiled: December 17, 2002Date of Patent: March 9, 2004Assignee: Intel CorporationInventors: Boyan Boyanov, Steven Keating, Anand Murthy
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Patent number: 6699764Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.Type: GrantFiled: September 9, 2002Date of Patent: March 2, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Douglas J. Tweet, Jer-shen Maa, Jong-Jan Lee, Sheng Teng Hsu
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Publication number: 20040038504Abstract: Disclosed are an ion implantation method capable of dramatically increasing an implantation rate of hydrogen ions into a semiconductor substrate and a method for manufacturing an SOI wafer, in which manufacturing efficiency of the SOI wafer is sufficiently high. When the hydrogen ions are implanted to a predetermined depth of the semiconductor substrate, hydrogen gas is introduced into a chamber where an inner pressure is reduced and a predetermined magnetic field is formed, plasma is generated by introducing a microwave into the magnetic field, hydrogen ion beams containing hydrogen molecule ions is extracted from the plasma, and the hydrogen molecule ions are irradiated and implanted onto the semiconductor substrate. Thus, a throughput in the hydrogen ion implantation is improved, thus making it possible to enhance the manufacturing efficiency of the SOI wafer.Type: ApplicationFiled: July 14, 2003Publication date: February 26, 2004Inventor: Hiroyuki Ito
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Publication number: 20040038505Abstract: The present invention provides an ion implantation method which can achieve sufficient throughput by increasing a beam current even in the case of ions with a small mass number or low-energy ions, an SOI wafer manufacturing method, and an ion implantation system. When ions are implanted by irradiating a semiconductor substrate with an ion beam, predetermined gas is excided in a pressure-reduced chamber to generate plasma containing predetermined ions, a magnetic field is formed by a solenoid coil or the like along an extraction direction when the ions are extracted to the outside of the chamber, and the ions are extracted from the chamber with predetermined extraction energy. The formation of the magnetic field promotes ion extraction, but this magnetic field has no influence on an advancing direction of the extracted ions. Therefore, the ion beam current can be kept at a high level-to contribute to the ion implantation.Type: ApplicationFiled: July 30, 2003Publication date: February 26, 2004Inventors: Hiroyuki Ito, Yasuhiko Matsunaga
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Publication number: 20040038503Abstract: A method of disordering a quantum well heterostructure, including the step of irradiating the heterostructure with a particle beam, wherein the energy of the beam is such that the beam creates a substantially constant distribution of defects within the heterostructure. The irradiating particles can be ions or electrons, and the energy is preferably such that the irradiating particles pass through the heterostructure. Light ions such as hydrogen ions are preferred because they are readily available and produce substantially uniform distributions of point defects at relatively low energies. The method can be used to tune the wavelength range of an optoelectronic device including such a heterostructure, such as a photodetector.Type: ApplicationFiled: September 8, 2003Publication date: February 26, 2004Inventors: Lan Fu, Hark Toe Tan, Chennupati Jagadish
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Publication number: 20040018701Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved.Type: ApplicationFiled: June 9, 2003Publication date: January 29, 2004Applicant: Sharp Kabushiki KaishaInventor: Takashi Ueda
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Patent number: 6681379Abstract: Methods and apparatuses for fully defining static random access memory (SRAM) using phase shifting layouts are described. The approach includes identifying that a layout includes SRAM cells and defining phase shifting regions in a mask description to fully define the SRAM cells. The phase conflicts between adjacent phase shifters are resolved by selecting cutting patterns designed for the SRAM shape and functional structure. Additionally, the transistor gates of the SRAM cells can be reduced in size relative to the original SRAM layout design. Thus, an SRAM cell can be lithographically printed with small, consistent critical dimensions including extremely small gate lengths resulting in higher yields and improved performance.Type: GrantFiled: November 15, 2001Date of Patent: January 20, 2004Assignee: Numerical Technologies, Inc.Inventors: Christophe Pierrat, Michel Luc Côté
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Patent number: 6670288Abstract: In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.Type: GrantFiled: June 27, 2000Date of Patent: December 30, 2003Assignee: Micron Technology, Inc.Inventors: Scott Jeffrey DeBoer, John T. Moore, Mark Fischer, Randhir P. S. Thakur
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Patent number: 6656774Abstract: Doping of the P type base region in a MOSFET or an IGBT with a combination of boron and one or more of indium, aluminum and gallium, provides a structure having a lower P type doping level in the channel portion of the structure than in the remainder of the structure without requiring counter doping of the channel. The doping level of the emitter region of an MCT is kept high everywhere except in the channel in order to provide a fast turn-off time for the MCT.Type: GrantFiled: September 22, 1994Date of Patent: December 2, 2003Assignee: Fairchild Semiconductor CorporationInventors: Tat-Sing Paul Chow, Victor Albert Keith Temple
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Patent number: 6653213Abstract: A structure for doping of III-V compounds is provided. The structure is a multi-layered structure in which layers of dopant are alternated with layers of initially undoped III-V compound. Dopant diffuses from the layers of dopant into the layers of III-V compound. The structure does not facilitate the introduction of impurities into the III-V compound during the diffusion of the dopant.Type: GrantFiled: December 21, 2000Date of Patent: November 25, 2003Assignee: Bookham Technology, plcInventors: Anthony J. Springthorpe, Richard W. Streater, Aniket Joshi