Abstract: A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

Abstract: A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance.

Abstract: The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The inventive semiconductor devices provide for very shallow source drain extensions which results in a reduced short channel effect.

Abstract: A method and structure for crystallizing film is disclosed. The method includes the steps of forming a film on a substrate, forming a lens on the film to focus an electro-magnetic wave on the film and directing the electro-magnetic wave on the film inclusive of the lens to crystallize the film.

Abstract: A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 .mu.m CMOS with reduced gate length variation. The localized pocket results in reduced C.sub.J. The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed.

Abstract: A method of forming a transistor is disclosed that comprises the step forming a gate insulator layer 12 on an outer surface of the substrate 10. A first gate conductor layer 22 is formed outwardly from the gate insulator layer 12. The first gate conductor layer 22 is extremely thin. Dopants are introduced into the layer 22 to render it conductive by using a diffusion source layer 24. The diffusion source layer 24 is then removed and replaced by a second gate conductor layer 26 having low resistance. The layer 26 can be used to form a T-gate structure 28, a flush gate 30, or a conventional gate structure.

Abstract: A method for fabricating a thin film transistor of a liquid crystal display device comprising the steps of introducing a dopant into an indium tin oxide layer or gate insulating layer with an ion shower doping process, forming an amorphous silicon layer thereon, exposing the amorphous silicon layer with a laser beam to diffuse the dopant into the amorphous layer and activate the dopant. As a result of the laser annealing, an n or p-type ohmic polysilicon layer and an intrinsic polysilicon channel layer can be formed. A gate electrode can also be formed on a gate insulating layer using a gate mask.

Abstract: It is the object of the invention to suppress the leakage current of a semiconductor photodiode. A trench, a side wall of which is covered with and insulating layer, is formed on the surface of a semiconductor substrate of the first conductivity type. Then, an epitaxial layer of the second conductivity type is grown in the trench, where a PN-junction is constructed between the bottom surface of the epitaxial layer and the semiconductor substrate. An impurity diffusion layer of the second conductivity type with higher impurity concentration than that of an internal portion of the epitaxial semiconductor layer is formed over the side surface of the epitaxial layer of the second conductivity type. In the aforementioned structure, when a reverse bias voltage is applied to the PN-junction, a depletion layer does not extend to a neighborhood of the insulating layer, and a leakage current, which flows via surface states near the insulating layer.

Abstract: The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is formed over the first dielectric layer. Next, the photoresist layer is patterned to define a gate region. An etching process is performed to the photoresist layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual photoresist layer as a mask. The undoped polysilicon layer is etched by using the residual photoresist layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate.

Abstract: A shallow trench isolation structure is formed by providing a pad layer and a silicon nitride polish stop layer on a surface of a P-type silicon substrate. The silicon nitride polish stop layer and the pad oxide layer are patterned to define openings corresponding to portions of the substrate that will be etched to form trenches. Trenches are defined in the P-type silicon substrate by anisotropic etching. A boron doped oxide or glass is deposited along the walls and floor of the trench. An undoped TEOS oxide is provided over the doped oxide or glass to complete filling of the trench. The device is subjected to a high temperature reflow process, causing the dielectric materials to flow, partially planarizing the device and causing the boron of the first layer to diffuse into the walls and floor of the trench. Chemical mechanical polishing removes excess portions of the dielectric layers.

Abstract: A manufacturing method of a complementary MOS transistor capable of providing line width stability at the time of lithography of gate patterning and suppressing punch through of an impurity from the silicon gate electrode to the side of a substrate is proposed.

Abstract: Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:(a) applying a dopant-containing oxide glass layer on the semiconductor surface,(b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer,(c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and(d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass.The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.

Abstract: A method and a deep sub-micron FET structure for suppressing short channel effects and reducing gate-to-drain overlay capacitance and for making CMOS devices is achieved. The method for making these improved FETs includes forming a gate oxide and a patterned polysilicon layer for gate electrodes. Silicon nitride (Si.sub.3 N.sub.4) first sidewall spacers are formed on the sidewalls of the gate electrodes. After selectively removing the gate oxide adjacent to the first sidewall spacers, second sidewall spacers are formed from a doped oxide that serve as a solid-phase diffusion source. The source/drain contact areas are implanted adjacent to the second sidewall spacers. The substrate is then annealed to diffuse from the second sidewall spacers the lightly doped source/drains (LDDs). The Si.sub.3 N.sub.4 sidewall spacers serve as a diffusion barrier and the LDDs are formed under the Si.sub.3 N.sub.

Abstract: A method of forming shallow junctions in a CMOS transistor is disclosed. The method comprises the steps of: (a) forming a diffusion source layer on a N-well region, a P-well region, field oxide layer, and the gates of a CMOS transistor; (b) forming a photoresist layer over the P-well region; (c) carrying out p-type ion implantation to dope a part of the diffusion source layer on the P-well region; (d) removing the photoresist layer on the P-well region; (e) forming a photoresist layer over the N-well region; (f) carrying out n-type ion implantation to dope the other part of the diffusion source layer on the N-well region; (g) removing the photoresist layer on the N-well region; and (h) oxidizing the diffusion source layer and driving the ions therein into the P-well and N-well regions to form shallow junctions, respectively. The present invention has several advantages. First, it is compatible with the conventional CMOS process.

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer of glass (2% BSG) is used to provide the source of doping for the tip region and a second layer of glass (6% BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract: Methods of forming power semiconductor devices include the steps of forming an insulated gate electrode on a face of semiconductor substrate containing a body region of first conductivity type (e.g., P-type) therein extending to the face. Using the gate electrode as a mask, a step is then performed to oxidize the body region and substrate at the face to form a first oxide layer. Source and drain region dopants are then implanted through the first oxide layer and into the body region and substrate to define recessed source and drain regions of second conductivity type therein, respectively. The step of implanting source and drain region dopants may be preceded by the step of etching the first oxide layer using an etching mask which covers the gate electrode. The step of oxidizing the body region and substrate may also be preceded by the step of forming nitride spacers on sidewalls of the gate electrode and then also using the nitride spacers as a mask during the oxidation step.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, a portion of the first silicon layer, and a portion of the anti-reflection layer. A shield layer is then formed over the semiconductor substrate, on the gate insulator layer, and on the first silicon layer. A spacer structure containing first conductivity type dopants is then formed on the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second conductivity type dopants is formed over the semiconductor substrate and the first silicon layer. Finally, a thermal process is performed to the semiconductor substrate for diffusing the first conductivity type dopants and the second conductivity type dopants into the semiconductor substrate.

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

Abstract: A method of forming a LDD fabrication by automatic phosphoric silicate glass (PSG) doping is disclosed herein. A phosphoric silicate glass serves as a diffusion source. The phosphorous ions of phosphoric silicate glass can be driven into a substrate to form a lightly-doped drain (LDD)by a high temperature during a thermal annealing process. The diffusion method can prevent from the damage in the substrate and the increasing of leakage current. Additionally, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from sequentially diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can effectively control the impurity concentration of the lightly-doped drain (LDD) to prevent from the impurity concentration of the LDD over high.

Abstract: The method of the present invention includes forming a silicon dioxide layer. A polysilicon layer is then deposited on the silicon dioxide layer. Next, a gate structure is formed by etching. A silicon oxynitride layer is formed on the substrate and covers the gate structure. Silicon nitride side-wall spacers are formed on the side walls of the gate. An amorphous silicon layer is formed on the substrate, the side-wall spacers, and top of the polysilicon gate. Then, the source and the drain are formed. A wet oxidation is subsequently carried out to convert the amorphous silicon into a doped oxide layer. An etching process is then utilized to etch the oxide layer. Therefore, oxide side-wall spacers are formed on the silicon nitride side-wall spacers. Then, a metal silicide layer is formed on top of the gate, and on the source and the drain. The silicon nitride side-wall spacers are removed to form air gaps between the gate and the side-wall spacers.

Abstract: A method of making a shallow trench isolation region includes providing a silicon substrate. A pad oxide layer is formed over the silicon substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer and the pad oxide layer are patterned, and a trench is thus formed in the silicon substrate. A side-wall oxide layer is formed on a surface of the silicon substrate within the trench. A doped oxide layer is formed over the silicon nitride layer and within the trench. A portion of the doped oxide layer is removed to expose the silicon nitride layer. The silicon nitride layer is removed. The pad oxide layer is removed. A sacrificial oxide layer is formed over the silicon substrate. A well is formed in the silicon substrate. The sacrificial oxide layer is removed. A gate oxide layer is formed over the silicon substrate. A polysilicon layer is formed over the silicon substrate. The polysilicon layer is patterned to form a polysilicon gate.

Abstract: The method includes forming a gate oxide on a substrate. A stacked-amorphous-silicon (SAS) layer is then formed on the gate oxide. An anti-reflective coating (ARC) layer is formed on the SAS layer. Next, a gate structure is patterned by etching. A silicon oxynitride layer is formed on the substrate, and covered the gate structure. A BSG sidewall spacers are formed on the side walls of the gate structure. A selective epitaxial silicon is grown on the substrate by using ultra high vacuum chemical vapor deposition. Then, an ARC layer is removed to expose the top of the SAS layer. Then, a blanket ion implantation is carried out to implant p type dopant into the SAS layer, the epitaxial silicon and silicon substrate. A SALICIDE layer, a polycide layer are respectively formed on the SAS layer and the epitaxial silicon. Further, the extended source and drain are formed in the step. A thick oxide layer is formed over the substrate and gate structure for isolation. Then, contact holes are generated in the oxide layer.

Abstract: A method for forming N- and P-channel transistors having shallow junctions in an integrated circuit device is described. A semiconductor substrate is provided having active regions separated from one another by isolation regions wherein there is a N-channel active region and a P-channel active region and wherein gate electrodes and associated lightly doped source and drain regions have been formed in each of the active regions. A layer of borosilicate glass is deposited overlying the semiconductor substrate. A photoresist mask is formed over the P-channel active region. The borosilicate glass layer is etched away where it is not covered by the photoresist mask thereby leaving the borosilicate glass layer only overlying the P-channel region. The photoresist mask is removed. A layer of phosphosilicate glass is deposited overlying the semiconductor substrate.

Abstract: A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique.

Abstract: A method of manufacturing a field effect transistor according to the present invention is disclosed including the steps of preparing a semiconductor substrate; forming an insulating film for use as high concentration on the semiconductor substrate; forming an insulating film for use as low concentration on the insulating film for use as high concentration; performing a heat treatment on the insulating films to thereby diffuse impurities; forming high concentration regions and low concentration region in the surface of the semiconductor substrate; forming mesa and electrodes on the upper surface and side of the semiconductor substrate; and selectively etching the insulating film for use as low concentration so as to expose a predetermined portion of the upper surface of the semiconductor substrate, to thereby form a gate electrode so as to be in contact with the low concentration region of the predetermined portion.

Abstract: A process for doping a region in a substrate from a solid phase source. An inert gas is bubbled through a dopant containing ester and supplied to a chamber along with the gases used to form a silicon dioxide layer such as a TEOS formed layer. The flow of the inert gas can be modulated to grade the dopant concentration in the silicon dioxide layer. The dopant is diffused from the silicon dioxide layer into the substrate to form, for instance, source and drain regions in field-effect transistors.

Abstract: A new method for forming shallow trench isolation is disclosed herein. A pad oxide layer and a silicon nitride layer are formed on a wafer, respectively. A plurality of trenches are created in the wafer. Then, a SAC layer is formed on an N-well. A BSG layer is formed on a P-well and the N-well. A thermal process is used to form a channel stop in the P-well. Then, the BSG layer and the SAC layer are removed. Subsequently, a LPD oxide layer is deposited in the trenches. Then, a CMP process is used to polish the LPD oxide layer for planarization. The pad oxide layer and the silicon nitride layer are removed. Next, a gate oxide layer is formed on the wafer.

Abstract: A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current driving capability of an NMOS device. The semiconductor device has halo impurity regions formed in either the NMOS region or the PMOS region such that a channel length of the PMOS device. Also, the source channel length of the PMOS device. Also, the source and drain regions of the PMOS device are prevented from forming deep source and drain regions, thus, preventing deterioration of the short channel properties for the PMOS device.

Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.

Abstract: A fabrication method for a semiconductor memory device with a non-uniformly doped channel(hereinafter, called NUDC) formed in a semiconductor substrate with a thin central portion that becomes gradually thicker toward the edges of the substrate. The method includes forming an impurity-bearing layer on a semiconductor substrate, selectively etching the impurity containing layer in a manner such that the portion of the impurity-bearing layer serving as a gate region is formed to be thin at a central portion thereof and gradually thickens as it nears the edges thereof; forming a first conductive impurity region by driving the impurity from the impurity containing layer into the semiconductor substrate, stripping the impurity containing layer, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive impurity region in the semiconductor substrate at the sides of the gate electrode.

Abstract: A thin film transistor is fabricated by introducing a dopant into an indium tin oxide layer or a gate insulating layer by an ion shower doping technique. An a-Si semiconductor layer is then deposited on the surface of the substrate and subjected to a single exposure of laser light. The laser exposure or annealing diffuses dopant into the semiconductor layer and activates the dopant to form an ohmic layer of n-type or p-type conductivity polysilicon, and an intrinsic polysilicon layer. A metal layer and an indium tin oxide layer are formed to the side of a gate electrode to maintain an electrical connection even if a break is formed in the data bus line.

Abstract: A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.

Abstract: Portions of a semiconductor device (10,30) are formed from a dielectric layer (16,38,46) which is deposited using a plasma enhanced chemical vapor deposition (PECVD) process which adds trimethylphosphite as a dopant source during the deposition. A first embodiment forms sidewall spacers (17) adjacent to a gate structure (14) and forms doped regions (19) under the sidewall spacers (17) by annealing the dielectric layer (16) and driving phosphorus into a substrate (11). A second embodiment uses the trimethylphosphite doped film as an interlevel dielectric layer (38) which can be planarized to provide a flat surface for the formation of metal interconnect lines. A third embodiment of the present invention uses the trimethylphosphite doped film as a passivation layer (46) which is deposited in a single step process and has a phosphorus concentration to getter mobile ions.

Abstract: A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.

Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.

Abstract: A method (10,30) of boron doping a semiconductor particle using boric acid to obtain a p-type doped particle. Either silicon spheres or silicon powder is mixed with a diluted solution of boric acid having a predetermined concentration. The spheres are dried (16), with the boron film then being driven (18) into the sphere. A melt procedure mixes the driven boron uniformly throughout the sphere. In the case of silicon powder, the powder is metered out (38) into piles and melted/fused (40) with an optical furnace. Both processes obtain a p-type doped silicon sphere with desired resistivity. Boric acid is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirements.

Abstract: A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.

Abstract: A method of making a semiconductor body includes the steps of preparing a sheet-like substrate having an insulating film and holes which pass through the insulating film, the holes being disposed at a uniform density, preparing a solution in which a semiconductor material is dissolved, and conveying the sheet-like substrate along a surface of the solution so as to grow a single crystal nucleus from each of the holes and thereby form a set of single crystal semiconductors on the sheet-like substrate. A solar cell can be manufactured by forming a semiconductor active area on the sheet-like support member made of a conductive material by a process containing the above-described semiconductor body forming method, and then by forming an electrode which makes a pair with the sheet-like support member.

Abstract: The present invention relates to a solid high temperature phosphorus diffusion source that is an R.sub.2 O.sub.3 /P.sub.2 O.sub.5 compound in which the ratio of R.sub.2 O.sub.3 to P.sub.2 O.sub.5 is 1 to 3 and R is La, Y, Ce, Nd, Eu, Pr, Sm, Ho, Tb, Er, Yb, Tm or Dy. The invention also relates to a method of making the diffusion source, a method of using the diffusion source to evolve P.sub.2 O.sub.5 to dope a silicon wafer, and to the doped silicon wafer.