From Vapor Phase Patents (Class 438/565)
  • Patent number: 6048782
    Abstract: Halides of a dopant species may be used as a dopant gas source to form shallow doped junctions using a direct gas-phase doping (GPD) process. These halides can also be combined with a carrier gas. Some advantages over conventional gas-phase doping processes include shallower junctions, shorter process times, lower processing temperature, and the elimination of a separate surface cleaning step for native oxide removal.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: April 11, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Mehrdad M. Moslehi
  • Patent number: 6040236
    Abstract: In a silicon conductor doped with an impurity of 100 nm or less thick, a method is provided for manufacturing a silicon thin film conductive element which can prevent the increase of resistance with a low impurity concentration. The method includes the step in which, after the formation of an impurity-containing amorphous silicon film, a crystallization is performed without removing the film from a film forming device by performing a heat treatment while flowing a gas containing the impurity.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: March 21, 2000
    Assignee: NEC Corporation
    Inventor: Fumiki Aiso
  • Patent number: 6040019
    Abstract: A method of forming a region of impurity in a semiconductor substrate with minimal damage. The method includes the steps of: forming a reaction-inhibiting impurity region in the semiconductor substrate to a depth below the semiconductor substrate; and applying laser energy to the semiconductor substrate at a sufficient magnitude to liquify the semiconductor substrate in the region.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: March 21, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Emi Ishida, Xiao-Yu Li, Sunil D. Mehta
  • Patent number: 6025208
    Abstract: A method of forming electrical elements on the sidewalls of deformable micromechanical structures such as flexible, high aspect ratio beams. The micromechanical structure is made of a semiconductor material such as silicon. The method includes angled ion implantation at an angle nonnormal to the substrate surface. The angle ensures that ions are implanted into appropriately oriented sidewalls. Multiple ion implantations can be performed to form electrical elements into different sidewalls. Masking techniques can be used to restrict the locations where ions are implanted. Alternatively, several different types of ion diffusion can be used to expose the sidewall in selected regions. The present invention can form conductive pathways which are continuous between perpendicular surfaces. This enables electrical elements on vertical surfaces to communicate with electronics on horizontal surfaces, for example. The dopant ion concentration and ion species can be controlled to form many different electrical elements.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: February 15, 2000
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Benjamin W. Chui, Thomas W. Kenny
  • Patent number: 5946587
    Abstract: The present invention aims to provide a continuous forming method and apparatus for functional deposited films having excellent characteristics while preventing any mutual mixture of gases between film forming chambers having different pressures, wherein each of semiconductor layers of desired conduction type is deposited on a strip-like substrate within a plurality of film forming chambers, by plasma CVD, while the strip-like substrate is being moved continuously in a longitudinal direction thereof through the plurality of film forming chambers connected via a gas gate having the structure of introducing a scavenging gas into a slit-like separation passage, characterized in that at least one of the gas gates connecting the i-type layer film forming chamber for forming the semiconductor junction and the n- or p-type layer film forming chamber having higher pressure than the i-type layer film forming chamber has the scavenging gas introducing position disposed on the n- or p-type layer film forming chamber sid
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: August 31, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Takehito Yoshino, Akira Sakai, Tadashi Hori
  • Patent number: 5882991
    Abstract: A method for forming shallow junctions using rapid thermal gas-phase doping (RTGPD). A wafer (26) is placed in a process chamber (14). After evacuating the chamber, a dopant gas combined with a carrier gas is introduced to the chamber (14) while the pressure is increased from a base pressure to on the order of 200-3000 Torr. The gas flow is shut off when the desired elevated pressure is reached. A rapid thermal cycle is then performed using a static gas flow and elevated pressures to create a shallow junction (40).
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: March 16, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Ajit Pramond Paranjpe
  • Patent number: 5874352
    Abstract: A method of producing an MIS transistor by preparing a substrate formed with a gate electrode and a semiconductor layer which defines a source region and a drain region, removing a natural oxide film from a surface of the gate electrode and from a surface of the semiconductor layer to expose an active surface, delivering a source gas containing an impurity component to the exposed active surface to deposit thereon an impurity adsorption film, and annealing the substrate to diffuse the impurity component from the impurity adsorption film into the gate electrode and concurrently into the semiconductor layer to form the source and drain regions. The gate electrode has the same conductivity type as the source and drain regions.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: February 23, 1999
    Assignee: Sieko Instruments Inc.
    Inventors: Tadao Akamine, Kenji Aoki
  • Patent number: 5792701
    Abstract: An apparatus for producing thin film coatings and/or dopant levels on semiconductor wafers or other substrates with improved film growth uniformity (of thickness and composition) and/or dopant uniformity is provided. The apparatus is positioned in a furnace tube between the wafers and a gas inlet. The apparatus comprises a conical shaped baffle.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: August 11, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Lang Wang, Yu-Jen Yu
  • Patent number: 5759905
    Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: June 2, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Sujit Sharan, Kirk Prall
  • Patent number: 5733815
    Abstract: A method of simultaneously forming a gallium arsenide p-i-n structure having p, i, and n regions, which includes heating to dissolve gallium arsenide in a solvent such as bismuth or gallium to form a saturated solution of gallium arsenide in the solvent, contacting the solution with a gaseous mixture, which mixture includes hydrogen, water vapor and products of reactions between the hydrogen and the water vapor with the solvent and with silicon dioxide, to form a contacted solution, coating a suitably selected substrate, such as a group III-V compound such as gallium arsenide, with the contacted solution, cooling the coated substrate to precipitate gallium arsenide from the contacted solution onto the substrate, and removing the substrate coated with a layer of gallium arsenide having a p-i-n structure which constitutes the product having an i region dopant concentration of less than about 10.sup.12 cm.sup.-3.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: March 31, 1998
    Assignee: Ramot University Authority for Applied Research & Industrial Development Ltd.
    Inventors: German Ashkinazi, Mark Leibovich, Boris Meyler, Menachem Nathan, Leonid Zolotarevski, Olga Zolotarevski
  • Patent number: 5721175
    Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type, forming a transition metal compound layer containing a constituent element of the semiconductor substrate on the impurity diffusion layer, and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: February 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Kunishima, Kyoichi Suguro
  • Patent number: 5641707
    Abstract: A direct doping method for semiconductor wafers, comprising the steps of providing a semiconductor wafer, exposing the surface of the wafer to a process medium in order to directly dope at least a portion of the surface of the wafer, wherein the process medium comprises a dopant gas, and wherein the dopant gas comprises an organic compound of a dopant species, and heating the wafer, thermally activating the direct doping process and causing solid-state diffusion of the dopant species into the semiconductor wafer surface. The organic source of a dopant species includes the organic compounds comprising boron, arsenic and phosphorous. The wafer is heated in the presence of an organic dopant source, thermally activating the doping process and causing surface chemisorption, surface dissociation, and solid-state diffusion of the dopant species into the wafer surface. The organic dopant source can be used with a germanium-containing additive gas, a halogen-containing compound or a remote plasma energy source.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 24, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Mehrdad M. Moslehi