Abstract: A method for forming an ohmic contact and a Schottky diode in an integrated circuit includes providing a semiconductor substrate; forming first and second diffusion regions in the semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a first contact opening in the insulating layer and over the first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer and the insulating layer to expose the semiconductor substrate where the second contact opening is formed over the second diffusion region; forming a metal layer on the barrier metal layer and the insulating layer and in the first and second contact openings where the metal layer includes a metal that forms a Schottky barrier junction with the semiconductor substrate; and patterning the metal layer to form the ohmic contact over the first diffusion region and the Schottky dio

Abstract: In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective insulating film spreads in an umbrella shape from above the T-shaped gate electrode. A hollow region is formed between the two SiN films. The SiN films are coated with a SiN third protective insulating film with the hollow region remaining.

Abstract: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.

Abstract: A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

Abstract: A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short.

Abstract: a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrodes are adapted to be biased differently from one another. The semiconductor region is overlaid with a metal layer to thereby form a Schottky barrier therebetween.

Abstract: In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion and forms a second Schottky barrier that has an opposite polarity to the first Schottky barrier. The conductive contact layer does not overlap the first portion, which forms a pn junction with the region of semiconductor material.

Abstract: A method for fabricating a field effect transistor includes: forming an insulating film provided on a semiconductor layer, the insulating film having an opening via which a surface of the semiconductor layer is exposed and including silicon oxide; forming a Schottky electrode on the insulating film and in the opening, the Schottky electrode having an overhang portion and having a first contact layer that is provided in a region contacting the insulating film and contains oxygen, and a second contact layer that is provided on the first contact layer and contains a smaller content of oxygen than that of the first contact layer; and removing the insulating film by a solution including hydrofluoric acid.

Abstract: A semiconductor component is proposed which has a semiconductor body having a first semiconductor zone of the first conduction type, at least one first rectifying junction with respect to the first semiconductor zone, at least one second rectifying junction with respect to the first semiconductor zone, wherein the three rectifying junctions each have a barrier height of different magnitude.

Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.

Abstract: A power diode having a silicon mesa atop the drift region includes a first contact positioned on the silicon mesa. The silicon mesa is highly doped p-type or n-type, and the anode may be formed on the mesa. The mesa may include two separate silicon layers, one of which is a Schottky barrier height layer. Under a forward bias, the silicon mesa provides carriers to achieve desirable forward current characteristics. The substrate has a significantly reduced thickness. The diode achieves reverse voltage blocking capability by implanting junction barrier Schottky wells within the body of the diode. The diode utilizes a deeper portion of the drift region to support the reverse bias. The method of forming the diode with a silicon mesa includes forming the mesa within a window on the diode or by thermally or mechanically bonding the silicon layer to the drift region.

Abstract: An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.

Abstract: A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to a surface of the semiconductor substrate, the directional sputtering being one of collimate sputtering, long throw sputtering and ion beam sputtering; removing the surface film formed along a sidewall of the dummy gate; removing the dummy gate; and forming the gate electrode in the region from which the dummy gate on the semiconductor substrate has been removed.

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and (d) a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material; and (e) a gate stack in direct physical contact with the semiconductor channel region.

Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

Abstract: In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of ?-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of ?-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.

Abstract: A semiconductor device (20) comprising a trench MOS barrier Schottky diode having an integrated PN diode and a method for manufacturing same are described.

Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n? silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

Abstract: The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench structures (105) are formed perpendicular to the surface of the driving unit (100). Deposition of a seed layer (106) on side walls (105a) of the trench structures (105) allows a crystallization agent (107) which has filled the trench structures (105), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

Abstract: Pt/n?GaN Schottky barrier diodes are disclosed that are particularly suited to serve as ultra-violet sensors operating at wavelengths below 200 nm. The Pt/n?GaN Schottky barrier diodes have very large active areas, up to 1 cm2, which exhibit extremely low leakage current at low reverse biases. Very large area Pt/n?GaN Schottky diodes of sizes 0.25 cm2 and 1 cm2 have been fabricated from n?/n+ GaN epitaxial layers grown by vapor phase epitaxy on single crystal c-plane sapphire, which showed leakage currents of 14 pA and 2.7 nA, respectively for the 0.25 cm2 and 1 cm2 diodes both configured at a 0.5V reverse bias.

Abstract: A semiconductor device has a Group III nitride semiconductor layer and a gate electrode formed on the Group III nitride semiconductor layer. The gate electrode contains an adhesion enhancing element. A thermally oxidized insulating film is interposed between the Group III nitride semiconductor layer and the gate electrode.

Abstract: A method of forming a power Schottky rectifier device is disclosed. The Schottky rectifier device including LOCOS structure and two p doped layers formed thereunder to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n? drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n? drift layer; a pair of field oxide regions and termination field oxide region formed into the n? drift layer and each spaced from each other by the mesas. A stack of metal layers formed of Ti/Ni/Ag are formed atop the front surface. A RTP (rapid thermal process) is then followed to form a Schottky barrier diode. Alternatively, the stack metal layers are formed of Ti/TiN/Al. Yet, the Al is formed after RTP. Subsequently, the top metal layer is patterned to form an anode electrode.

Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.

Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.

Abstract: A method for forming an ohmic contact and a Schottky diode in an integrated circuit includes providing a semiconductor substrate; forming first and second diffusion regions in the semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a first contact opening in the insulating layer and over the first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer and the insulating layer to expose the semiconductor substrate where the second contact opening is formed over the second diffusion region; forming a metal layer on the barrier metal layer and the insulating layer and in the first and second contact openings where the metal layer includes a metal that forms a Schottky barrier junction with the semiconductor substrate; and patterning the metal layer to form the ohmic contact over the first diffusion region and the Schottky dio

Abstract: A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a channel region. The improvements from the controllability of the placement of the Schottky-barrier junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.

Abstract: Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solid state chemical sensors. Detention of the following chemical species was established: hydrogen, deuterium, carbon monoxide, and molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells. Each of the PCM cells includes diode arranged adjacent to a metallization layer; a heater element arranged adjacent to the diode, and a phase-change material arranged adjacent to the heater element.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method includes the steps of: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer, The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: A mirror-like key (40) comprises a base portion (46), a sputtered layer (44) and a lightproof printed layer (42) with a light-pervious label (422). The base portion comprises an upper surface (462) and a lower surface (464) opposite to the upper surface. The sputtered layer is formed on one of the upper surface and the lower surface of the base portion. The printed layer is formed below the sputtered layer.

Abstract: A silicon carbide-based device contact and contact fabrication method employ a layer of poly-silicon on a SiC substrate, with the contact's metal layer deposited on top of the poly-silicon. Both Schottky and ohmic contacts can be formed. The poly-silicon layer can be continuous or patterned, and can be undoped or doped to be n-type or p-type. The present contact and method provide excellent contact adhesion, and can be employed with a number of different device types, to provide electrical contacts for Schottky diodes, pn diodes, and transistors, for example.

Abstract: A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second doped region is disposed between the first doped region and the first conductive layer. The plurality of third doped regions are disposed in the second doped region. The first doped region of the semiconductor is heavily doped with a first type of dopant (e.g., phosphorous or arsenic). The second doped region is moderately doped with the first type of dopant. The plurality of third doped regions are moderately to heavily doped with a second type of dopant.

Abstract: There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: A manufacturing method for forming a region into which impurity ions are implanted, and an electrode is coupled to the region, in a self-aligned manner. An oxide film is formed on an n-type semiconductor layer composed of a silicon carbide semiconductor, and then the oxide film on regions in which source and drain regions are to be formed is removed by etching. Impurity ions are implanted into an exposed semiconductor layer and heat treatment is performed for activating the implanted impurity ions. A metal film to serve as ohmic electrodes is formed on the entire surface, and then the oxide film is removed by etching to thereby form a source electrode and a drain electrode. Leaving a part of the oxide film on regions on which source and drain electrodes are to be formed can prevent the oxide film from being deformed during the heat treatment for activation.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.

Abstract: A problem in related art according to which an increase in leak current cannot be avoided in order to obtain a low forward voltage VF as forward voltage VF and reverse leak current IR characteristics of a Schottky barrier diode are in a trade-off relationship is hereby solved by forming a Schottky barrier diode using a metal layer comprising a Schottky metal layer of Ti including a small amount of Al. Consequently, a low reverse leak current IR can be obtained without causing a large increase in the forward voltage VF of pure Ti such that power consumption can be reduced by suppressing forward power loss and decreasing reverse power loss.

Abstract: A field-effect transistor includes: a carrier supply layer supplying carriers; a Schottky contact layer forming a Schottky barrier; and an intermediate layer formed between the carrier supply layer and the Schottky contact layer. Here, the intermediate layer has an electron affinity which is higher than an electron affinity of the carrier supply layer but lower than an electron affinity of the Schottky contact layer.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 ?-?m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: A filter having a thin-film resonator fabricated on a semiconductor substrate and a method of making the same are disclosed. The filter has a bonding pad connected to the resonator and in contact with the substrate to form a Schottky diode with the substrate to protect the resonator from electrostatic discharges.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: A light-receiving device, a method for manufacturing the same, and an optoelectronic integrated circuit including the same are provided. The light-receiving device includes a substrate; an intrinsic region formed on the substrate; a first region formed to a shallow depth in the intrinsic region; and a second region formed to a deep depth in the intrinsic region and distanced from the first region, wherein the first and second regions are doped with different conductivity types. The light-receiving device can shorten the transit time of holes with slow mobility. Therefore, no response delay occurs, and thus, a high response speed can be accomplished.

Abstract: A schottky barrier transistor and a method of manufacturing the same are provided. The method includes forming a gate insulating layer and a gate on a substrate, forming a spacer on a sidewall of the gate, and growing a polycrystalline silicon layer and a monocrystalline silicon layer on the gate and the substrate, respectively, using a selective silicon growth. A metal is deposited on the polycrystalline silicon layer and the monocrystalline silicon layer. Then, the metal reacts with silicon of the polycrystalline silicon layer and the monocyrstalline silicon layer to form a self-aligned metal silicide layer. Therefore, selective wet etching for removing an unreacted metal after silicidation can be omitted. Furthermore, etching damage caused during the formation of the spacer can be decreased during the growth of the monocrystalline silicon layer, thereby improving the electrical characteristics of devices.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.