Silicide Patents (Class 438/581)
  • Patent number: 7902055
    Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Texas Instruments Incoprorated
    Inventors: Richard B. Irwin, Tony T. Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer S. Dumin, Patrick J. Jones, Fredric D. Bailey
  • Publication number: 20100258899
    Abstract: A Schottky diode device includes a silicon substrate, an epitaxial silicon layer on the silicon substrate, an annular trench in a scribe line region that encompasses the epitaxial silicon layer, an insulation layer on interior sidewall of the annular trench, a silicide layer on the epitaxial silicon layer, a conductive layer on the silicide layer, and a guard ring in the epitaxial silicon layer, wherein the guard ring butts the insulation layer.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Inventors: Chih-Tsung Huang, Jhih-Siang Huang
  • Patent number: 7803702
    Abstract: A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
  • Patent number: 7795100
    Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: September 14, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hedeyuki Kojima, Toru Anezaki
  • Patent number: 7786537
    Abstract: A semiconductor device includes a silicon substrate; a P channel type field effect transistor including a first gate insulating film on the substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and an N channel type field effect transistor including a second gate insulating film on the substrate, a second gate electrode on the second gate insulating film and a second source/drain region. The entire first gate electrode is made of a metal silicide, and at least in an upper portion including the upper surface of the second gate electrode, a silicide region of the same kind as the metal (M) is provided. The metal concentration in the silicide region is lower than that in the silicide of the first gate electrode. In an upper portion including the upper surface of the second gate electrode, there is a barrier layer region containing a metal diffusion suppressing element at a concentration higher than that in the lower portion.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: August 31, 2010
    Assignee: NEC Corporation
    Inventor: Kenzo Manabe
  • Patent number: 7759202
    Abstract: A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: July 20, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Che-Hua Hsu, Yao-Tsung Huang, Guang-Hwa Ma
  • Patent number: 7749877
    Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and an ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form and SiO2 passivation layer to improve the self aligned process.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Siliconix Technology C. V.
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 7732312
    Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: June 8, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
  • Patent number: 7732313
    Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: June 8, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
  • Patent number: 7662707
    Abstract: Methods of forming metal silicide layers in a semiconductor device are provided in which a first metal silicide layer may be formed on a substrate, where the first metal silicide layer comprises a plurality of fragments of a metal silicide that are separated by one or more gaps. A conductive material is selectively deposited into at least some of the gaps in the first metal silicide layer in order to electrically connect at least some of the plurality of fragments.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sug-Woo Jung, Gil-Heyun Choi, Jong-Ho Yun, Hyun-Su Kim, Eun-Ji Jung
  • Patent number: 7662716
    Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Su Kim, Kwang-Jin Moon, Sang-Woo Lee, Eun-Ok Lee, Ho-Ki Lee
  • Patent number: 7618884
    Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: November 17, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: William F. Seng, Richard L. Woodin, Carl Anthony Witt
  • Patent number: 7605076
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 7595234
    Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: September 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
  • Patent number: 7585767
    Abstract: A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto
  • Patent number: 7566642
    Abstract: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: July 28, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yark Yeon Kim, Moon Gyu Jang, Jae Heon Shin, Seong Jae Lee
  • Patent number: 7553729
    Abstract: A method of manufacturing a non-volatile memory device includes the steps of forming gates respectively having a structure in which a gate insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a metal-silicide layer are laminated over a semiconductor substrate, annealing the metal-silicide layer at a temperature, which is the same as or lower than an annealing temperature of the dielectric layer, forming a buffer oxide layer on the entire surface, and forming a nitride layer on the buffer oxide layer.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 30, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Yeol Choi
  • Patent number: 7550372
    Abstract: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Su-Yuan Chang, Min-San Huang, Hann-Jye Hsu
  • Patent number: 7504328
    Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: March 17, 2009
    Assignee: National University of Singapore
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chunxiang Zhu, Dim-Lee Kwong
  • Patent number: 7501333
    Abstract: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: March 10, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Jung Lin, Cheng-Tung Lin, Chih-Wei Chang, Shau-Lin Shue
  • Patent number: 7485513
    Abstract: One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and the second diffusion region. The memory cell includes a gate insulator stack formed above the channel region, and a gate to connect to a word line. The gate insulator stack includes a floating plate to selectively hold a charge. The floating plate is connected to the second diffusion region. The memory cell includes a diode that connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. Other aspects are provided herein.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: February 3, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7459382
    Abstract: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Wesley C. Natzle, Siddhartha Panda, Brian L. Tessier
  • Patent number: 7459756
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: December 2, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
  • Patent number: 7432181
    Abstract: A method of forming self-aligned silicides is described and applied to a substrate having an isolation area, which divides the substrate into a first area and a second area. A resist protective oxide layer is formed on the substrate, and subsequently a mask layer is formed on the resist protective oxide layer. Further, the mask layer includes an opening on the first area and another opening on a contact hole of the second area. When a resist protective oxide process is performed, the mask layer protects the resist protective oxide layer underlying the same from being removed, whereas the resist protective oxide layer under the openings are removed. Therefore, silicides are controlled to form on the first area and the contact hole of the second area in a subsequent self-aligned silicidation process.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: October 7, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yei-Hsiung Lin, Steven Huang
  • Patent number: 7432180
    Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 7, 2008
    Assignee: Fujitsu Limited
    Inventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
  • Patent number: 7429525
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: September 30, 2008
    Assignee: Fujitsu Limited
    Inventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
  • Patent number: 7425482
    Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures; forming a second electrode layer over the first insulation layer; and forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: September 16, 2008
    Assignee: Magna-Chip Semiconductor, Ltd.
    Inventor: Yong-Sik Jeong
  • Patent number: 7396764
    Abstract: The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Shigeki Komori
  • Patent number: 7368371
    Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n? silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 6, 2008
    Assignee: Chip Integration Tech. Co., Ltd.
    Inventor: Shye-Lin Wu
  • Patent number: 7348265
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: March 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Jiong-Ping Lu
  • Patent number: 7306983
    Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a protective layer to a device, applying a first silicon nitride liner to the device, removing a portion of the first silicon nitride liner, removing a portion of the protective layer, and applying a second silicon nitride liner to the device.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: December 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha
  • Publication number: 20070269970
    Abstract: The present invention provides a semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x<y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 22, 2007
    Applicant: International Business Machines Corporation
    Inventors: Robert J. Purtell, Henry K. Utomo, Yun-Yu Wang, Haining S. Yang
  • Patent number: 7297618
    Abstract: The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are compatible with workfunctions that are different from conventional n+ and p+ doped poly silicon electrodes. Each device region consists of at least one Field Effect Transistor (FET) device which consists of either a polysilicon gate electrode or a fully silicided (FUSI) gate electrode. A gate electrode comprised of silicon and a Ge containing layer is used in combination with a selective removal process of the Ge containing layer. The Ge containing layer is not removed on devices with threshold voltages that are not compatible with the FUSI workfunction. Devices that are compatible with the FUSI workfunction have the Ge containing layer removed prior to the junction silicidation step.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: November 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: William K. Henson, Kern Rim
  • Patent number: 7285491
    Abstract: A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal process is performed at 450˜550 degrees centigrade for 10˜60 seconds.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: October 23, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Min-Hsian Chen, Ching-Hsing Hsieh
  • Publication number: 20070212862
    Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and a ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form an SiO2 passivation layer to improve the self aligned process.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 13, 2007
    Inventors: Rossano Carta, Carmelo Sanfilippo
  • Patent number: 7247549
    Abstract: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back the oxide film to expose the nitride film; etching the exposed nitride film, exposing the gate polysilicon, and forming a space; forming undoped polysilicon burying the space; etching back the undoped polysilicon to form a wide portion in the upper portion of the gate polysilicon; and etching the oxide film and the nitride film; siliciding the wide undoped silicon to form titanium silicide (or cobalt silicide). This manufacturing method makes it possible to easily form the T type gate electrode with good yield.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: July 24, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: So Suzuki
  • Patent number: 7235471
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating layer over the semiconductor substrate, forming a conductive layer over the insulating layer, forming a first metal silicide layer over the conductive layer, patterning the conductive layer to form a patterned first layer, wherein the patterned first layer is a part of a control electrode, patterning the first metal silicide layer to form a patterned first metal silicide layer over the control electrode so that the patterned first metal silicide layer remains over the control electrode, and forming a second metal silicide over the patterned metal silicide layer, wherein the second metal silicide layer has a thickness greater than the thickness of first metal silicide layer.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: June 26, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dharmesh Jawarani, Tab A. Stephens
  • Patent number: 7208398
    Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130) to form a halogen-containing metal layer (140) on a semiconductor substrate (150). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400) comprising the metal silicide electrode.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Douglas E. Mercer, Noel Russell
  • Patent number: 7199032
    Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: April 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Duofeng Yue, Peijun J. Chen, Sue Ellen Crank, Thomas D. Bonifield, Jiong-Ping Lu, Jie-Jie Xu
  • Patent number: 7172955
    Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0?y<1.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: February 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Matsuo, Kazuaki Nakajima
  • Patent number: 7172933
    Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
  • Patent number: 7169678
    Abstract: Semiconductor devices and methods for fabricating a silicide of a semiconductor device are disclosed. An illustrated method comprises: forming a gate electrode; depositing an insulating layer; removing a predetermined portion of the insulating layer in order to expose a portion of the gate electrode; forming silicide on the exposed portion of the gate electrode; and etching the insulating layer while using the silicide as an etching mask.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 30, 2007
    Assignee: Dongbu Electronics, Co., Ltd.
    Inventor: Seok Su Kim
  • Patent number: 7141498
    Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: November 28, 2006
    Assignees: Denso Corporation, The University of Newcastle upon Tyne
    Inventors: Rajesh Kumar Malhan, Yuichi Takeuchi, Irina Nikitina, Konstantin Vassilevski, Nicholas Wright, Alton Horsfall
  • Patent number: 7135369
    Abstract: An atomic layer deposited ZrAlxOy dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a zirconium-containing precursor onto a substrate, pulsing a first oxygen-containing precursor, pulsing an aluminum-containing precursor, and pulsing a second oxygen-containing precursor to form ZrAlxOy by atomic layer deposition provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide and with a relatively low leakage current. Dielectric layers containing atomic layer deposited ZrAlxOy are thermodynamically stable such that the ZrAlxOy will have minimal reactions with a silicon substrate or other structures during processing.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 14, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7132352
    Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: November 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Simon Siu-Sing Chan, Paul R. Besser, Jeffrey P. Patton
  • Patent number: 7067391
    Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: June 27, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Wen Chan, Chih-Hao Wang, Lawrance Hsu, Hun-Jan Tao
  • Patent number: 7052945
    Abstract: A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: May 30, 2006
    Assignee: Spinnaker Semiconductor, Inc.
    Inventor: John P. Snyder
  • Patent number: 7052946
    Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: May 30, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chien-Hao Chen, Chia-Lin Chen, Ju-Wang Hsu, Tze-Liang Lee, Shih-Chang Chen
  • Patent number: 7037371
    Abstract: After distributing a nonmetal element in a region in the vicinity of a surface portion of a semiconductor layer, a metal film is deposited on the semiconductor layer. Next, a semiconductor-metal compound layer is epitaxially grown in the surface portion of the semiconductor layer by causing a reaction between an element included in the semiconductor layer and a metal included in the metal film through annealing carried out on the metal film.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: May 2, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shin Hashimoto, Takenobu Kishida, Kyoko Egashira, Yoshifumi Hata, Toru Nishiwaki, Tomoya Tanaka
  • Patent number: 7029972
    Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tony Thanh Phan, Farris D. Malone