Forming Array Of Gate Electrodes Patents (Class 438/587)
  • Patent number: 8846517
    Abstract: A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVilliers
  • Patent number: 8846515
    Abstract: Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Micaela Gabriella Tomasini
  • Publication number: 20140273377
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a top portion and a bottom portion on a substrate, forming a sacrificial layer contacting the bottom portions of the gate patterns, forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer, removing the sacrificial layer after forming the first spacer, and forming a plurality of first recesses on lateral surfaces of the gate patterns after removing the sacrificial layer.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventor: JIN-BUM KIM
  • Publication number: 20140264495
    Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.
    Type: Application
    Filed: July 15, 2013
    Publication date: September 18, 2014
    Inventors: FANG-HAO HSU, ZUSING YANG, HONG-JI LEE
  • Publication number: 20140264614
    Abstract: A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Publication number: 20140264553
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chiang MIN, Tsung-Hsueh Yang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8829524
    Abstract: An exemplary thin film transistor array substrate (200) includes a substrate (210) and a gate electrode (220) formed on the substrate. The gate electrode includes an adhesive layer (226) formed on the substrate, a conductive layer (224) formed on the adhesive layer and a barrier layer (222) formed on the conductive layer, the adhesive layer and the barrier layer both have sandwich structures. A central core of the adhesive layer, the conductive layer, and a central core of the barrier layer are made of a same material.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: September 9, 2014
    Assignee: Innolux Corporation
    Inventor: Shuo-Ting Yan
  • Publication number: 20140246732
    Abstract: An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Nien Chen, Eric Huang, Chi-Hsun Hsieh, Wei Cheng Wu, Bao-Ru Young, Harry Hak-Lay Chuang
  • Patent number: 8823064
    Abstract: Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Chung-Hsun Lin, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8822278
    Abstract: Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Chung-Hsun Lin, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8816446
    Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Manuel Angel Quevedo-Lopez
  • Patent number: 8802513
    Abstract: A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Thomas N. Adam, Kangguo Cheng, Paul C. Jamison, Ali Khakifirooz
  • Patent number: 8802185
    Abstract: An object is to provide a deposition method for smoothly obtaining desired pattern shapes of material layers and a method for manufacturing a light-emitting device while throughput is improved when a plurality of different material layers is stacked on a substrate. A material layer is selectively formed in advance in a position overlapped with a light absorption layer over a first substrate by pump feeding. Three kinds of light-emitting layers are deposited on one deposition substrate. This first substrate and a second substrate that is to be a deposition target substrate are arranged to face each other, and the light absorption layer is heated by being irradiated with light, whereby a film is deposited on the second substrate. Three kinds of light-emitting layers can be deposited with positional accuracy by performing only one position alignment before light irradiation.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka, Hisao Ikeda, Satoshi Seo
  • Publication number: 20140217516
    Abstract: A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 7, 2014
    Applicant: INTELLECTUAL VENTURES II LLC
    Inventor: Won-Ho Lee
  • Publication number: 20140210012
    Abstract: Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Unsoon Kim
  • Publication number: 20140199827
    Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8778757
    Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Park, Sang-sup Jeong
  • Patent number: 8778763
    Abstract: A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: July 15, 2014
    Assignee: Hermes Microvision, Inc.
    Inventor: Hong Xiao
  • Patent number: 8772147
    Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Publication number: 20140187030
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
    Type: Application
    Filed: March 18, 2013
    Publication date: July 3, 2014
    Applicant: SK HYNIX INC.
    Inventors: Yun-Hyuck JI, Se-Aug JANG, Seung-Mi LEE, Hyung-Chul KIM
  • Patent number: 8765587
    Abstract: A method of manufacturing non-volatile memory devices includes forming a gate insulating layer and a first conductive layer over a semiconductor substrate, etching the first conductive layer and the gate insulating layer to expose part of the semiconductor substrate, forming trenches at a target depth of the semiconductor substrate by repeatedly performing a dry etch process for etching the exposed semiconductor substrate and a cleaning process for removing residues generated in the dry etch process, forming isolation layers within the trenches, forming a dielectric layer on a surface of the entire structure in which the isolation layers are formed, and forming a second conductive layer on the dielectric layer.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Su Hyun Lim, Seung Cheol Lee
  • Patent number: 8766348
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include a first select-gate and a second select-gate disposed on the cell region, the first select-gate and the second select-gate spaced apart from each other. A plurality of cell gate structures are disposed between the first select-gate and the second select-gate. The first select-gate and an adjacent cell gate structure have no air gap defined therebetween. At least a pair of adjacent cell gate structures have an air gap defined therebetween.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Kyung Kim, Woosung Choi
  • Patent number: 8766367
    Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street
  • Patent number: 8765589
    Abstract: A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a surface and a rising surface that protrudes upward from the surface, on a semiconductor substrate; forming a conductive layer to cover the insulation layer having the protruding portion; and removing a predetermined region of the conductive layer by patterning the predetermined region according to an etching process using microwave plasma, which uses a microwave as a plasma source, while applying bias power of 70 mW/cm2 or above on the semiconductor substrate, under a high pressure condition of 85 mTorr or above.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: July 1, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tetsuya Nishizuka, Masahiko Takahashi
  • Publication number: 20140175541
    Abstract: A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench. At least one layer of electrically conductive material is formed within each trench superimposed on the at least one layer of insulating material. The formation of the plurality of trenches includes forming the trenches partitioned into sub-sets of trenches. The trenches of a first sub-set are oriented along a first common direction that is different from the orientation of the trenches of a second sub-set.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 26, 2014
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Angelo Matri', Francesco Lizio
  • Patent number: 8759163
    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Wen-Shen Chou, Jui-Cheng Huang
  • Publication number: 20140170844
    Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.
    Type: Application
    Filed: January 29, 2014
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
  • Publication number: 20140170843
    Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Shenqing FANG, Unsoon KIM, Mark RAMSBEY, Kuo Tung CHANG, Sameer HADDAD
  • Publication number: 20140167139
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Kuo Tung CHANG, Chun CHEN, Shenqing FANG
  • Patent number: 8753940
    Abstract: One method includes forming a plurality of trenches in a semiconducting substrate to define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed and wherein the subset of fins is comprised of at least one but less than all of the fins, performing an etching process through the masking layer to remove at least a portion of the layer of overfill material and expose the upper surface of the subset of fins, and performing a second etching process on the exposed surface of the subset of fins to remove the subset of fins.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy C. Wei, Dae Geun Yang
  • Patent number: 8748256
    Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Gregory Charles Baldwin, Shashank S. Ekbote, Youn Sung Choi
  • Patent number: 8748302
    Abstract: In a replacement gate approach, the dielectric material for laterally encapsulating the gate electrode structures may be provided in the form of a first interlayer dielectric material having superior gap filling capabilities and a second interlayer dielectric material that provides high etch resistivity and robustness during a planarization process. In this manner, undue material erosion upon replacing the placeholder material may be avoided, which results in reduced yield loss and superior device uniformity.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christopher M. Prindle, Johannes F. Groschopf, Andreas R. Ott
  • Patent number: 8741719
    Abstract: A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Publication number: 20140145267
    Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.
    Type: Application
    Filed: July 22, 2013
    Publication date: May 29, 2014
    Inventors: GuoHao CAO, Guangli YANG, Yang ZHOU, GangNing WANG
  • Patent number: 8735892
    Abstract: An object of one embodiment of the disclosed invention is to provide a semiconductor device having a novel structure in which stored data can be held even when power is not supplied and the number of times of writing is not limited. The semiconductor device is formed using an insulating layer formed over a supporting substrate and, over the insulating layer, a highly purified oxide semiconductor and single crystal silicon which is used as a sililcon on insulator (SOI). A transistor formed using a highly purified oxide semiconductor can hold data for a long time because leakage current thereof is extremely small. Further, by using an SOI substrate and utilizing features of thin single crystal silicon formed over an insulating layer, fully-depleted transistors can be formed; therefore, a semiconductor integrated circuit with high added values such as high integration, high-speed driving, and low power consumption can be obtained.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8722483
    Abstract: The invention discloses a method for manufacturing a dual-layer polysilicon gate. The method includes: depositing silicon nitride on silicon oxide of an integrated circuit to be processed; performing anisotropic etching on the silicon nitride to form sidewalls of silicon nitride on sidewalls of a first layer of polysilicon gate of the integrated circuit to be processed; manufacturing a second layer of polysilicon gate; and rinsing the sidewalls of silicon nitride.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 13, 2014
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Guangran Pan
  • Publication number: 20140127892
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 8, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • Patent number: 8716117
    Abstract: A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeongcheol Kim, Sooyeon Jeong, Joon Goo Hong, Dohyoung Kim, Yongjin Kim, Jin Wook Lee, Yoonhae Kim
  • Patent number: 8716089
    Abstract: A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Patent number: 8716094
    Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Global Foundries Inc.
    Inventors: Chang Seo Park, Linus Jang, Jin Cho
  • Publication number: 20140117413
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: Yakimishu Co. Ltd. L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Publication number: 20140117466
    Abstract: Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Vamsi K. Paruchuri
  • Publication number: 20140110764
    Abstract: Methods and apparatuses for combinatorial processing are disclosed. Methods of the present disclosure providing a substrate, the substrate comprising a plurality of site-isolated regions. Methods include forming a first capping layer on the surface of a first site-isolated region of the substrate. The methods further include forming a second capping layer on the surface of a second site-isolated region of the substrate. In some embodiments, forming the first and second capping layers include exposing the first and second site-isolated regions to a plasma induced with H2 and hydrocarbon gases. In some embodiments, methods include applying at least one subsequent process to each site-isolated region. In addition, methods include evaluating results of the films post processing.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: Intermolecular Inc.
    Inventors: Sandip Niyogi, Sean Barstow, Dipankar Pramanik
  • Publication number: 20140110719
    Abstract: Provided is a manufacturing method for an array substrate, which relates to the technical field of displaying and comprises the steps of: S1: forming a pattern which comprises a first gate electrode (2) on a substrate (1); S2: forming a second gate electrode (4) above the first gate electrode (2) on the substrate (1) after step S1, and conducting oxidation treatment on the surface of the second gate electrode (4) to form a gate-insulating layer, the first gate electrode (2) and the second gate electrode (4) forming a gate electrode together; and S3: forming a layer-level structure of a pattern which comprises an active layer, source and drain electrodes, a data line, a passivation layer and a pixel electrode on the substrate after step S2. Also provided are an array substrate and a display device.
    Type: Application
    Filed: November 15, 2012
    Publication date: April 24, 2014
    Inventor: Bing Sun
  • Publication number: 20140104945
    Abstract: Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: CHANGHYUN LEE, BYOUNGKEUN SON
  • Patent number: 8697560
    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Balaji Padmanabhan
  • Publication number: 20140097497
    Abstract: Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: Spansion LLC
    Inventor: Angela T. HUI
  • Publication number: 20140097482
    Abstract: A NAND flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Kazuya Tokunaga, Jongsun Sel, Marika Gunji-Yoneoka, Tuan Pham
  • Patent number: 8685850
    Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 1, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu
  • Publication number: 20140087551
    Abstract: Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Inventors: Jerome A. IMONIGIE, Prashant Raghu