Forming Array Of Gate Electrodes Patents (Class 438/587)
  • Patent number: 8679923
    Abstract: A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Junzhu Cao, Lily Jiang, Cindy Li, Creek Zhu
  • Patent number: 8680623
    Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Arvind Kumar, Vijay Narayanan, Vamsi K. Paruchuri, Jeffrey Sleight
  • Publication number: 20140077299
    Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Helmut Horst Tews, Andre Schenk
  • Publication number: 20140077310
    Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 20, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yasushi Ishii, Hiraku Chakihara, Kentaro Saito
  • Publication number: 20140073124
    Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.
    Type: Application
    Filed: November 14, 2013
    Publication date: March 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei CHEN, Jung-Hsuan CHEN, Shao-Yu CHOU, Hung-Jen LIAO, Li-Chun TIEN
  • Publication number: 20140070326
    Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 13, 2014
    Applicant: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20140061784
    Abstract: The present invention provides a semiconductor device in which the threshold voltage of NMOS and the threshold voltage of PMOS are independently controllable, and a method for fabricating the same.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK hynix Inc.
    Inventor: Dong-Kyun KANG
  • Patent number: 8664071
    Abstract: A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: March 4, 2014
    Inventor: John James Seliskar
  • Patent number: 8658524
    Abstract: A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: February 25, 2014
    Assignee: Cambridge Silicon Radio Limited
    Inventors: Rainer Herberholz, David Vigar
  • Patent number: 8658502
    Abstract: The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 25, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Zaifeng Tang, Yukun Lv, Chao Fang, HsuSheng Chang
  • Patent number: 8658526
    Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8652909
    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 8652904
    Abstract: A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: February 18, 2014
    Assignee: NXP, B.V.
    Inventors: Philip Rutter, Christopher Martin Rogers
  • Patent number: 8647938
    Abstract: SRAM ICs and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer. The method involves anisotropically etching U-shaped channels in the oxide layer corresponding to pattern, and thereafter isotropically etching U-shaped channels in the silicon layer to form saddle-shaped fins in the silicon. A second oxide layer is deposited over the saddle-shaped fins, and a first metal layer is deposited over the second oxide layer. A contact metal layer is formed over the first metal layer and planarized to form local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 11, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Peter Baars, Matthias Goldbach
  • Patent number: 8647952
    Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Richard Carter, Andy Wei
  • Patent number: 8642458
    Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hong Chung, Young-Hee Kim, In-Sun Yi, Han-Mei Choi
  • Patent number: 8637389
    Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: January 28, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8637362
    Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8635573
    Abstract: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (?{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 ?m2).
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: January 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hak-Lay Chuang, Ming Zhu, Po-Nien Chen, Bao-Ru Young
  • Publication number: 20140017886
    Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 16, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Wee TEO, Ming ZHU, Hui-Wen LIN, Bao-Ru YOUNG, Harry-Hak-Lay CHUANG
  • Patent number: 8629048
    Abstract: A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVilliers
  • Publication number: 20140009211
    Abstract: Radio-frequency (RF) switch circuits are disclosed having transistor gate voltage compensation to provide improved switching performance. RF switch circuits include a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate. A compensation network including a coupling circuit couples the gates of each pair of neighboring FETs.
    Type: Application
    Filed: July 6, 2013
    Publication date: January 9, 2014
    Inventors: Anuj Madan, Fikret Altunkilic, Guillaume Alexandre Blin
  • Publication number: 20140008720
    Abstract: A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicants: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Ruilong Xie, Pranatharthi Haran Balasubramanian
  • Patent number: 8623716
    Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 8618604
    Abstract: A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: December 31, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Atsushi Narazaki
  • Patent number: 8618616
    Abstract: A method for fabricating a FinFET structure includes fabricating a plurality of parallel fins overlying a semiconductor substrate, each of the plurality of parallel fins having sidewalls and forming an electrode over the semiconductor substrate and between the parallel fins. The electrode is configured to direct an electrical field into the fins, thereby affecting the threshold voltage of the FinFET structure.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 31, 2013
    Assignee: Globalfoundries, Inc.
    Inventor: Daniel Thanh Khac Pham
  • Patent number: 8617996
    Abstract: Methods for removal of fins from a semiconductor structure are provided. A fin liner is applied to the fins. The fin liner is then removed from the fins that are to be removed. The fin liner is of a material that is selective compared to the semiconductor fins. Hence, the fins can be removed without significant damage to the fin liner. The subsets of fins that are to be removed are then removed, while the fin liner protects the adjacent fins that are to be kept.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min-hwa Chi, Honglian Shen, Changyong Xiao
  • Patent number: 8617974
    Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.
    Type: Grant
    Filed: October 28, 2012
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Ishii, Hiraku Chakihara, Kentaro Saito
  • Patent number: 8610205
    Abstract: In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Dean E. Probst
  • Patent number: 8610176
    Abstract: An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 17, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Prayag B. Patel, Pratyush Kamal, Foua Vang, Chock H. Gan, Pr Chidambaram, Chethan Swamynathan
  • Publication number: 20130323887
    Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 5, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8598028
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hao Tu, Chi-Jen Liu, Tzu-Chung Wang, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
  • Publication number: 20130309856
    Abstract: Semiconductor devices and methods of their fabrication are disclosed. One method includes forming a semiconductor device structure including a plurality of dummy gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the dummy gates. An etch resistant nitride layer is applied above the dielectric gap filling material to maintain the aspect ratio of the gap filling material. In addition, the dummy gates are removed by implementing an etching process. Further, replacement gates are formed in regions of the device structure previously occupied by the dummy gates.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: HEMANTH JAGANNATHAN, SANJAY MEHTA, CHUN-CHEN YEH
  • Patent number: 8586436
    Abstract: Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Ming Zhu, Chi-Wen Liu
  • Patent number: 8586462
    Abstract: Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: November 19, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Byoung-Gue Min, Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
  • Patent number: 8581308
    Abstract: A device for storing embedded charge includes a first insulator and at least one second insulator. The first insulator has at least two outer surfaces and has a band gap of less than about 5.5 eV. The second insulator is deposited on at least each of the at least two outer surfaces of the first insulator to form at least one interface for storing charge between the first and second insulators. The second insulator has a band gap of more than about 6.0 eV.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: November 12, 2013
    Assignee: Rochester Institute of Technology
    Inventor: Michael D. Potter
  • Patent number: 8581322
    Abstract: A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: November 12, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wuu Yang
  • Patent number: 8575013
    Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: November 5, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Peter Baars, Matthias Goldbach
  • Publication number: 20130288472
    Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.
    Type: Application
    Filed: February 7, 2013
    Publication date: October 31, 2013
    Inventors: Jay-Bok Choi, Yoo-Sang Hwang, Ah-Young Kim, Ye-Ro Lee, Gyo-Young Jin, Hyeong-sun Hong
  • Patent number: 8563410
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
  • Publication number: 20130270644
    Abstract: Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement gate structures.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. ANDERSON, Edward J. NOWAK
  • Publication number: 20130256804
    Abstract: According to one exemplary implementation, an integrated circuit (IC) includes a first memory cell transistor of a read only memory (ROM) array, the first memory cell transistor including a first metal gate of a first work function and having a first threshold voltage. The IC also includes a second memory cell transistor of the ROM array, the second memory cell transistor including a second metal gate of a second work function and having a second threshold voltage. The first memory cell transistor and the second memory cell transistor can be of a first conductivity type. Furthermore, the first memory cell transistor can include a first high-k gate dielectric and the second memory cell transistor can include a second high-k gate dielectric.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: BROADCOM CORPORATION
    Inventor: Wei Xia
  • Patent number: 8546252
    Abstract: A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8541826
    Abstract: A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: September 24, 2013
    Assignee: Tsinghua University
    Inventors: Liyang Pan, Haozhi Ma
  • Patent number: 8541284
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwang Sim
  • Publication number: 20130242645
    Abstract: Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors.
    Type: Application
    Filed: July 20, 2011
    Publication date: September 19, 2013
    Applicant: University of Virginia Patent Foundation
    Inventors: Benton H. Calhoun, Randy W. Mann
  • Publication number: 20130237044
    Abstract: A method of manufacturing metal gates comprises the steps of: forming a plurality of parallel trenches on a substrate; forming sequentially a conductive layer and a protective layer on the surfaces of the substrate and trenches; removing the protective layer and conductive layer on the surface of the substrate and the protective layer on the bottom walls of the trenches through anisotropic etching to retain only the protective layer and conductive layer on the side walls; and finally removing the conductive layer not covered by the protective layer through isotropic etching to retain only the protective layer and conductive layer on the side walls so that two insulating gates are respectively formed on the side walls. Thus no isolation material is needed to be disposed at the bottom of the trenches, and the problem of excessive etching to the trenches that results in undesirable insulation can be averted.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Inventors: Hsiao-chia CHEN, Chien-hua TSAI
  • Publication number: 20130234245
    Abstract: A super junction structural semiconductor device with a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region; trench gate MOSFET units in the first region comprising a plurality of trench gate regions and a first plurality of pillars; a body region between the trench gate regions and the first plurality of pillars; a second plurality of pillars in the second region extending along a corresponding side of the first region comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein in a corner part of the second region, ends of the plurality of lateral pillars and ends of the plurality of longitudinal pillars are stagger and separated apart from each other.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 12, 2013
    Applicant: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Rongyao Ma, Tiesheng Li, Donald Disney, Lei Zhang
  • Patent number: 8530942
    Abstract: According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsubasa Yamada
  • Publication number: 20130228844
    Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 5, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi NAGASHIMA, Fumitaka Arai, Hisataka Meguro