Gettering Of Substrate Patents (Class 438/58)
  • Patent number: 6635517
    Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: October 21, 2003
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta, Paul A. Ronsheim, Ghavam G. Shahidi
  • Patent number: 6617189
    Abstract: A method of fabricating an image sensor on a semiconductor substrate including a sensor array region is introduced. First, an R/G/B color filter array (CFA) is formed on portions of the semiconductor substrate corresponding to the sensor array region. Then, a spacer layer is formed on the R/G/B CFA, and a plurality of U-lens is formed on the spacer layer corresponding to the R/G/B CFA. Afterwards, a buffer layer is coated to fill a space between the U-lens, and a low-temperature passivation layer is deposited on the buffer layer and the U-lens at a temperature of about 300° C. or less to prevent the R/G/B CFA from damage.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: September 9, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Tze-Jing Chen, Ching-Chung Chen, Tung-Hu Lin, Chen-Bin Lin, Chi-Rong Lin
  • Patent number: 6586270
    Abstract: A process for producing a stable photovoltaic element having an electrode structure comprising a collecting electrode and a metal bus bar which are connected to have an improved connection between them. Said electrode structure is formed by dotting an electrically conductive paste onto a metal wire as the collecting electrode such that a dotted electrically conductive paste has an elliptical form whose major axis and minor axis are respectively perpendicular to and parallel to a lengthwise direction of said metal wire, arranging the metal bus bar on said dotted electrically conductive paste, and heating the resultant while pressing it to cure the electrically conductive paste to form connection between the metal wire as the collecting electrode and the metal bus bar.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: July 1, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kouji Tsuzuki, Tsutomu Murakami, Kouichi Shimizu
  • Patent number: 6551866
    Abstract: A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step for conducting heat treatment to the single crystalline silicon 3 after the step of forming the storage node and gettering contaminants contained in the single crystalline silicon 3 by the conductive layer 7 connected to the single crystalline silicon, and a step of forming a gate oxide film 8a on the single crystalline silicon 3 after the step of gettering is provided to thereby obtain a sufficient gettering effect even though the width of an element and/or the thickness of the element is reduced in accordance with microminiaturization of the element.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: April 22, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shigenobu Maeda
  • Patent number: 6465873
    Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: October 15, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Fernando González
  • Publication number: 20020127762
    Abstract: In a method for manufacturing a solid state image pick up device capable of improving gettering efficiency a semiconductor substrate having a front side on which a solid state image pick-up device may be formed, and a rear side opposite to the front side is provided. Subsequently, a polysilicon layer including impurities for gettering having a predetermined concentration is formed on the rear side of the semiconductor substrate. Next, a predetermined thickness of the polysilicon layer including the impurities for gettering is oxidized, and the impurities for gettering are condensed into the reduced polysilicon layer.
    Type: Application
    Filed: November 27, 2001
    Publication date: September 12, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-sik Park, Mikio Takagi, Jae-heon Choi, Sang-il Jung, Jun-taek Lee
  • Patent number: 6420246
    Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: July 16, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Publication number: 20020034837
    Abstract: In a method of activating CdTe thin-film solar cells, substrates provided with a CdS layer and the CdTe layer are exposed to a gas mixture containing HCl, oxygen and nitrogen at an elevated temperature and at a total pressure below atmospheric pressure, the HCl partial pressure of the gas mixture being set at levels between 0.002 % and 0.2 % of the total gas pressure.
    Type: Application
    Filed: July 18, 2001
    Publication date: March 21, 2002
    Inventors: Manuel D. Campo, Dieter Bonnet, Rainer Gegenwart, Jutta Beier
  • Patent number: 6342436
    Abstract: There is a provided a method of manufacturing a semiconductor substrate in which generation of bright points after epitaxial growth is reduced, and there is provided a method of manufacturing a solid-state image-pickup device in which illuminated defects are reduced. In fabrication of an epitaxial semiconductor substrate for a solid-state image-pickup device, an epitaxial layer is grown at a growth temperature of 1,120° C. or lower. Pre-annealing is preferably performed at a temperature of 900° C. or lower before hydrogen annealing.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: January 29, 2002
    Assignee: Sony Corporation
    Inventor: Ritsuo Takizawa
  • Patent number: 6339018
    Abstract: A method and structure for preventing device leakage. The method and structure includes forming a blocking layer of preferably nitride over a junction between a source/drain region and a shallow trench isolation. A silicide is then formed over a landed area of the source/drain region but is blocked by the blocking layer from forming over the junction between the source/drain region and the shallow trench isolation. This prevents device leakage at this location.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: January 15, 2002
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Terence B. Hook
  • Patent number: 6261860
    Abstract: There is provided a method of fabricating a solid-state image sensor, comprising the step of carrying out heat treatment before formation of a gate of the solid-state image sensor, a maximum temperature in the heat treatment being in the range of 1000 to 1200 degrees centigrade both inclusive, the step of carrying out heat treatment further including the steps of (a) carrying out lamp-up at least twice, and (b) carrying out lamp-down at least twice. The method makes it possible to grow BMD (Bulk-Micro-Defect) in a wafer in a greater size than a size of BMD to be grown in accordance with a conventional method, ensuring reduction in illuminated or white defect.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: July 17, 2001
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Nagata
  • Patent number: 6221741
    Abstract: A semi-insulating polycrystalline silicon layer containing oxygen of at least 10 percent by atom is grown on a back surface of a single crystalline silicon wafer, and achieves high gettering efficiency at a thickness less than the thickness usual polycrystalline silicon so that the silicon substrate is less warped
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Koji Hamada
  • Patent number: 6136670
    Abstract: In one aspect, the invention includes a semiconductor processing method of forming a contact between two electrically conductive materials comprising: a) forming a first conductive material over a substrate, the first conductive material being capable of being oxidized in the presence of oxygen to an insulating material; b) sputter cleaning the first conductive material in the presence of oxygen in a gaseous phase and in the presence of an oxygen gettering agent; and c) forming a second conductive material in electrical contact with the first conductive material.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: October 24, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Max Hineman
  • Patent number: 6043105
    Abstract: A method of manufacturing a semiconductor device having a non-single crystalline semiconductor layer including an intrinsic or substantially instrinsic silicon which contains hydrogen or halogen and is formed on a substrate in a reaction chamber which may have a substrate holder. Sodium is removed from the inside of the reaction chamber and/or the surface of the substrate holder to remove sodium therefrom so that the concentration of sodium in the semiconductor layer is preferably 5.times.10.sup.18 atoms/cm.sup.3 or less.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: March 28, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6013873
    Abstract: A photovoltaic apparatus includes a first conductive layer, a semiconductor layer and a second conductive layer on a substrate. The first conductive layer is divided into a first electrode layer and into a peripheral first electrode layer by the lower peripheral groove filled up with a first peripheral insulating material. The first upper peripheral groove is provided at the upper portion of the lower peripheral groove, to divide the semiconductor layer and the second conductive layer. The second peripheral insulating material is provided at the outer region of the lower peripheral groove to divide the semiconductor layer. The second upper part peripheral groove is provided at the upper part of the second peripheral insulating material to divide the semiconductor layer and the second conductive layer.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: January 11, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Naoki Daito, Toshihiro Nomura, Ryuji Okawa, Koji Katsube, Yoshinobu Takabatake
  • Patent number: 5961743
    Abstract: A method of manufacturing a thin-film solar cell, comprising the steps or: forming an amorphous silicon film on a substrate; holding a metal element that accelerates the crystallization of silicon in contact with the surface of the amorphous silicon film; subjecting the amorphous silicon film to a heat treatment to obtain a crystalline silicon film; depositing a silicon film to which phosphorus has been added in close contact with the crystalline silicon film; and subjecting the crystalline silicon film and the silicon film to which phosphorus has been added to a heat treatment.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: October 5, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 5944889
    Abstract: With a view to optimizing the donor killing process performed in the semiconductor wafer fabricating process, a heat-treating operation is performed in a thermal furnace above at least 900 .degree. C. for a predetermined time so that growth of the initial oxygen precipitates, induced into the crystal lattices during single-crystal growth, is suppressed.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: August 31, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-guen Park, Gon-sub Lee, Kyoo-chul Cho, Ho-kyoon Chung