Selectively Interconnecting (e.g., Customization, Wafer Scale Integration, Etc.) Patents (Class 438/598)
  • Patent number: 8106515
    Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffery B. Maxson, Aurelia A. Suwarno-Handayana, Shamas M. Ummer, Kenneth J. Giewont, Scott Richard Stiffler
  • Patent number: 8105936
    Abstract: Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma. Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may be provided along an interface between the via and an internal metal layer.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Louis C. Hsu, Rajiv V. Joshi
  • Publication number: 20120009774
    Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 12, 2012
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8071468
    Abstract: There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: December 6, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hideyuki Sameshima, Tomoo Ono
  • Patent number: 8053349
    Abstract: A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth R. Rhyner, Kevin Lyne, David G. Wontor, Peter R. Harper
  • Patent number: 8053352
    Abstract: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Roger Allen Booth, Jr., Matthew Stephen Doyle
  • Patent number: 8048804
    Abstract: A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in which a functional element is disposed; a step C that removes the first transforming portion that is disposed on the first substrate by etching; and a step D that forms a conductive portion in the first substrate by filling a conductive material in a portion where the first transforming portion has been removed.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: November 1, 2011
    Assignee: Fujikura Ltd.
    Inventor: Shogo Mitani
  • Publication number: 20110263116
    Abstract: A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically conductive, quasi one- or zero-dimensional electron gas is present such that the interface presents an electrically conductive region that is non-volatile. The second insulating layer is of a thickness to allow metal-insulator transitions upon the application of a first external electric field. The electrically conductive region is subject to erasing upon application of a second external electric field.
    Type: Application
    Filed: June 30, 2011
    Publication date: October 27, 2011
    Inventor: Jeremy LEVY
  • Publication number: 20110261491
    Abstract: A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 27, 2011
    Inventors: JASON C. PERKEY, Scott S. Roth, Tim J. Zoerner
  • Patent number: 8026593
    Abstract: An integrated circuit package system is provided including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: September 27, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang
  • Patent number: 8021978
    Abstract: Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Sun Sel, Jung-Dal Choi
  • Patent number: 8008126
    Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: August 30, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Boon Suan Jeung, Chia Yong Poo, Low Siu Waf, Eng Meow Koon, Chua Swee Kwang, Huang Shuang Wu, Neo Yong Loo, Zhou Wei
  • Patent number: 7994041
    Abstract: A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is provided. The method includes forming a seed layer required for forming a via core on a bottom surface of a wafer, forming at least one via hole vertically through the wafer, forming a via core in the via hole, insulating the via hole from the via core, and removing the seed layer from the bottom surface of the wafer. The stacked semiconductor package is suitable for high-speed signal transmission.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 9, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwon-Seob Lim, Hyun Seo Kang
  • Patent number: 7994049
    Abstract: The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takuya Futase
  • Patent number: 7989914
    Abstract: An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: August 2, 2011
    Assignees: STMicroelectronics Crolles 2 SAS, Koninklijke Philips Electronics N.V.
    Inventors: Bertrand Borot, Roberto Maurizio Gonella, Sébastien Fabre
  • Patent number: 7982285
    Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Byeongju Park, Subramanian S. Iyer, Chandrasekharan Kothandaraman
  • Patent number: 7977229
    Abstract: A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductive posts, so that the plurality of conductive bump is soldered onto the circuit board when the semiconductor device is mounted on the circuit board. A distance between a peripheral edge of the semiconductor device and an outer edge of the conductive post is determined to be narrow so that a solderbility or wetting condition of the conductive bumps can be visibly recognized easily.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: July 12, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Yasuo Tanaka
  • Patent number: 7968458
    Abstract: A production process for making an electronic circuit substrate comprising: a patterning step of forming a respectively anodically oxidizable conductor pattern and distribution pattern connected to the conductor pattern on a substrate; and an anodic oxidation step of generating an oxide film from the conductor pattern and the distribution pattern by contacting an electrolyte solution with the conductor pattern and the distribution pattern and carrying out anodic oxidation while applying current thereto, the patterns serving as anodes, wherein the width or film thickness of the distribution pattern is at least partially set so that an insulator portion is formed in the anodic oxidation step in which an oxide film formed on one of the side walls of the distribution pattern is integrated with an oxide film formed on the other side wall.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: June 28, 2011
    Assignee: Pioneer Corporation
    Inventors: Takashi Chuman, Satoru Ohta, Satoshi Miyaguchi
  • Patent number: 7964969
    Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventor: Takeshi Harada
  • Patent number: 7960269
    Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: June 14, 2011
    Assignee: Megica Corporation
    Inventors: Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 7956448
    Abstract: A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: June 7, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Jean Wang
  • Patent number: 7947532
    Abstract: A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Helmut Strack
  • Patent number: 7943422
    Abstract: Methods for producing a flip chip package by prepackaging one or more dice on a semiconductor wafer are provided. An embodiment of the method includes applying an adhesive to a first side of a finished wafer, where a number of dice are located. The active layer of the dice is on the first side of the finished wafer. The method further includes forming an array of conductive elements within the adhesive, where the array of conductive elements is electrically coupled to an array of connection pads on a die. The wafer can be diced to provide pre-packaged chips. To provide greater mounting densities, two or more dice may be coupled before application of the adhesive layer.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Suan Jeung Boon
  • Patent number: 7935603
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: May 3, 2011
    Assignees: HRL Laboratories, LLC, Raytheon Corporation, Promtek
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Patent number: 7935621
    Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
  • Patent number: 7935594
    Abstract: Forming a metal-insulator diode and carbon memory element in a single damascene process is disclosed. A trench having a bottom and a sidewall is formed in an insulator. A first diode electrode is formed in the trench during a single damascene process. A first insulating region comprising a first insulating material is formed in the trench during the single damascene process. A second insulating region comprising a second insulating material is formed in the trench during the single damascene process. A second diode electrode is formed in the trench during the single damascene process. The first insulating region and the second insulating region reside between the first diode electrode and the second diode electrode to form a metal-insulator-insulator-metal (MIIM) diode. A region of carbon is formed in the trench during the single damascene process. At least a portion of the carbon is electrically in series with the MIIM diode.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: May 3, 2011
    Assignee: SanDisk 3D LLC
    Inventors: April Dawn Schricker, Deepak C. Sekar, Andy Fu, Mark Clark
  • Patent number: 7906421
    Abstract: In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A covering material is formed over the solder pad and an uncovered portion of the redistribution line is passivated. The covering material prevents passivation of the solder pad. Solder is then formed over the solder pad such that the uncovered portion of the redistribution line has solder resist properties due to the passivating.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 15, 2011
    Assignee: Qimonda AG
    Inventors: Octavio Trovarelli, Martin Reiss, Bernd Zimmermann
  • Publication number: 20110058292
    Abstract: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 10, 2011
    Inventors: Uwe Hodel, Wolfgang Soldner
  • Patent number: 7897512
    Abstract: Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Cho, Seung-Pil Chung, Dong-Seok Lee
  • Patent number: 7888213
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: February 15, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • Patent number: 7879711
    Abstract: A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: February 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Jean Wang
  • Patent number: 7875544
    Abstract: A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: January 25, 2011
    Assignees: Infineon Technologies AG, International Business Machines Corporation, United Microelectronics Co.
    Inventors: Robert C. Wong, Ernst H. Demm, Pak Leung, Alexander M. Hirsch
  • Patent number: 7867886
    Abstract: A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: January 11, 2011
    Assignee: Cavendish Kinetics, Ltd
    Inventors: Charles Gordon Smith, Robertus P. Van Kampen
  • Patent number: 7858510
    Abstract: Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350° C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al—N, Al—O or both Al—O and Al—N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and/or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 28, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Ananda Banerji, George Andrew Antonelli, Jennifer O'loughlin, Mandyam Sriram, Bart van Schravendijk, Seshasayee Varadarajan
  • Patent number: 7847368
    Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: December 7, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paval Kornilovich, Peter Mardilovich, Sriram Ramamoorthi
  • Patent number: 7842613
    Abstract: Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: November 30, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Kuolung Lei
  • Patent number: 7842610
    Abstract: A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangular ring-shaped semiconductor is formed around the inner through-electrode, and the outer peripheral through-electrode is formed around the quadrangular ring-shaped semiconductor.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 30, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 7838408
    Abstract: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshihisa Matsubara, Hiromasa Kobayashi
  • Patent number: 7833894
    Abstract: A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof are passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and conductive material at both the active surface and the thinned back side. A metal layer having a glass transition temperature greater than that of the solder may be plated to form a dam structure covering one or both ends of the TWI. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: W. Mark Hiatt
  • Patent number: 7833895
    Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: November 16, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas D. Bonifield, Brian E. Goodlin, Mona M. Eissa
  • Patent number: 7811931
    Abstract: A semiconductor device has a plurality of interconnect layers each including a plurality of interconnect lines. The semiconductor device includes a dielectric film (HDP film) formed by means of high density plasma-enhanced CVD and including an edge formed on the side surface of the topmost-layer interconnect lines, a silicon oxide film formed by modifying a SOG film on the HDP film between adjacent two of the topmost-layer interconnect lines in the element forming region, and a passivation film formed to cover the HDP film and the topmost-layer interconnect lines.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: October 12, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Masateru Ando
  • Patent number: 7807570
    Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffery B. Maxson, Aurelia A. Suwarno-Handayana, Shamas M. Ummer, Kenneth J. Giewont, Scott Richard Stiffler
  • Patent number: 7808105
    Abstract: A semiconductor package includes a first semiconductor die; a first redistribution layer coupled to a bonding pad of the first semiconductor die; a first solder bump coupled to the first redistribution layer; a second semiconductor die; a second redistribution layer coupled to a bonding pad of the second semiconductor die; a second solder bump coupled to the second redistribution layer and to the first solder bump; a third redistribution layer coupled to the second redistribution layer; and a solder ball coupled to the third redistribution layer.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: October 5, 2010
    Assignee: Amkor Technology, Inc.
    Inventor: Jong Sik Paek
  • Patent number: 7799671
    Abstract: Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating material (e.g., material generating B, Al, Ti, etc.) over an exposed copper line, converting the upper portion of the source layer to a passivated layer (e.g., nitride or oxide) while allowing an unmodified portion of a dopant-generating source layer to remain in contact with copper, and, subsequently, allowing the dopant from the unmodified portion of source layer to controllably diffuse into and/or react with copper, thereby forming a thin protective cap within copper line. The cap may contain a solid solution or an alloy of copper with the dopant.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: September 21, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Ananda Banerji, George Andrew Antonelli, Jennifer O'Ioughlin, Mandyam Sriram, Bart van Schravendijk, Seshasayee Varadarajan
  • Patent number: 7795126
    Abstract: A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Ashok Prabhu, Sadanand R. Patil, Shaw Wei Lee, Alexander H. Owens
  • Patent number: 7795737
    Abstract: Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an integrated circuit includes providing an integrated circuit comprising an inner lead bondpad. A first insulative passivation layer is formed over the integrated circuit. A bondpad-redistribution line is formed over the first insulative passivation layer and in electrical connection with the inner lead bondpad through the first insulative passivation layer. The bondpad-redistribution line includes an outer lead bondpad area. A second insulative passivation layer is formed over the integrated circuit and the bondpad-redistribution line. The second insulative passivation layer is formed to have a sidewall outline at least a portion of which is proximate to and conforms to at least a portion of the bondpad-redistribution line. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: September 14, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Charles M. Watkins
  • Patent number: 7772047
    Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: August 10, 2010
    Assignee: SanDisk Corporation
    Inventors: Chien-Ko Liao, Chin-Tien Chiu, Jack Chang Chien, Cheemen Yu, Hem Takiar
  • Publication number: 20100197117
    Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state.
    Type: Application
    Filed: April 15, 2010
    Publication date: August 5, 2010
    Inventors: Zhiyong Li, Warren Robinett
  • Patent number: 7768096
    Abstract: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.
    Type: Grant
    Filed: May 3, 2008
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Patent number: 7759231
    Abstract: A method of forming contacts between at least one metallic layer and at least one semiconductor substrate through at least one layer of dielectric in a semiconductor device. The semiconductor device includes, on at least one base face of the semiconductor substrate, the dielectric layer. The metallic layer is stacked on the dielectric layer. The heated ends of plural protruding elements assembled on a support are brought into contact with the metallic layer simultaneously, thereby creating zones of melted metal under the heated ends of the protruding elements. The melted metal traverses the dielectric and amalgamates with the semiconductor of the substrate at the level of the zones of melted metal, thereby creating the contacts.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: July 20, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre Jean Ribeyron, Emmanuel Rolland