Using Structure Alterable To Conductive State (i.e., Antifuse) Patents (Class 438/600)
  • Patent number: 10903274
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10096569
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 9, 2018
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., NATIONAL CHUNG HSING UNIVERSITY
    Inventors: Ying-Ta Chiu, Shang-Kun Huang, Yong-Da Chiu, Jenn-Ming Song
  • Patent number: 9659822
    Abstract: A method for providing position control information for controlling an impingement position of a laser beam for treatment of a chip die in a chip manufacturing process, comprises the steps of a) receiving a specification of positions (x,y) of a electrically conductive elements in the chip die, the positions having a first coordinate along a first direction (x) and a second coordinate (y) along a second direction in a plane defined by the chip die, said first and second direction being mutually transverse to each other, b) selecting a cluster of positions that is within a predetermined two-dimensional spatial range, wherein each pair of positions in the cluster at least has a first minimum difference in their first coordinates or a second minimum difference in their second coordinates and removing the next position from the ordered set, c) update the positions of the set of positions in accordance with an expected time needed to carry out the treatment for said cluster and a speed of a wafer comprising the chi
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: May 23, 2017
    Assignee: NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO
    Inventors: Johannes Adrianus Cornelis Theeuwes, Jeroen Anthonius Smeltink, Egbert Anne Martijn Brouwer, Gerrit Oosterhuis
  • Patent number: 9356030
    Abstract: An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film and an insulating film are alternately stacked over the first conductive layer, and a second conductive layer over the multilayer film. Voltage is applied between the first and second conductive layers and resistance of the multilayer film is decreased, whereby data is written to the memory element. When an insulating film having higher resistance than amorphous silicon is formed between the first and second conductive layers, current flowing through the antifuse at the time of writing is reduced.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 31, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Tajima, Hajime Tokunaga
  • Patent number: 9093455
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Patent number: 9040406
    Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Publication number: 20150097295
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: JaeHyun Lee, SunJae Kim, JoongGi Kim
  • Patent number: 8999835
    Abstract: A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: April 7, 2015
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 8975724
    Abstract: An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yong Park, Zhongze Wang, John J. Zhu, Choh fei Yeap
  • Patent number: 8969141
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventor: Laurentiu Vasiliu
  • Patent number: 8941094
    Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Nantero Inc.
    Inventors: C. Rinn Cleavelin, Thomas Rueckes, H. Montgomery Manning, Darlene Hamilton, Feng Gu
  • Publication number: 20150014811
    Abstract: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Casey Smith, Jasper S. Gibbons, Kunal R. Parekh
  • Publication number: 20150002213
    Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 8916938
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 23, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Publication number: 20140361400
    Abstract: Various embodiments provide electrostatic discharge protection structures and methods for forming the same. An exemplary structure can include a semiconductor chip including a through hole. The structure can further include a through silicon via (TSV) structure disposed within the through hole and passing through the semiconductor chip. The TSV structure can have a first surface and a second surface. The structure can further include a tunneling dielectric layer disposed on the first surface of the TSV structure. The tunneling dielectric layer can have a surface area covering a top view surface area of the TSV structure and a surface portion of the semiconductor chip surrounding the TSV structure. Yet further, the structure can include a metal material discretely dispersed in the tunneling dielectric layer, a first electrode disposed on the tunneling dielectric layer, and a second electrode disposed on the second surface of the TSV structure.
    Type: Application
    Filed: October 18, 2013
    Publication date: December 11, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: ZHENGHAO GAN
  • Patent number: 8860176
    Abstract: The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gregory M. Fritz, Bahman Hekmatshoartabari, Ali Khakifirooz, Dirk Pfeiffer, Kenneth P. Rodbell, Davood Shahrjerdi
  • Publication number: 20140291801
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 2, 2014
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • Patent number: 8841746
    Abstract: SoC and SiP designs are configured with an antifuse link within the die to allow on-die programming of bond wires connecting package lead fingers to the bond pads on the die. This permits alteration of the bond pad connections for the die, particularly for the ground voltage ground signal (VSS) connections on the bond pad, at the testing stage after the die package and the power supply have been installed on the PCB. On-die programming of antifuse link allows the VSS bond pad connections to be reconfigured, typically to eliminate long bond wire runs to reduce ground bounce and simultaneous switching output (SSO) noise, after assembly and field testing of the integrated circuit. Antifuse programming is completed by applying the programming voltage to the programming pad of the antifuse.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: LSI Corporation
    Inventors: Akhilesh Rathi, Arvind Shrivastava
  • Publication number: 20140210043
    Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage VPP greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.
    Type: Application
    Filed: March 27, 2014
    Publication date: July 31, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Zhongze Wang, John Jianhong Zhu, Xia Li
  • Patent number: 8785300
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Andreas Kurz, Jens Poppe
  • Patent number: 8741697
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Thierry Coffi Herve Yao, Shizen Skip Liu
  • Patent number: 8722518
    Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 13, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
  • Patent number: 8709931
    Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 29, 2014
    Assignee: SK Hynix Semiconductor, Inc.
    Inventor: Byung-Duk Lee
  • Publication number: 20140103448
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Patent number: 8689163
    Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: April 1, 2014
    Assignees: Samsung Electronics Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Dong-Yun Kim, Dong-Hoon Yeo, Hyun-Chul Shin, Kyung-Ho Kim, Byung-Tae Kang, Ju-Yong Shin, Sung-Chul Lee
  • Patent number: 8674476
    Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
  • Publication number: 20140070364
    Abstract: An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Yong Park, Zhongze Wang, John J. Zhu, Choh Fei Yeap
  • Publication number: 20140024210
    Abstract: An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.
    Type: Application
    Filed: August 16, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Stephen M. Gates
  • Patent number: 8610245
    Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinsuke Tani, Toshiyuki Nakaiso
  • Patent number: 8610243
    Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Poppe, Andreas Kurz
  • Publication number: 20130307115
    Abstract: A method and structure of a non-intrinsic anti-fuse structure. The anti-fuse structure has a first electrode, a second electrode, a first dielectric, and second dielectric. The first and second dielectrics have an interface which couples electrodes. The length along the interface which couples the electrodes is called the predetermined length. When the anti-fuse is programmed a conductive link forms along the interface to connect the first and second electrodes. The anti-fuse structure can be single-level or dual-level. The predetermined length can be less than spacing between adjacent electrodes when a dual-level structure is used. The anti-fuse structures have the advantage that they can be programmed at lower voltages than intrinsic structures and no extra steps are needed to integrate the anti-fuses with active structures.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Naftali Lustig, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8530319
    Abstract: An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ephrem G. Gebreselasie, Joseph M. Lukaitis, Robert R. Robison, William R. Tonti, Ping-Chuan Wang
  • Patent number: 8507326
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 13, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Andreas Kurz, Jens Poppe
  • Patent number: 8501591
    Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 6, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Han Chao Lai, Wen Jer Tsai, Tao Cheng Lu, Chih Yuan Lu
  • Patent number: 8476157
    Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.?doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.?doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.?doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: July 2, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8471356
    Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Patent number: 8399959
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 19, 2013
    Assignee: Broadcom Corporation
    Inventor: Laurentiu Vasiliu
  • Publication number: 20130065387
    Abstract: A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs.
    Type: Application
    Filed: March 1, 2012
    Publication date: March 14, 2013
    Applicant: MCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 8367483
    Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
  • Patent number: 8367484
    Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
  • Patent number: 8368069
    Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
  • Publication number: 20130029460
    Abstract: Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8361887
    Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Alberto Cestero, Byeongju Park, John M. Safran
  • Patent number: 8339844
    Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: December 25, 2012
    Assignee: eASIC Corporation
    Inventors: Herman Schmit, Ronnie Vasishta, Adam Levinthal, Jonathan Park
  • Patent number: 8329514
    Abstract: Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 11, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Geoffrey W. Perkins, Kyle D. Zukowski, Jiang-Kai Zuo
  • Patent number: 8298905
    Abstract: A method for forming a functional element includes a first step of forming an insulating layer composed of an insulator phase of a transition metal oxide serving as a metal-to-insulator transition material, the transition metal oxide being mainly composed of vanadium dioxide, and a second step of causing part of the insulating layer to transition to a metallic phase, in which the insulator phase differs from the metallic phase in terms of electrical resistivity and/or light transmittance.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: October 30, 2012
    Assignee: Sony Corporation
    Inventor: Daisuke Ito
  • Publication number: 20120248568
    Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Serge Blonkowski
  • Publication number: 20120248546
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • Patent number: 8278155
    Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 2, 2012
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey W. Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen M. Rossnagel, Christy S. Tyberg, Robert L. Wisnieff
  • Patent number: 8247905
    Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell