Transparent Conductor Patents (Class 438/609)
  • Patent number: 7675075
    Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: March 9, 2010
    Assignee: Panasonic Corporation
    Inventor: Hideo Nagai
  • Publication number: 20100038667
    Abstract: An optoelectronic semiconductor chip with a semiconductor body having a semiconductor layer sequence with an active region suitable for generating radiation is specified, wherein the semiconductor chip comprises a radiation-transmissive and electrically conductive contact layer arranged on a semiconductor body and electrically connected to an active region. The contact layer adjoins a barrier layer of the semiconductor layer sequence and a contact layer is applied to the semiconductor body having a structure. An electrode is arranged on the semiconductor body on a side of the active region facing away from the barrier layer and having a contact area, wherein the contact layer adjoins the barrier layer with its entire surface in a region of the barrier layer that is covered by the contact area of the electrode.
    Type: Application
    Filed: January 11, 2008
    Publication date: February 18, 2010
    Inventor: Reiner Windisch
  • Publication number: 20100024862
    Abstract: Provided in this invention is a low-cost substrate provided with a transparent conductive film for photoelectric conversion device, which can improve performance of the photoelectric conversion device by enhanced light confinement effect achieved with effectively increased surface unevenness of the substrate. A method for manufacturing said substrate and a photoelectric conversion device using said substrate which can show improved performance are also provided. The substrate provided with the transparent conductive film for the photoelectric conversion device comprises a transparent insulating substrate and a transparent electrode layer containing at least zinc oxide deposited on the transparent insulating substrate, wherein the transparent electrode layer is composed of a double layer structure wherein first and second transparent conductive films are deposited in this order from a substrate side.
    Type: Application
    Filed: November 12, 2007
    Publication date: February 4, 2010
    Applicant: KANEKA CORPORATION
    Inventor: Yuko Tawada
  • Publication number: 20100029067
    Abstract: Apparatuses and methods are provided for the continuous, roll-to-roll formation of photovoltaic (PV) cells. Apparatuses include reel-to-reel transport chambers, one or more deposition chambers, a differential process isolation unit and a chamber for obtaining real time quality data, including IV data, yield data and uniformity data.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 4, 2010
    Inventors: Aarohi Vijh, Xinmin Cao, Bradley S. Mohring
  • Publication number: 20100001359
    Abstract: A transparent conductive layer includes a substrate, a first conductive layer disposed on the substrate, and a second conductive layer disposed on the first conductive layer, wherein the second conductive layer comprises a textured surface and an opening which exposes the first conductive layer, wherein the opening comprises a diameter of about 1 micrometer to about 3 micrometers. Also disclosed is a method of manufacturing the transparent conductive layer and a photoelectric device.
    Type: Application
    Filed: March 30, 2009
    Publication date: January 7, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae JUNG, Yuk-Hyun NAM, Czang-Ho LEE, Myung-Hun SHIN, Min-Seok OH, Byoung-Kyu LEE, Mi-Hwa LIM, Joon-Young SEO
  • Patent number: 7642183
    Abstract: A high power, high luminous flux light emitting diode (LED) comprises a substrate, a light-emitting structure, a first electrode and a second electrode. The LED has a top surface layout design in which the first electrode has a number of legs extending in one direction, and the second electrode has a number of legs extending in the opposite direction. At least portions of the legs of the first electrode are interspersed with and spaced apart from portions of the legs of the second electrode. This provides a configuration that enhances current spreading along the length of the legs of both electrodes.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: January 5, 2010
    Assignees: Dalian Meiming
    Inventors: Yongsheng Zhao, William W. So, Kevin Y. Ma, Chyi S. Chern, Heng Liu, Eugene J. Ruddy
  • Publication number: 20090323168
    Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the micro electromechanical systems device.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 31, 2009
    Applicant: IDC, LLC
    Inventors: Mark W. Miles, John Batey, Clarence Chui, Manish Kothari
  • Publication number: 20090325331
    Abstract: A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
    Type: Application
    Filed: September 19, 2008
    Publication date: December 31, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Kuo-Lung Fang, Chia-Chi Tsai
  • Publication number: 20090317934
    Abstract: Disclosed is a novel method for creating local contacts in solar cells. In the method, a surface passivation that has been applied to a semiconductor substrate is locally etched away using a plasma process with the help of a thin stretched, elastic foil. If necessary, deep doping gradients are then locally created at the same points by means of a hydrogen plasma treatment with the help of thermal donors so as to increase the diffusion length of the charge carriers in the direction of the contacts. Finally, local heterostructure contacts are applied through the same mask openings. The contacts are characterized by a much lower saturation current than common diffused contacts and are therefore particularly suitable for high-performance solar cells.
    Type: Application
    Filed: August 28, 2007
    Publication date: December 24, 2009
    Inventors: Maximilian Scherff, Wolfgang Rainer Fahrner
  • Publication number: 20090301543
    Abstract: The present invention discloses novel thin film photovoltaic devices with monolithic integration and backside metal contacts and methods of making the devices. The innovative approach described in the present invention allows for devices and methods of construction completely through thin-film processes. Solar cells in accordance with the present invention provide an increased output for large devices due to decreased current loss in the transparent conducting electrode.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 10, 2009
    Applicant: Solexant Corp.
    Inventors: Damoder Reddy, Craig Leidholm, Brian Gergen
  • Patent number: 7628896
    Abstract: A transparent conductive oxide (TCO) based film is formed on a substrate. The film may be formed by sputter-depositing, so as to include both a primary dopant (e.g., Al) and a co-dopant (e.g., Ag). The benefit of using the co-dopant in depositing the TCO inclusive film may be two-fold: (a) it may prevent or reduce self-compensation of the primary dopant by a more proper positioning of the Fermi level, and/or (b) it may promote declustering of the primary dopant, thereby freeing up space in the metal sublattice and permitting more primary dopant to create electrically active centers so as to improve conductivity of the film. Accordingly, the use of the co-dopant permits the primary dopant to be more effective in enhancing conductivity of the TCO inclusive film, without significantly sacrificing visible transmission characteristics. An example TCO in certain embodiments is ZnAlOx:Ag.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: December 8, 2009
    Assignee: Guardian Industries Corp.
    Inventors: Alexey Krasnov, Yiwei Lu
  • Patent number: 7626202
    Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 1, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20090221141
    Abstract: A method for patterning crystalline indium tin oxide (ITO) using femtosecond laser is disclosed, which comprises steps of: (a) providing a substrate with an amorphous ITO layer thereon; (b) transferring the amorphous ITO layer in a predetermined area into a crystalline ITO layer by emitting a femtosecond laser beam to the amorphous ITO layer in the predetermined area; and (c) removing the amorphous ITO layer on the substrate using an etching solution.
    Type: Application
    Filed: January 22, 2009
    Publication date: September 3, 2009
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: CHUNG-WEI CHENG, COSTAS P. GRIGOROPOULOS, DAVID JEN HWANG, MOOSUNG KIM
  • Publication number: 20090179239
    Abstract: A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 16, 2009
    Inventors: Doo-cheol Park, Jung-hyeon Kim, Jun-young Lee
  • Publication number: 20090179220
    Abstract: The present invention provides a semiconductor light-emitting device capable of effectively emitting ultraviolet light and a method of manufacturing the same. A semiconductor light-emitting device 1 includes: a p-type semiconductor layer 14; a semiconductor layer that has an emission wavelength in at least an ultraviolet range; and a transparent electrode 15 that is formed on the p-type semiconductor layer 14. The transparent electrode 15 includes a crystallized IZO film.
    Type: Application
    Filed: April 13, 2007
    Publication date: July 16, 2009
    Applicant: SHOWA DENKO K.K.
    Inventors: Naoki Fukunaga, Hiroshi Osawa
  • Patent number: 7553749
    Abstract: A method of hiding transparent electrodes on a transparent substrate coats a solution of non-conductive nanoparticles onto the transparent substrate and the transparent electrodes after forming a plurality of transparent electrodes on the transparent substrate, and both non-conductive nanoparticles and transparent electrodes have the same reflective index of light. After a high-temperature thermal processing is performed to the transparent substrate, an even mask is formed on the transparent substrate and the transparent electrodes, such that the non-conductive nanoparticles in the mask provide the same reflective index of light for the positions of the transparent substrate with and without the transparent electrodes, so as to effectively prevent a different reflective index of light at any position of the transparent substrate that will cause a poor image quality of the screen.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: June 30, 2009
    Assignee: TPK Touch Solutions Inc.
    Inventor: Chun-Min Hu
  • Patent number: 7528060
    Abstract: A branched nanostructure is synthesized. A porous material, with pores having a diameter of approximately 1 ?m or less, is placed in a vacuum. It is irradiated with an electron beam. This causes a trunk to grow from the porous material and further causes branches to grow from the trunk.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: May 5, 2009
    Assignee: University of Puerto Rico
    Inventors: Luis F. Fonseca, Oscar Resto, Francisco Solá
  • Patent number: 7517784
    Abstract: A method for producing transparent p-type conducting oxide films without co-doping plasma enhancement or high temperature comprising: a) introducing a dialkyl metal at ambient temperature and a saturated pressure in a carrier gas into a low pressure deposition chamber, and b) introducing NO alone or with an oxidizer into the chamber under an environment sufficient to produce a metal-rich condition to enable NO decomposition and atomic nitrogen incorporation into the formed transparent metal conducting oxide.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: April 14, 2009
    Assignee: Alliance For Sustainable Energy, LLC
    Inventors: Xiaonan Li, Yanfa Yan, Timothy J. Coutts, Timothy A. Gessert, Clay M. Dehart
  • Patent number: 7517783
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7476607
    Abstract: An object of the present invention is to provide a photovoltaic cell that demonstrates a superior photoelectric conversion function. The present invention relates to a photovoltaic cell comprising a semiconductor electrode, an electrolyte and a counter electrode, wherein (1) the semiconductor electrode contains an oxide semiconductor layer having photocatalytic activity, (2) the oxide semiconductor layer contains secondary particles in which primary particles comprising a metal oxide are aggregated, (3) the average particle diameter of the primary particles is from 1 nm to 50 nm, and the average particle diameter of the secondary particles is from 100 nm to 10 ?m, and (4) the photovoltaic cell generates electromotive force by radiating light of a wavelength substantially equal to the average particle diameter of the secondary particles onto the semiconductor electrode.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: January 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Yuka Yamada, Nobuyasu Suzuki, Yasunori Morinaga, Hidehiro Sasaki
  • Patent number: 7470608
    Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: December 30, 2008
    Assignee: Panasonics Corporation
    Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
  • Patent number: 7470607
    Abstract: This invention relates to novel, transparent oxide semiconductor thin film transistors (TFT's) and a process for making them.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: December 30, 2008
    Assignee: E.I. Du Pont De Nemours & Company
    Inventors: Peter Francis Carcia, Robert S. McLean
  • Publication number: 20080258174
    Abstract: Disclosed is an optical device including an optical member and a contact layer stacked on at least one of top and bottom surfaces of the optical member. The contact layer has at least one transparent conducting oxynitride (TCON) layer. The TCON consists of at least one of indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium (Mg), titanium (Ti), molybdenum (Mo), nickel (Ni), copper (Cu), silver (Ag), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru), and palladium (Pd).
    Type: Application
    Filed: December 15, 2006
    Publication date: October 23, 2008
    Inventor: Tae-Yeon Seong
  • Patent number: 7432187
    Abstract: A method for improving current distribution of a transparent electrode includes forming a transparent electrode over a substrate; and forming a first mask. First openings are formed in the first mask. The first mask is also located over the transparent electrode. A dispersion, including conductive precursor components, is formed and deposited over the first mask and through the first openings onto the transparent electrode. Upon removal of the first mask, the conductive precursor components of the dispersion are cured to form first patterned conductive areas having a first thickness on the transparent electrode.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: October 7, 2008
    Assignee: Eastman Kodak Company
    Inventor: Ronald S. Cok
  • Publication number: 20080237760
    Abstract: One object of the present invention is to provide a transparent electrode substrate with an ITO film formed thereon, used for example as the transparent electrode plate in a dye sensitized solar cell, for which the electrical resistance does not increase even when exposed to high temperatures of 300° C. or higher. In order to achieve the object, the present invention provides a substrate for a transparent electrode, wherein two or more layers of different transparent conductive films are formed on a transparent substrate, and an upper layer transparent conductive film has a higher heat resistance than that of a lower layer transparent conductive film.
    Type: Application
    Filed: May 1, 2008
    Publication date: October 2, 2008
    Applicant: Fujikura Ltd.
    Inventors: Takuya Kawashima, Hiroshi Matsui, Kenichi Okada, Nubuo Tanabe
  • Patent number: 7416907
    Abstract: A low temperature process for fabricating a high-performance and reliable semiconductor device in high yield, comprising forming a silicon oxide film as a gate insulator by chemical vapor deposition using TEOS as a starting material under an oxygen, ozone, or a nitrogen oxide atmosphere on a semiconductor coating having provided on an insulator substrate; and irradiating a pulsed laser beam or an intense light thereto to remove clusters of such as carbon and hydrocarbon to thereby eliminate trap centers from the silicon oxide film. Also claimed is a process comprising implanting nitrogen ions into a silicon oxide film and annealing the film thereafter using an infrared light, to thereby obtain a silicon oxynitride film as a gate insulator having a densified film structure, a high dielectric constant, and an improved-withstand voltage.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: August 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang
  • Patent number: 7413922
    Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 19, 2008
    Assignee: Au Optronics Corporation
    Inventors: Meng-Yi Hung, Ming-Hung Shih
  • Publication number: 20080191350
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20080191351
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20080194094
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain tungsten and monolayers that contain indium are deposited onto a substrate and subsequently processed to form tungsten-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7410893
    Abstract: A method for depositing a seed layer for a controllable electric pathway on a substrate includes selectively dispensing a seed material from an inkjet material dispenser onto said substrate.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: August 12, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Niranjan Thirukkovalur, Thomas J. Lindner
  • Patent number: 7390731
    Abstract: The process according to the invention makes it possible to deposit a transparent conductive oxide film on a toughened glass substrate placed inside a chamber. It consists in providing sources containing an oxygen-based liquid compound, a liquid compound of the metal intended to form the oxide, and a dopant in gaseous or liquid form, respectively; establishing a temperature between 130 and 300° C. and a pressure between 0.01 and 2 mbar in the chamber; and then bringing said sources into communication with the chamber, which has the effect of vaporizing the liquids at their surface, of drawing them up into the chamber without having to use a carrier gas, and of making them react therein with the dopant so that the oxide layer is formed on the substrate.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: June 24, 2008
    Assignee: Universite de Neuchatel, Institut de Microtechnique
    Inventors: Ulrich Kroll, Johannes Meier
  • Patent number: 7388277
    Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
  • Patent number: 7338824
    Abstract: In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching the first metal layer to form a plurality of gate lines on the substrate, forming a common electrode on the substrate, forming a second metal layer on the substrate, etching the second metal layer to form a first electrode, a second electrode, a common line and a plurality of data lines on the substrate, and forming a pixel electrode overlapping the common electrode, wherein the gate lines intersect the data lines to form at least one enclosed area, the common electrode and the pixel electrode are positioned in the enclosed area, the first electrode is connected to the pixel electrode and the second electrode is connected to the data lines.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: March 4, 2008
    Assignee: HannStar Display Corp.
    Inventor: Po-Sheng Shih
  • Publication number: 20070262312
    Abstract: A thin film transistor array substrate structure. The array substrate structure includes a thin film transistor array substrate, an organic material layer formed thereon, and a plurality of black matrices and color filter patterns disposed on the organic material layer. The invention also provides a method of fabricating the thin film transistor array substrate.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 15, 2007
    Applicant: AU OPTRONICS CORP.
    Inventors: Yu-Wei Liu, Feng-Yuan Gan, Shu-Chin Lee, Yen-Heng Huang
  • Publication number: 20070264844
    Abstract: A method of hiding transparent electrodes on a transparent substrate coats a solution of non-conductive nanoparticles onto the transparent substrate and the transparent electrodes after forming a plurality of transparent electrodes on the transparent substrate, and both non-conductive nanoparticles and transparent electrodes have the same reflective index of light. After a high-temperature thermal processing is performed to the transparent substrate, an even mask is formed on the transparent substrate and the transparent electrodes, such that the non-conductive nanoparticles in the mask provide the same reflective index of light for the positions of the transparent substrate with and without the transparent electrodes, so as to effectively prevent a different reflective index of light at any position of the transparent substrate that will cause a poor image quality of the screen.
    Type: Application
    Filed: August 10, 2006
    Publication date: November 15, 2007
    Applicant: TrendON Touch Technology Corp.
    Inventor: Chun-Min Hu
  • Patent number: 7286195
    Abstract: An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: October 23, 2007
    Assignee: AU Optronics Corp.
    Inventor: Kun-Hong Chen
  • Patent number: 7282430
    Abstract: The present invention provides methods and apparatus for melt-based patterning for electronic devices. It employs and provides processes and apparatus for fabricating an electronic device having a pattern formed on a surface by a deposition material. Further, the invention a process for fabricating semiconductors, organic light-emitting devices (OLEDs), field-effect transistors, and in particular high-resolution patterning for RGB displays. A process for fabricating an organic electronic device includes the steps of heating and applying a pressure to the deposition material to form a melt, and depositing the melted deposition material on the surface with a phase-change printing technique or a spray technique. The melted deposition material solidifies on the surface.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Siegfried F. Karg, Heike E. Riel, Walter H. Riess
  • Patent number: 7279792
    Abstract: According to this invention, a semiconductor device has an upper surface on which an external connection electrode is formed and a lower surface which opposes the upper surface and is in a mirror surface state. A roughened region roughened by laser marking is formed at part of the lower surface. The roughened region includes a product information mark of the semiconductor device itself. The product information mark is printed by laser marking. The number, size, shape, and layout position of the roughened regions are decided to make it possible to, when the lower surface is irradiated with light, read the product information from the difference in light reflectance between the roughened region and mirror-finished region.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: October 9, 2007
    Assignee: Casio Micronics Co., Ltd
    Inventor: Kinichi Naya
  • Patent number: 7229859
    Abstract: Any one of an insulating film forming a TFT, a silicon film and a conductive film is formed by applying a solution and annealing it. In a spin coater (102), a coating solution containing a thin film component which is supplied from a solution storage section (105) is spin-coated onto a substrate. The substrate after coating the coating solution is annealed in an annealing section (103) to form a coating film on the substrate. Additional laser annealing improves one of film characteristics, i.e., crystallinity, density and adhesiveness. Application of the coating solution or a resist by an ink jet process increases utilization of the solution and permits forming a patterned coating film. Because a thin film device in accordance with the present invention is inexpensive and has a high throughput, TFT production by a production system having high utilization of the coating solution drastically reduces initial investment and production cost of a liquid crystal display device.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: June 12, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Ichio Yudasaka, Tatsuya Shimoda, Sadao Kanbe, Wakao Miyazawa
  • Patent number: 7208401
    Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film are described.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: April 24, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Curt Nelson, David Punsalan, Peter S. Nyholm
  • Patent number: 7193249
    Abstract: Provided are a nitride-based light emitting device using a p-type conductive transparent thin film electrode layer and a method of manufacturing the same. The nitride-based light emitting device includes a substrate, and an n-cladding layer, an active layer, a p-cladding layer and an ohmic contact layer sequentially formed on the substrate. The ohmic contact layer is made from a p-type conductive transparent oxide thin film. The nitride-based light emitting device and method of manufacturing the same provide excellent I-V characteristics by improving characteristics of an ohmic contact to a p-cladding layer while enhancing light emission efficiency of the device due to high light transmittance exhibited by a transparent electrode.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: March 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-yeon Seong, June-o Song, Dong-seok Leem
  • Patent number: 7163868
    Abstract: In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the width of the LDD can be defined by the geometry of the inclined planes.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: January 16, 2007
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Te-Ming Chu
  • Patent number: 7132319
    Abstract: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts and electrical interconnection leads may also be substantially transparent. Methods for making and using such double-injection field-effect transistors are also disclosed.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: November 7, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Randy Hoffman
  • Patent number: 7129556
    Abstract: An array substrate for use in an X-ray sensing device is fabricated using an etching stopper that enables good control of the etching process and that prevents over-etch of drain electrodes and second capacitor electrodes while forming contact holes and a cutting furrow. The etching stopper is located in a tiling portion that is utilized for tiling substrates to form a large-sized X-ray detector. During fabrication, gate lines can have gate-protruded portions located near the etching stopper, and the etching stopper can have stopper-protruded portions near the gate lines. The stopper-protruded portions electrically connect to the gate-protruded portions through gate line contact holes such that the etching stopper and the gate lines have equipotentials. This can reduce static electricity damage.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: October 31, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Keuk-Sang Kwon
  • Patent number: 7119411
    Abstract: An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: October 10, 2006
    Assignee: AU Optronics Corp.
    Inventor: Kun-Hong Chen
  • Patent number: 7112458
    Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: September 26, 2006
    Assignee: TPO Displays Corp.
    Inventors: Chu-Jung Shih, Gwo-Long Lin, I-Min Lu
  • Patent number: 7041608
    Abstract: A method of making an electronic device in which a conductive electrode has been formed over a substrate including using a liquid to clean the conductive electrode, heating in a processing station the conductive electrode to a temperature which dries the conductive electrode and thereby removes residual cleaning liquid applied during the cleaning step, and providing an oxidizing plasma in the processing station to modify the properties of the conductive electrode. The method also includes producing a fluorocarbon plasma in the processing station to form a fluorocarbon layer over the modified conductive electrode, and further processing the structure to produce the electronic device.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: May 9, 2006
    Assignee: Eastman Kodak Company
    Inventors: Kurt D. Sieber, Jeremy M. Grace, Michael J. Heinsler, Jeffrey P. Spindler
  • Patent number: 7037766
    Abstract: An active matrix substrate comprises a matrix array of TFTs. A double-layered film includes an under-layer of aluminum-neodymium (Al—Nd) alloy and an over-layer of high melting point metal. The double-layered film forms first interconnection lines for connection to the TFTs. A triple-layered film includes an under-layer of said high melting point metal, a middle-layer of said Al—Nd alloy and an over-layer of the high melting point metal. The triple-layered film forms second interconnection lines for connection to the TFTs.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: May 2, 2006
    Assignee: NEC LCD Technologies, Inc.
    Inventors: Akitoshi Maeda, Hiroaki Tanaka, Shigeru Kimura, Satoshi Kimura
  • Patent number: 7011983
    Abstract: Large, light-weight organic devices and methods of preparing large, light-weight organic devices. Specifically, flexible and rigid light-weight plastics are implemented. The flexible plastic may be disposed from a reel. A metal grid is fabricated on the flexible plastic to provide current conduction over the large area. A transparent oxide layer is provided over the metal grid to form the bottom electrode of the organic device. A light emitting or light gathering organic layer is disposed on the transparent oxide layer. A second electrode is disposed over the organic layer. Electrodes are coupled to the metal grid and the second electrode to provide electrical current to or from the organic layer. Depending on the type of materials used for the organic layer, the organic device may comprise an area light device or a photovoltaic device.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: March 14, 2006
    Assignee: General Electric Company
    Inventors: Donald F. Foust, Anil R. Duggal, Richard J. Saia, Herbert S. Cole