Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.

Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.

Abstract: The present disclosure relates to microstructure devices, in which a conductive pattern is formed on the basis of a conductive polymer material. In order to avoid the deposition and processing of the sacrificial materials and reduce a negative influence of the lithography process on sensitive conductive polymer materials a one-layer patterning sequence is proposed, in which a trench pattern is formed in a dielectric material that is subsequently filled with the conductive polymer material.

Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.

Abstract: A layer of material having a low thermal conductivity is coated over a substrate. A film of conductive ink is then coated over the layer of material having the low thermal conductivity, and then sintered. The film of conductive ink does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity maybe a polymer, such as polyimide.

Abstract: A representative printable composition comprises a liquid or gel suspension of a plurality of metallic particles; a plurality of semiconductor particles; and a first solvent. The pluralities of particles may also be comprised of an alloy of a metal and a semiconductor. The composition may further comprise a second solvent different from the first solvent. In a representative embodiment, the first solvent comprises a polyol or mixtures thereof, such as glycerin, and the second solvent comprises a carboxylic or dicarboxylic acid or mixtures thereof, such as glutaric acid. In various embodiments, the metallic particles and the semiconductor particles are nanoparticles between about 5 nm to about 1.5 microns in any dimension. A representative metallic and semiconductor particle ink can be printed and annealed to produce a conductor.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract: Plating pre-processing is carried out before carrying out a plating process on the surface of a conducting section provided on a semiconductor wafer. A first metal film is formed on the surface of the conducting section by NiP alloy plating process. A second metal film is formed on the surface of the first metal film by immersion Ag plating process. The semiconductor wafer is diced and cut into semiconductor chips. A conductive composition containing Ag particles is applied to the surface of the second metal film which is on the front surface of the semiconductor chip. A bonding layer containing Ag particles is formed by sintering the conductive composition through heating. A metal plate is then bonded to the surface of the second metal film via the bonding layer containing Ag particles. The electronic component has high bonding strength, excellent thermal resistance and heat radiation properties.

Abstract: A production method for producing graphene on a substrate, and the like are provided. According to the method, in a forming step heating is conducted to a solid solution temperature at which a solid solution of carbon dissolved in a metal is able to be formed, and a solid solution layer (505) composed of the solid solution on a substrate (103) is formed; and in a removing step graphene (102) is grown on the substrate (103) by removing the metal from the solid solution layer (505) while maintaining the heating to the solid solution temperature. As a solvent for dissolving carbon a metal composed of a single element as well as various alloys are applicable. The graphene (102) touches directly the substrate (103), by removing the metal from the solid solution layer (505) by supplying an etching gas.

Abstract: An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure.

Abstract: A fabricated substrate has at least one plurality of posts. The plurality is fabricated such that the two posts are located at a predetermined distance from one another. The substrate is exposed to a fluid matrix containing functionalized carbon nanotubes. The functionalized carbon nanotubes preferentially adhere to the plurality of posts rather than the remainder of the substrate. A connection between posts of the at least one plurality of posts is induced by adhering one end of the functionalized nanotube to one post and a second end of the functionalized carbon nanotube to a second post.

Abstract: Certain example embodiments of this invention relate to large-area transparent conductive coatings (TCCs) including carbon nanotubes (CNTs) and nanowire composites, and methods of making the same. The ?dc/?opt ratio of such thin films may be improved via stable chemical doping and/or alloying of CNT-based films. The doping and/or alloying may be implemented in a large area coating system, e.g., on glass and/or other substrates. In certain example embodiments, a CNT film may be deposited and then doped via chemical functionalization and/or alloyed with silver and/or palladium. Both p-type and n-type dopants may be used in different embodiments of this invention. In certain example embodiments, silver and/or other nanowires may be provided, e.g., to further decrease sheet resistance. Certain example embodiments may provide coatings that approach, meet, or exceed 90% visible transmission and 90 ohms/square target metrics.

Abstract: The present invention relates generally to dendritic metal structures and devices including them. The present invention also relates particularly to methods for making dendritic metal structures without the use of solid electrolyte materials. In one aspect, a method for constructing a dendritic metal structure includes providing a substrate having a surface and a cathode disposed on the surface; providing an anode comprising a metal; and disposing a liquid on the surface of the substrate, such that the liquid is in electrical contact with the anode and the cathode; and then applying a bias voltage across the cathode and the anode sufficient to grow the dendritic metal structure extending from the cathode. The methods described herein can be used to grow dedritic metal electrodes, which can be useful in devices such as LEDs, touchscreens, solar cells and photodetectors.

Abstract: Provided are methods for growing large-size, uniform graphene layers on planarized substrates using Chemical Vapor Deposition (CVD) at atmospheric pressure; graphene produced according to these methods may have a single layer content exceeding 95%. Field effect transistors fabricated by the inventive process have room temperature hole mobilities that are a factor of 2-5 larger than those measured for samples grown on commercially-available copper foil substrates.

Abstract: Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse side of the semiconductor chip at positions opposing the bump electrodes. Because the attracting openings do not overlap the joining regions, the bump electrodes (reverse electrodes) are not suctioned at the joining regions.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.

Abstract: A process for depositing a tellurium-containing film on a substrate is disclosed, including (a) providing a substrate in a reactor; (b) introducing into the reactor at least one tellurium-containing precursor having the formula TeLn or cyclic LTe(-L-)2TeL, wherein at least one L contains a N bonded to one said Te, “n” is between 2-6, inclusive, and each “L,” is independently selected from certain alkyl and aryl groups. The process further includes (c) optionally, introducing at least one M-containing source, wherein M is Si, Ge, Sb, Sn, Pb, Bi, In, Ag or Se, or a combination of any of those; (d) optionally, introducing a hydrogen-containing fluid; (e) optionally, introducing an oxygen-containing fluid; (f) optionally, introducing a nitrogen-containing fluid; (g) reacting the precursor(s) and M-containing source(s), if any, in the reactor with the hydrogen-, oxygen- and/or nitrogen-containing fluid, if any; and (h) depositing a tellurium-containing film onto the substrate.

Abstract: A fabricated substrate has at least one plurality of posts. The plurality is fabricated such that the two posts are located at a predetermined distance from one another. The substrate is exposed to a fluid matrix containing functionalized carbon nanotubes. The functionalized carbon nanotubes preferentially adhere to the plurality of posts rather than the remainder of the substrate. A connection between posts of the at least one plurality of posts is induced by adhering one end of the functionalized nanotube to one post and a second end of the functionalized carbon nanotube to a second post.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: A simple process is disclosed for treating substrates having pre-structured zinc oxide layers on rigid or flexible supports. The ZnO is treated with an etching medium then with a cleaning liquid. The treatment with the etching and cleaning liquids is carried out while the substrate is conveyed through a device. The process is technically simple to implement and makes it possible to regularly and homogeneously roughen and texturize ZnO layers of up to 1 m2. The device for treating substrates having pre-structured zinc oxide layers on rigid or flexible supports has for that purpose a first means for treating the substrate with an etching liquid, a second means for treating the substrate with a cleaning liquid, and another means, in particular transport rollers, for conveying the substrate from the first to the second means.

Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract: A semiconductor device includes a metal carrier and a spacer element attached to the metal carrier. The semiconductor device includes a first sintered metal layer on the spacer element and a semiconductor chip on the first sintered metal layer.

Abstract: A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.

Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.

Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).

Abstract: The invention relates to a process for producing electrodes for solar cells, the electrode being configured as an electrically conductive layer on a substrate for solar cells, in which, in a first step, a dispersion comprising electrically conductive particles is transferred from a carrier to the substrate by irradiating the dispersion with a laser and, in a second step, the dispersion transferred to the substrate is dried and/or hardened to form the electrically conductive layer.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.

Abstract: Methods for forming a conductive oxide layer on a substrate are provided. The method can include sputtering a transparent conductive oxide layer (“TCO layer”) on a substrate from a target (e.g., including cadmium stannate) at a sputtering temperature of about 10° C. to about 100° C. The TCO layer can then be annealed in an anneal temperature comprising cadmium at an annealing temperature of about 500° C. to about 700° C. The method of forming the TCO layer can be used in a method for manufacturing a cadmium telluride based thin film photovoltaic device, further including forming a cadmium sulfide layer over the transparent conductive oxide layer and forming a cadmium telluride layer over the cadmium sulfide layer.

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract: There are provided a method of fabricating a thin metal film electrode and a thin metal film electrode fabricated by the same. The method of fabricating a thin metal film electrode according to an embodiment of the present invention includes applying a metal paste including a metal powder and a dispersant to a substrate to form a thin metal film; and subjecting the thin metal film to reduction firing in an atmosphere containing an organic acid and an aqueous solution in a ratio ranging from 10:90 to 90:10.

Abstract: A method for fabricating interconnections with carbon nanotubes of the present invention comprises the following steps: forming a dual-layer that contains a catalytic layer and an upper covering layer on the periphery of a hole connecting with a substrate; and growing carbon nanotubes on the catalytic layer with the upper covering layer covering the carbon nanotubes. The present invention grows the carbon nanotubes between the catalytic layer and the upper covering layer. The upper covering layer protects the catalytic layer from being oxidized and thus enhances the growth of the carbon nanotubes. The carbon nanotubes are respectively connected with the lower substrate and an upper conductive wire via the catalytic layer and the upper covering layer, which results in a lower contact resistance. Moreover, the upper covering layer also functions as a metal-diffusion barrier layer to prevent metal from spreading to other materials via diffusion or other approaches.

Abstract: Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the composite, where the channel forms a primary conduction path for the device. Upon applied voltage, capacitive actuators squeeze the composite, causing it to become conductive. The squishable device includes a control electrode, and a composite electrically and mechanically connected to two terminal electrodes. By applying a voltage to the control electrode relative to a first terminal electrode, an electric field is developed between the control electrode and the first terminal electrode. This electric field results in an attractive force between the control electrode and the first terminal electrode, which compresses the composite and enables electric control of the electron conduction from the first terminal electrode through the channel to the second terminal electrode.

Abstract: A method for making electrical interconnections of carbon nanotubes, including a) depositing an ionic liquid including nanoparticles of at least one suspended electrically conducting material, covering at least one surface of an element configured to be used as a support for carbon nanotubes, b) forming a deposit of the nanoparticles at least against the surface of the element, c) removing the remaining ionic liquid, d) growing carbon nanotubes from the deposited nanoparticles, and further including between the c) removing the remaining ionic liquid and the d) growing carbon nanotubes, passivating the deposited nanoparticles not found against the surface of the element.

Abstract: A method for fabricating electrical bonding pads on the electrical contact areas of a wafer includes producing first blocks made of a solder material, producing second blocks made of a solder material on these first blocks, and passing the blocks through an oven so as to shape the blocks into approximately domed electrical bonding pads.

Abstract: The present disclosure relates to the field of fabricating microelectronic devices, wherein a conductive adhesive is used as a temporary microelectronic wafer bonding adhesive to prevent damage to microelectronic devices resulting from electrical charge build-up on the microelectronic devices during the formation of through-silicon vias.

Abstract: In the bundle of long thin carbon structures of the present invention, end parts of the bundle are interconnected in a carbon network. The interconnected end parts form a flat surface. By this, an electrical connection structure with low resistance and/or a thermal connection structure with high thermal conductivity are obtained. The bundle of long thin carbon structures can be used suitably as a via, heat removal bump or other electronic element.

Abstract: An aggregate structure of carbon fibers, organized by a plurality of carbon fibers, includes, an aggregate of the carbon fibers aligned in a lengthwise direction, in which a density of the carbon fibers at one side end is different from a density of the carbon fibers at the other side end.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.

Abstract: In one exemplary embodiment, a method for fabricating a nanowire product comprising: providing a wafer having a buried oxide (BOX) upper layer in which a well is formed, the wafer further having a nanowire having ends resting on the BOX layer such that the nanowire forms a beam spanning said well; and forming a mask coating on an upper surface of the BOX layer leaving an uncoated window over a center part of said beam over said well and also forming a mask coating around beam intermediate ends between each end of a beam center part and a side wall of said well.

Abstract: Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.

Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A method for manufacturing a semiconductor device includes forming an electrode pad in a surface layer of an insulating layer; disposing a conductive particle, of which at least a portion of the surface is coated with a thermoplastic resin, over the electrode pad; and fixing the conductive particle over the electrode pad using the resin, by heating the resin to soften the resin, and then cooling and solidifying the resin after the conductive particle and the electrode pad are electrically connected to each other, to form the conductive particle as an external connection terminal.