Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents (Class 438/618)
  • Patent number: 9640388
    Abstract: In a method for forming a fluorocarbon-based insulating film to be in contact with a metal, a microwave is irradiated to the metal to which moisture is adhered in a hydrogen-containing atmosphere. Then plasma CVD using a fluorocarbon-based gas is performed on the metal to which the microwave is irradiated to form the insulating film.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 2, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Kasai, Kotaro Miyatani, Takuya Kurotori, Kenichi Kote, Yutaka Fujino, Akira Tanihara, Kohei Kawamura
  • Patent number: 9633897
    Abstract: The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Patent number: 9570389
    Abstract: An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner layers. Each interconnect line is positioned within a trench. At least one first liner layer is affixed between the trench bottom surface and the interconnect bottom surface. The interconnect structure further includes one or more second liner layers. At least one of the second liner layers is affixed directly to the interconnect top surface and at least one interconnect side surface. The interconnect structure further includes at least one air gap. Each air gap is positioned between the trench side surface and the interconnect side surface. A corresponding method of manufacture and product of a method of manufacture are also disclosed.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dinesh A. Badami, Baozhen Li, Wen Liu, Chih-Chao Yang
  • Patent number: 9564404
    Abstract: Systems and methods for forming semiconductor wafers with wafer support structures includes: multiple semiconductor devices formed in multiple semiconductor dies. An electrical interconnect structure is formed over the semiconductor devices and providing electrical connections to the semiconductor devices. The electrical interconnect structure includes multiple metallization layers. At least one portion of at least one metallization layer includes variations in density of conductive lines or conducting devices as compared to the other portions of the metallization layers. At least one wafer support structure is formed substantially across a width of the semiconductor wafer. The semiconductor wafer being thinned to between about 40 um and about 200 um after the semiconductor devices formed thereon.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 7, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Manuel A. d'Abreu
  • Patent number: 9564328
    Abstract: The method for fabricating patterns made from first material having: providing a substrate covered by a covering layer, forming a first mask by means of a self-assembled structure of block copolymers, the first mask having first patterns, making a second mask from the first mask, the second mask having a second series of patterns organized according to the first repetition pitch or an integral multiple of the first repetition pitch, the second series having less patterns than the first series, depositing and exposing a resin layer to form an intermediate mask on the first mask, the intermediate mask covering a part of the first patterns formed in the first mask and having second holes facing the first holes, etching the covering layer through the facing first and second holes to form third holes, filling the third holes with a first material to form the patterns made from first material.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 7, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jérôme Belledent
  • Patent number: 9553047
    Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: January 24, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Min Hung, Tzung-Ting Han, Miao-Chih Hsu
  • Patent number: 9553049
    Abstract: Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: January 24, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Kezia Cheng
  • Patent number: 9536753
    Abstract: A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: January 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yohei Koto, Kazunori Hayata, Dan Okamoto
  • Patent number: 9514979
    Abstract: A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
  • Patent number: 9514938
    Abstract: According to one embodiment, a method of forming a pattern includes applying a polymer material having a first segment and a second segment in openings formed in a guide, heating the polymer material to achieve microphase separation of the polymer material to form a self-assembled pattern which includes a first polymer portion having a cylindrical shape which includes the first segment, and a second polymer portion including the second segment and surrounding a lateral portion of the first polymer portion, and selectively removing the first polymer portion. A molecular weight ratio of the first segment to the second segment in the polymer material is approximately 4:6.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hironobu Sato
  • Patent number: 9514981
    Abstract: An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner layers. Each interconnect line is positioned within a trench. At least one first liner layer is affixed between the trench bottom surface and the interconnect bottom surface. The interconnect structure further includes one or more second liner layers. At least one of the second liner layers is affixed directly to the interconnect top surface and at least one interconnect side surface. The interconnect structure further includes at least one air gap. Each air gap is positioned between the trench side surface and the interconnect side surface. A corresponding method of manufacture and product of a method of manufacture are also disclosed.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dinesh A. Badami, Baozhen Li, Wen Liu, Chih-Chao Yang
  • Patent number: 9472499
    Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9472506
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Patent number: 9472495
    Abstract: Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed. The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: October 18, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Yukio Maki
  • Patent number: 9466579
    Abstract: The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing element having at least one integrated anchor-like part, is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 11, 2016
    Assignee: NXP B.V.
    Inventors: Hendrik Pieter Hochstenbach, Willem Dirk Van Driel
  • Patent number: 9449928
    Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Gudrun Stranzl
  • Patent number: 9437443
    Abstract: A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Markus Brink, Michael A. Guillorn, Sebastian U. Engelmann, Hiroyuki Miyazoe, Adam M. Pyzyna, Jeffrey W. Sleight
  • Patent number: 9437638
    Abstract: There is disclosed a substrate including at least one photodetector, the photodetector having a first active area on a first surface of the substrate and a second active area on a second surface of the substrate, wherein the photodetector is provided with a conductive via electrically isolated from the substrate, said conductive via extending through the photodetector from the first surface of the substrate to the second surface of the substrate for connecting the first active area to the second surface of the substrate, the second surface providing electrical connections for the first and second active areas of the photodetector.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: September 6, 2016
    Assignee: Detection Technology Oy
    Inventors: Fan Ji, Mikko Juntunen, Iiro Hietanen
  • Patent number: 9428835
    Abstract: A present invention provide a technique for easily forming a high-quality cobalt base film, which have a small specific resistance. The present invention comprises a transportation process of a Co[i-C3H7NC(C2H5)N-i-C3H7]2, and a film formation process by decomposition of the Co[i-C3H7NC(C2H5)N-i-C3H7]2. The film formation process comprises at least a first film formation process and a second film formation process. In the first film formation process, a film formation chamber is supplied with at least NH3 and/or NH3 product compound, and is not virtually supplied with H2. In the second film formation process, the film formation chamber is supplied with at least NH3 and/or NH3 product compound, and H2. An internal pressure of the film formation chamber in the first film formation process is higher than an internal pressure of the film formation chamber in the second film formation process.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 30, 2016
    Assignees: GAS-PHASE GROWTH LTD., Tokyo Electron Limited
    Inventors: Hideaki Machida, Masato Ishikawa, Hiroshi Sudoh, Yumiko Kawano, Kazutoshi Iwai
  • Patent number: 9425097
    Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
  • Patent number: 9418968
    Abstract: A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sensho Usami, Koji Hosokawa
  • Patent number: 9412648
    Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
  • Patent number: 9396988
    Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Woo Lee, Woo-Jin Lee, Jong-Sam Kim, Woo-Kyung You, Young-Sang Lee, Min Huh
  • Patent number: 9383404
    Abstract: A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, Eric D. Johnson, Ian A. McCallum-Cook, Richard A. Phelps, Anthony K. Stamper, Michael J. Zierak
  • Patent number: 9385068
    Abstract: A method is provided of forming an interconnect structure. The method comprises forming a first dielectric layer overlying a first conductive layer, etching a trench opening in the first dielectric layer, depositing a sacrificial material layer in the trench opening, and forming a second conductive layer overlying the sacrificial layer. The method also comprises forming a via to the sacrificial layer, and performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer decreasing the effective dielectric constant between the first and second conductive layers.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: July 5, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Thomas J. Knight
  • Patent number: 9379001
    Abstract: A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns. The semiconductor device includes insulating fences electrically isolating the conductive patterns from each other and having chamfered corners. The semiconductor device includes insulating patterns filling gaps between side surfaces of the line patterns and the chamfered corners of the insulating fences.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonggyu Choi, Dong-hyun Kim, Yongchul Oh, Kichul Nam
  • Patent number: 9362135
    Abstract: A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a surface and a rising surface that protrudes upward from the surface, on a semiconductor substrate; forming a conductive layer to cover the insulation layer having the protruding portion; and removing a predetermined region of the conductive layer by patterning the predetermined region according to an etching process using microwave plasma, which uses a microwave as a plasma source, while applying bias power of 70 mW/cm2 or above on the semiconductor substrate, under a high pressure condition of 85 mTorr or above.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: June 7, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tetsuya Nishizuka, Masahiko Takahashi
  • Patent number: 9358753
    Abstract: Substrates and methods of forming a pattern on a substrate. The pattern includes a repeating pattern region and a pattern-interrupting region adjacent to the repeating pattern region. A mask is formed on the substrate, with the mask including the repeating pattern region and the pattern-interrupting region and which are formed using two separate masking steps. The mask is used in forming the pattern into underlying substrate material on which the mask is received. Substrates comprising masks are also disclosed.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 7, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, David A. Kewley, Kyle Armstrong, Michael Dean Van Patten, Michael D. Hyatt
  • Patent number: 9349679
    Abstract: A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: May 24, 2016
    Assignee: UTAC THAI LIMITED
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 9341670
    Abstract: A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Philip R. Germann, Mark O. Maxson
  • Patent number: 9335596
    Abstract: Embodiments of the present invention disclose an array substrate, a display device and a repair method of the array substrate. The array substrate comprises a display region; a peripheral region, in which a peripheral circuit including a plurality of leading wires is provided, and the peripheral region including: an insulation layer, provided above a layer in which the peripheral circuit is provided; and a leading wire repair layer, provided above the insulation layer, wherein the leading wire repair layer includes at least two common repair lines extended along an arrangement direction of the leading wires in the peripheral circuit, and a plurality of repair lines electrically connected the at least two common repair lines are provided between the two adjacent common repair lines.
    Type: Grant
    Filed: December 14, 2013
    Date of Patent: May 10, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Pijian Jia, Woong Sun Yoon, Zhaohui Hao
  • Patent number: 9305835
    Abstract: Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Viraj Sardesai, Cung Tran, Reinaldo Vega
  • Patent number: 9299660
    Abstract: A process of bumping a die backside includes opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, followed by filling the recess with a conductive material that contacts the TSV contact. Added solder is coupled to the conductive material at a level of the DBF. A subsequent die is coupled to the first die at the added solder to form an electrical coupling consisting of the TSV contact, the conductive material, and the added solder, an electrical bump coupled to the subsequent die. Apparatus and computer systems are assembled using the process.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 29, 2016
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Shan Zhong
  • Patent number: 9293367
    Abstract: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: March 22, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Marc Sulfridge
  • Patent number: 9293365
    Abstract: The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer, Jim Shih-Chun Liang, Joyeeta Nag, Wei-tsu Tseng, George S. Tulevski
  • Patent number: 9293363
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 9293412
    Abstract: A structure including a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions, a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions, and a metal via comprising a palladium liner extends vertically and electrically connects the first metal line with the second metal line, the via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9293360
    Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jung Il Cho, Jong Moo Choi, Eun Joo Jung
  • Patent number: 9281288
    Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Chun-Cheng Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9269809
    Abstract: When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Marco Lepper, Katrin Reiche
  • Patent number: 9257636
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9249013
    Abstract: Compositions for directed self-assembly patterning techniques are provided which avoid the need for separate anti-reflective coatings and brush neutral layers in the process. Methods for directed self-assembly are also provided in which a self-assembling material, such as a directed self-assembly block copolymer, can be applied directly to the silicon hardmask neutral layer and then self-assembled to form the desired pattern. Directed self-assembly patterned structures are also disclosed herein.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: February 2, 2016
    Assignee: Brewer Science Inc.
    Inventors: Yubao Wang, Mary Ann Hockey, Douglas J. Guerrero, Vandana Krishnamurthy, Robert C. Cox
  • Patent number: 9236300
    Abstract: A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 9232638
    Abstract: A printed wiring board includes a core substrate including resin and inorganic fiber, a first buildup layer formed on a first surface of the substrate and including resin insulating layers and first conductive layers, and a second buildup layer formed on a second surface of the substrate on the opposite side of the core substrate with respect to the first surface and including resin insulating layers and second conductive layers. The first conductive layers in the first buildup have sum V1 of volumes which is greater than sum V2 of volumes of the second conductive layers in the second buildup, and the substrate has a first-surface side portion which has resin amount greater than resin amount of a second-surface side portion of the substrate where boundary between the first-surface and second-surface side portions is set with respect to the center line in the thickness direction of the substrate.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 5, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Hisashi Kato, Ryojiro Tominaga, Tetsuya Nobutoki
  • Patent number: 9196548
    Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Srikanth Samavedam, David Doman, Navneet Jain, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 9190238
    Abstract: A blanking device for multi-charged particle beams includes plural shift registers arranged in two dimensions, and plural data transmitters each configured to be arranged, where each of first shift register groups is aligned in the same row or column, in the plural shift registers arranged in two dimensions, the plural data transmitters each arranged for each of second shift register groups each obtained by grouping shift registers of one of the first shift register groups into one or more groups, wherein each of the second shift register groups is further grouped into third shift register groups each having shift registers serially connected, as plural subgroups, and each of the plural data transmitters is connected to shift registers configuring a part of shift registers serially connected in each of the third shift register groups such that all of the plural subgroups in a corresponding second shift register group are parallelly connected.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: November 17, 2015
    Assignee: NuFlare Technology, Inc.
    Inventor: Hiroshi Matsumoto
  • Patent number: 9177981
    Abstract: Disclosed herein is a solid-state imaging device including: a sensor element having a plurality of pixels each having a photoelectric conversion section; and a logic element attached to the sensor element in such a manner as to be stacked on the sensor element face-to-face and provided with a pad electrode. In a stacked body of the sensor and logic elements, a pad opening is provided above the top surface of the pad electrode facing the sensor element, and a pad periphery guard ring is provided to surround the side portion of the pad opening. The pad periphery guard ring is formed by integrally filling, on the side of the pad opening, an entire trench that is at least as deep as the pad opening with a metal material.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: November 3, 2015
    Assignee: Sony Corporation
    Inventor: Kenichi Nishizawa
  • Patent number: 9165885
    Abstract: An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a first polymer via. A first redistribution layer is disposed on the first polymer layer and within the first polymer via. The first redistribution layer is electrically coupled to the metal via. A second polymer layer is disposed on the first redistribution layer. The second polymer layer has a second polymer via laterally offset from the first polymer via. A second redistribution layer is disposed on the second polymer layer and within the second polymer via. The second redistribution layer is electrically coupled to the first redistribution layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo
  • Patent number: 9153480
    Abstract: An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 6, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 9153487
    Abstract: A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate, except on the first wire; forming a surface treatment film on the material layer; and forming a second wire on the first wire. The surface treatment film has physical properties opposite to the first wire. A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate and the first wire; removing a portion of the material layer from the first wire; forming a surface treatment film on the material layer and the first wire; removing a portion of the surface treatment film from the first wire; and forming a second wire on the first wire. A thickness of the material layer on the substrate is greater than a thickness of the first wire on the substrate.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 6, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-ho Lee, Young-ki Hong, Sung-gyu Kang, Joong-hyuk Kim, Jae-woo Chung