Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents (Class 438/618)
  • Patent number: 8980708
    Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: March 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: John J. Zhu, Bin Yang, P R Chidambaram, Lixin Ge, Jihong Choi
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8975178
    Abstract: According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Kikutani, Satoshi Nagashima, Hidefumi Mukai, Takehiro Kondoh, Hisataka Meguro
  • Patent number: 8975116
    Abstract: An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignees: Technische Universität Berlin, Fraunhofer-Gesellschaft zur Foerderung der angewandt Forschung e.V.
    Inventors: Andreas Ostmann, Dionysios Manessis, Lars Böttcher, Stefan Karaszkiewicz
  • Patent number: 8975147
    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hanhong Chen, Pragati Kumar, Sandra G. Malhotra
  • Publication number: 20150061132
    Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.
    Type: Application
    Filed: November 4, 2014
    Publication date: March 5, 2015
    Inventors: Sok-Won LEE, Joon-Hee LEE, Jung-Dal CHOI, Seong-Min JO
  • Publication number: 20150061143
    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.
    Type: Application
    Filed: June 27, 2014
    Publication date: March 5, 2015
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Omar James Bchir
  • Publication number: 20150055414
    Abstract: A structure of a memory device and a method for making the memory device structure are described. The memory device includes an array of memory cells in an array level die. The array comprises a plurality of sub-arrays. Each of the sub-arrays comprises respective data lines. The memory device also includes page buffers for corresponding sub-arrays in a page-buffer level die. The memory device also includes inter-die connections that are configured to electrically couple the page buffers in the page-buffer level die to data lines of corresponding sub-arrays in the array level die.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: SHIH-HUNG CHEN
  • Patent number: 8962482
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Patent number: 8959764
    Abstract: A structure and method for manufacturing the same for manufacturing a contact structure for microelectronics manufacturing including the steps of forming first and second metal sheets to form a plurality of outwardly extending bump each defining a cavity. Symmetrically mating the first and second metal sheets in opposing relation to each other to form upper and lower bumps each defining an enclosure therebetween wherein the mated first and second sheets form a contact structure. Coating the contact structure with an insulating material, and fabricating helix shaped contacts from upper and lower bumps. The helix shaped contacts having first and second portions being in mirror image relationship to each other.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gareth Hougham, Gerard McVicker, Xiaoxiong Gu
  • Patent number: 8963342
    Abstract: Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging types for an integrated circuit. The structure generally comprises a bump pad, a plurality of bond pads configured for independent electrical connection to the bump pad, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the bump pad. The method of configuring generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. The method of selecting generally comprises the uppermost metal layer-forming step, and forming either (i) a wire bond to at least one of the bond pads, or (ii) a bumping metal configured to electrically connect at least one of the bond pads to the bump pad.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Marvell International Ltd.
    Inventors: Tyson Leistiko, Huahung Kao
  • Patent number: 8963328
    Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Chang-Pin Huang, Tzuan-Horng Liu, Michael Shou-Ming Tong, Ying-Ju Chen, Tung-Liang Shao, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
  • Publication number: 20150050804
    Abstract: Methods for manufacturing the grating sheet and a liquid crystal display panel are provided. The grating sheet comprises a plurality of primary color gratings in parallel, each of which comprises a red R sub-grating, a green G sub-grating and a blue B sub-grating in parallel, and each sub-grating comprises an opening area and a reflective region disposed around the opening area and corresponds to a pixel unit on a sub-array substrate. The methods for manufacturing the grating sheet and a liquid crystal display panel may be applicable to a system with a liquid crystal display.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Inventor: Linlin LU
  • Publication number: 20150044865
    Abstract: A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Chii-Ping CHEN, Chih-Hao CHEN
  • Publication number: 20150041986
    Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
    Type: Application
    Filed: September 22, 2014
    Publication date: February 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kosuke YANAGIDAIRA, Chikaaki KODAMA
  • Patent number: 8951906
    Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Publication number: 20150037972
    Abstract: Described are cleaning methods for removing contaminants from an electrical contact interface of a partially fabricated semiconductor substrate. The methods may include introducing a halogen-containing species into a processing chamber, and forming an adsorption-limited layer, which includes halogen from the halogen-containing species, atop the electrical contact interface and/or the contaminants thereon. The methods may further include thereafter removing un-adsorbed halogen-containing species from the processing chamber and activating a reaction between the halogen of the adsorption-limited layer and the contaminants present on the electrical contact interface. The reaction may then result in the removal of at least a portion of the contaminants from the electrical contact interface. In some embodiments, the halogen adsorbed onto the surface and reacted may be fluorine. Also described herein are apparatuses having controllers for implementing such electrical contact interface cleaning techniques.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventors: Michal Danek, Juwen Gao, Aaron Fellis, Francisco Juarez, Chiukin Steven Lai
  • Publication number: 20150035166
    Abstract: A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. The mold compound is separated to form singulated semiconductor components. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion using one of a vibratory plating device or a spouted bed electroplating device.
    Type: Application
    Filed: January 30, 2014
    Publication date: February 5, 2015
    Inventors: James P. Letterman, JR., Phillip Celaya, Robert L. Marquis
  • Publication number: 20150035150
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Patent number: 8946912
    Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 3, 2015
    Assignee: Intersil Americas LLC
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Publication number: 20150031201
    Abstract: A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.
    Type: Application
    Filed: October 13, 2014
    Publication date: January 29, 2015
    Inventors: Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yongan Xu, Yunpeng Yin
  • Patent number: 8940631
    Abstract: Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Albert Bergemont
  • Patent number: 8941090
    Abstract: A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sung Min Lee
  • Publication number: 20150024546
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20150024587
    Abstract: A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern.
    Type: Application
    Filed: May 14, 2014
    Publication date: January 22, 2015
    Inventors: Kyoungmi Kim, Myung-Sun Kim, Jaeho Kim, Hyounghee Kim, Namuk Choi, Jungsik Choi
  • Patent number: 8936960
    Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuan-Yu Wang, Hui-Min Wu, Kun-Che Hsieh
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter
  • Publication number: 20150014859
    Abstract: An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric loss of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, which reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be fabricated using today's standard IC fabrication techniques.
    Type: Application
    Filed: May 3, 2014
    Publication date: January 15, 2015
    Applicant: BANPIL PHOTONICS, INC.
    Inventor: ACHYUT KUMAR DUTTA
  • Patent number: 8927345
    Abstract: A method comprises fabricating an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure and coupling each of the conductive interconnects to a corresponding bond pad of a package substrate and bond pad of a die. A device package comprises a substrate having a first plurality of bond pads disposed at a first surface of the substrate and a die having a first surface facing the first surface of the substrate and a second surface opposite the first surface, the die comprising a second plurality of bond pads disposed at the second surface. The device package further comprises an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure, each of the conductive interconnects coupled to a corresponding bond pad of the first plurality of bond pads and to a corresponding bond pad of the second plurality of bond pads.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng Foong Yap, Lai Cheng Law, Boh Kid Wong
  • Patent number: 8927416
    Abstract: A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeshi Harada, Junichi Shibata, Akira Ueki
  • Patent number: 8927420
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Publication number: 20150001728
    Abstract: A method of forming a semiconductor device, the method includes performing, in a first module, a remote plasma treatment on a wafer to remove an oxide layer from the wafer by a reduction reaction. The method further includes transferring the pre-treated wafer from the first module to a second module under a vacuum. The method further includes forming, in the second module, an etch stop layer over the wafer.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventors: Li CHEN, Jyh-Nan LIN, Chin-Feng SUN, Po-Hsiung LEU, Ding-I LIU
  • Publication number: 20140374915
    Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventor: Errol T. RYAN
  • Publication number: 20140375341
    Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jason R. Fender, Ngai Ming Lau
  • Publication number: 20140374832
    Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Gwo-Chyuan Kuoh, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien, Yen-Ming Peng
  • Publication number: 20140371110
    Abstract: A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured ASIC formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured ASIC connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.
    Type: Application
    Filed: May 21, 2014
    Publication date: December 18, 2014
    Inventors: Pieter Van Rooyen, Robert J. McMillen, Michael Ruehle
  • Publication number: 20140367835
    Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: Ming-Te Wei, Po-Chao Tsao, Ching-Li Yang, Chien-Yang Chen, Hui-Ling Chen, Guan-Kai Huang
  • Patent number: 8912088
    Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masaaki Kurita, Takashi Nishimori, Yukio Kanehira
  • Patent number: 8912060
    Abstract: A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Uenaka, Kazuyuki Higashi
  • Patent number: 8912540
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 16, 2014
    Assignee: Renesas Electronics Corporations
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Publication number: 20140363970
    Abstract: A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Chien Ling HWANG, Yi-Wen WU, Chun-Chieh WANG, Chung-Shi LIU
  • Publication number: 20140361399
    Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: XIAOYING MENG, QIUHUA HAN
  • Patent number: 8906799
    Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Wai-Kin Li, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8906800
    Abstract: An apparatus includes a device package, a first Integrated Circuit (IC) that is packaged in the device package, and a second IC, which is packaged in the device package and is fabricated on a multi-layer interconnection circuit including a plurality of interconnection layers for interconnecting components of the second IC, wherein a selected layer in the plurality is configured to serve as a conductive shield for reducing interference between the first and second ICs.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: December 9, 2014
    Assignee: Siano Mobile Silicon Ltd.
    Inventor: Neil David Feldman
  • Patent number: 8906757
    Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeong-Cheol Kim, Il-Sup Kim, Cheol Kim, Jong-Chan Shin, Jong-Wook Lee, Choong-Ho Lee, Si-Young Choi, Jong-Seo Hong
  • Patent number: 8900996
    Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
  • Patent number: 8901744
    Abstract: A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, III, Shom Ponoth
  • Publication number: 20140346662
    Abstract: Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mahbub RASHED, Lei YUAN
  • Patent number: 8896120
    Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta