Including Organic Insulating Material Between Metal Levels Patents (Class 438/623)
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Patent number: 8084355Abstract: A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line trenches are formed into the damascene material. Copper-comprising material is electrochemically deposited over the damascene material. The copper-comprising material is removed and the damascene material is exposed, and individual copper-comprising conductive lines are formed within individual of the line trenches. The damascene material is removed selectively relative to the conductive copper-comprising material. Dielectric material is deposited laterally between adjacent of the individual copper-comprising conductive lines. The deposited dielectric material is received against sidewalls of the individual copper-comprising conductive lines. A void is received laterally between immediately adjacent of the individual copper-comprising conductive lines within the deposited dielectric material. Other embodiments are contemplated.Type: GrantFiled: April 19, 2010Date of Patent: December 27, 2011Assignee: Micron Technology, Inc.Inventor: Zailong Bian
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Patent number: 8084294Abstract: An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas.Type: GrantFiled: February 14, 2006Date of Patent: December 27, 2011Assignee: NEC CorporationInventors: Munehiro Tada, Tsuneo Takeuchi, Yoshihiro Hayashi
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Publication number: 20110312177Abstract: The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate, said inorganic antireflective coating is vapor deposited and comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; forming at least one interconnect pattern within the at least one patternable low-k material; and curing the at least one patternable low-k material.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: International Business Machines CorporationInventors: Qinghuang Lin, Deborah A. Neumayer
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Publication number: 20110304053Abstract: An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.Type: ApplicationFiled: June 11, 2010Publication date: December 15, 2011Applicant: International Business Machines Corp.Inventors: Qinghuang Lin, Dirk Pfeiffer, Ratnam Sooriyakumaran
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Patent number: 8071473Abstract: An object of the present invention is to obtain a favorable etching shape in etching an organic film formed on a substrate. A semiconductor device manufacturing method according to the present invention comprises the steps of: etching with plasma a silicon-containing film and transferring a pattern of a pattern mask stacked on the silicon-containing film onto the silicon-containing film to form a patterned silicon-containing film; removing the pattern mask using plasma to expose the surface of the silicon-containing film; and etching the surface of the organic film through the patterned silicon-containing film by use of oxygen active species in plasma to form a concave portion on the organic film. Thereafter, the silicon-containing film is sputtered to form silicon-containing protection films on the inner wall surfaces of the concave portion. The concave portion is further etched in its depth direction through the patterned silicon-containing film by use of oxygen active species in plasma.Type: GrantFiled: August 13, 2008Date of Patent: December 6, 2011Assignee: Tokyo Electron LimitedInventors: Kazuki Narishige, Koichi Nagakura
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Patent number: 8067309Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: GrantFiled: September 26, 2008Date of Patent: November 29, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Patent number: 8062973Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: GrantFiled: January 25, 2010Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Patent number: 8053356Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.Type: GrantFiled: October 12, 2010Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8043957Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.Type: GrantFiled: May 16, 2007Date of Patent: October 25, 2011Assignee: NEC CorporationInventors: Munehiro Tada, Hiroto Ohtake, Fuminori Ito, Yoshihiro Hayashi, Hironori Yamamoto
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Patent number: 8034664Abstract: Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer.Type: GrantFiled: October 28, 2010Date of Patent: October 11, 2011Assignee: Wavenics Inc.Inventors: Young-Se Kwon, Kyoung Min Kim
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Patent number: 8026164Abstract: A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming a conductive material over the organic insulating film and in the recesses, and removing the conductive material on the organic insulating film by a polishing to expose the surface of the organic insulating film and to leave the conductive material buried in recesses of the organic insulating film.Type: GrantFiled: October 21, 2009Date of Patent: September 27, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Takesako, Shinichi Akiyama, Tamotsu Owada
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Patent number: 8026184Abstract: Disclosed is a method of manufacturing a semiconductor device formed by laminating a capacitor including a bottom metal electrode, a capacitive insulating film, and an upper metal electrode. When the capacitive insulating film is formed by performing a first step of forming a first dielectric layer on the bottom metal electrode by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric; and a second step of forming a second dielectric layer on the first dielectric layer by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric, a film forming temperature in the first step is set so as to be lower than a film forming temperature in the second step.Type: GrantFiled: December 28, 2007Date of Patent: September 27, 2011Assignee: Elpida Memory, Inc.Inventor: Mitsuhiro Horikawa
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Patent number: 8021975Abstract: A plasma processing method for forming a film on a substrate using a gas processed by a plasma. The plasma processing method for forming a film includes the steps of forming a CF film on the substrate by using a CaFb gas (here, a is a counting number, and b is a counting number which satisfies an equation of “b=2×a?2”), processing the CF film with the gas processed by the plasma, and forming an insulating film on the CF film processed by using an insulating material processed with the plasma.Type: GrantFiled: December 28, 2007Date of Patent: September 20, 2011Assignee: Tokyo Electron LimitedInventors: Kotaro Miyatani, Kohei Kawamura, Toshihisa Nozawa, Takaaki Matsuoka
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Patent number: 8008730Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.Type: GrantFiled: July 13, 2009Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Shoichi Fukui, Noboru Morimoto, Yasutaka Nishioka, Junko Izumitani, Atsushi Ishii
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Patent number: 8008186Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under the wiring, in which a surface layer of the first insulating film lying in a boundary surface between the first insulating film and the second insulating film is chemically modified to reinforce the surface layer.Type: GrantFiled: March 8, 2010Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazumichi Tsumura, Masaki Yamada
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Patent number: 8008127Abstract: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad.Type: GrantFiled: October 17, 2008Date of Patent: August 30, 2011Assignee: Yamaha CorporationInventor: Hiroshi Naito
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Patent number: 8003513Abstract: A multilayer circuit includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by electroplating techniques. Substrates formed in this manner enable significant increases in circuit pattern miniaturization, circuit pattern reliability, interconnect density and significant reduction of over-all substrate thickness.Type: GrantFiled: March 22, 2005Date of Patent: August 23, 2011Assignee: Medtronic Minimed, Inc.Inventors: Rajiv Shah, Shaun Pendo
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Patent number: 7998873Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.Type: GrantFiled: June 15, 2007Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
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Patent number: 7998856Abstract: Leakage, capacitance and reliability degradation of interconnects fabricated in low-k dielectric materials, particularly porous low-k dielectric material, due to penetration by a barrier metal and/or barrier metal precursor during damascene processing is prevented by depositing a conformal, heat stable dielectric sealant layer on sidewalls of the low-k dielectric material defining the damascene opening. Embodiments include forming a dual damascene opening in a porous, low-k organosilicate layer, the organosilicate having a pendant silanol functional group, depositing a siloxane polymer having a silylating functional group which bonds with the pendant silanol group to form the sealant layer, depositing a Ta and/or TaN barrier metal layer by CVD or ALD and filling the opening with Cu or a Cu alloy.Type: GrantFiled: May 27, 2005Date of Patent: August 16, 2011Assignee: Advanced Micro Devices, Inc.Inventor: E. Todd Ryan
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Patent number: 7981790Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: GrantFiled: January 7, 2010Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Patent number: 7964969Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.Type: GrantFiled: October 28, 2009Date of Patent: June 21, 2011Assignee: Panasonic CorporationInventor: Takeshi Harada
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Patent number: 7960294Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.Type: GrantFiled: July 21, 2009Date of Patent: June 14, 2011Assignee: Applied Materials, Inc.Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
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Patent number: 7952188Abstract: A module is described having a semiconductor chip which has at least one contact pad. A first dielectric layer, which contains a fluorocarbon compound, as well as a first wiring layer are applied to the semiconductor chip.Type: GrantFiled: January 8, 2007Date of Patent: May 31, 2011Assignee: Infineon Technologies AGInventors: Markus Brunnbauer, Joachim Mahler, Manfred Mengel
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Patent number: 7947978Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: GrantFiled: December 5, 2006Date of Patent: May 24, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen
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Patent number: 7939446Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.Type: GrantFiled: November 11, 2009Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Anthony D. Lisi, Satya V. Nitta
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Patent number: 7932175Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.Type: GrantFiled: May 29, 2007Date of Patent: April 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Ritwik Chatterjee, Eddie Acosta, Sam S. Garcia, Varughese Mathew
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Patent number: 7932172Abstract: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.Type: GrantFiled: November 19, 2008Date of Patent: April 26, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
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Patent number: 7928000Abstract: A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures. Each of the chips has conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures. The method then applies a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass. A step of cleaning the exposed portion of silicon nitride using an isotropic component is also included.Type: GrantFiled: April 5, 2007Date of Patent: April 19, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Jin Kang, Mingching Wang
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Patent number: 7923366Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: September 17, 2007Date of Patent: April 12, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Patent number: 7915157Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: February 2, 2008Date of Patent: March 29, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7915159Abstract: A treating agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent which may be an acid, a base, an onium compound, a dehydrating agent, and combinations thereof, and a solvent or mixture of a main solvent and a co-solvent.Type: GrantFiled: August 12, 2005Date of Patent: March 29, 2011Assignee: Honeywell International Inc.Inventors: Anil S. Bhanap, Boris A. Korolev, Roger Y. Leung, Beth C. Munoz
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Patent number: 7915160Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.Type: GrantFiled: January 19, 2007Date of Patent: March 29, 2011Assignee: GlobalFoundries Inc.Inventors: Cyrus E. Tabery, Srikanteswara Dakshina-Murthy, Chih-Yuh Yang, Bin Yu
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Patent number: 7915161Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: September 17, 2007Date of Patent: March 29, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Patent number: 7910475Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.Type: GrantFiled: July 17, 2009Date of Patent: March 22, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Ting Cheong Ang
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Patent number: 7906422Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: October 31, 2007Date of Patent: March 15, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7906848Abstract: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.Type: GrantFiled: February 19, 2009Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Kumagai, Hiroyuki Ohta, Naotaka Tanaka, Masahiko Fujisawa, Akihiko Ohsaki
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Patent number: 7902641Abstract: The present invention relates to a semiconductor device. The semiconductor device includes a fluorocarbon film formed on a substrate and a film containing metal formed on the fluorocarbon film, wherein the content amount of fluorine atom on the fluorocarbon film, which contacts the film containing metal, is in a predetermined range.Type: GrantFiled: July 24, 2008Date of Patent: March 8, 2011Assignee: Tokyo Electron LimitedInventor: Yoshiyuki Kikuchi
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Patent number: 7902067Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: October 4, 2007Date of Patent: March 8, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Patent number: 7901743Abstract: A method and system for treating a dielectric film on a plurality of substrates includes disposing the plurality of substrates in a batch processing system, the dielectric film on the plurality of substrates having a dielectric constant value less than the dielectric constant of SiO2. The plurality of substrates are heated, and a treating compound comprising a CxHy containing compound, wherein x and y represent integers greater than or equal to unity is introduced to the process system. A plasma is formed and at least one surface of the dielectric film on said plurality of substrates is exposed to the plasma.Type: GrantFiled: September 30, 2005Date of Patent: March 8, 2011Assignee: Tokyo Electron LimitedInventors: Eric M. Lee, Dorel I. Toma
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Patent number: 7897504Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.Type: GrantFiled: May 11, 2007Date of Patent: March 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jung Geun Kim, Cheol Mo Jeong, Whee Won Cho, Seong Hwan Myung
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Patent number: 7892965Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: September 17, 2007Date of Patent: February 22, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee
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Patent number: 7883986Abstract: This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having an elevationally outer portion and an elevationally inner portion within the isolation trenches. At least one of carbon removal from and/or oxidation of the outer portion of the solidified dielectric occurs. After such, the dielectric outer portion is etched selective to and effective to expose the dielectric inner portion. After the etching, dielectric material is deposited over the dielectric inner portion to within the isolation trenches.Type: GrantFiled: October 1, 2009Date of Patent: February 8, 2011Assignee: Micron Technology, Inc.Inventor: Li Li
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Patent number: 7875981Abstract: To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection structure in which a parasitic capacitance between the interconnections can be reduced, efficient methods for manufacturing the multilayer interconnection structure, and an efficient method for manufacturing a semiconductor device with a high speed and reliability. The insulating film material contains at least a silicon compound having a steric structure represented by Structural Formula (1) below. where, R1, R2, R3, and R4 may be the same or different and at least one of them represents a functional group containing any of a hydrocarbon and an unsaturated hydrocarbon.Type: GrantFiled: February 26, 2008Date of Patent: January 25, 2011Assignee: Fujitsu LimitedInventors: Yasushi Kobayashi, Yoshihiro Nakata, Shirou Ozaki
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Patent number: 7875547Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.Type: GrantFiled: January 12, 2005Date of Patent: January 25, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Wang Hsu, Jyu-Horng Shieh, Yi-Nien Su, Peng-Fu Hsu, Hun-Jan Tao
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Patent number: 7875549Abstract: A film forming method includes the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio larger than 1 smaller than 2, the F/C ratio being defined as a ratio of a number of F atoms to a number of C atoms in a source gas molecule.Type: GrantFiled: July 23, 2004Date of Patent: January 25, 2011Assignee: Tokyo Electron LimitedInventors: Kenichi Nishizawa, Yasuhiro Terai, Akira Asano
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Patent number: 7871923Abstract: An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.Type: GrantFiled: January 26, 2007Date of Patent: January 18, 2011Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.Inventors: Chung-Shi Liu, Chen-Hua Yu
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Patent number: 7871925Abstract: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.Type: GrantFiled: March 16, 2009Date of Patent: January 18, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sung Min Kim, Min Suk Suh
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Patent number: 7858513Abstract: A low-cost and efficient process produces self-aligned vias in dielectric polymer films that provides electrical connection between a top conductor and a bottom conductor. The process is achieved by printing conductive posts on the first patterned conductive layer, followed by the deposition of an unpatterned layer dielectric, followed by the deposition of a second patterned conductive layer. The vias are formed during the flash annealing of the post after the dielectric is deposited, but before the second conductive layer is deposited. In this process, the post material is annealed with a flash of light, resulting in a release of energy which removes the dielectric on the top of the post.Type: GrantFiled: June 18, 2007Date of Patent: December 28, 2010Assignee: OrganicID, Inc.Inventors: Siddharth Mohapatra, Klaus Dimmler, Patrick H Jenkins
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Patent number: 7858507Abstract: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.Type: GrantFiled: February 6, 2009Date of Patent: December 28, 2010Assignee: The Regents of the University of MichiganInventor: Stephen R. Forrest
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Publication number: 20100314767Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.Type: ApplicationFiled: June 16, 2009Publication date: December 16, 2010Applicant: International Business Machines CorporationInventors: Shyng-Tsong Chen, Qinghuang Lin, Sampath Purushothaman, Terry A. Spooner, Shawn M. Walsh