Silicide Formation Patents (Class 438/630)
  • Patent number: 7220623
    Abstract: The present invention is directed to a method of manufacturing silicide used to reduce a contact resistance at a contact of a semiconductor device and a semiconductor device with the silicide manufactured by the same method. The method comprises the steps of: (a) cleaning a semiconductor substrate with a transistor formed thereon, the transistor including a source electrode, a drain electrode and a gate electrode; (b) placing the cleaned semiconductor substrate into a sputter chamber in a deposition equipment, and forming silicide at the same time of depositing a metal film under a state where the semiconductor substrate is heated at a temperature of 450-600° C.; (c) removing residual metal film not used for the formation of silicide; and (d) annealing the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 22, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae-Won Han
  • Patent number: 7214621
    Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Gordon A. Haller, Thomas Arthur Figura, Ravi Iyer
  • Patent number: 7186604
    Abstract: After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: March 6, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Sakai, Satoshi Yamamoto, Atsushi Hiraiwa, Ryoichi Furukawa
  • Patent number: 7179737
    Abstract: In a semiconductor device, the ohmic contact at the junction between the metal interconnection and the semiconductor layer is lowered by depositing a first conductor layer comprised of, for example, tungsten nitride and a second conductor layer comprised of, for example, tungsten silicide successively from the lower layer so as to cover the upper surface of intermediate conductive layers comprised of a metal, for example, tungsten as a main interconnection material, subsequently introducing an impurity, for example, boron (b) to the second conductor layer, then patterning the first and the second conductor layers thereby forming a conductor layer, and then forming a lower semiconductor layer comprised of, for example, polycrystal silicon for forming a semiconductor region for source and drain of load MISFET of SRAM so as to be in contact with the conductor layer.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 20, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Akio Nishida, Kazuhito Ichinose, Hiraku Chakihara
  • Patent number: 7153769
    Abstract: A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first material. The first and second materials are of different compositions, and are proximate one another at an interface. The first and second materials as being proximate one another at the interface are capable of reacting with one another at some minimum reaction temperature when in an inert non-plasma atmosphere at a pressure. The interface is provided at a processing temperature which is at least 50° C. below the minimum reaction temperature, and is provided at the pressure. With the interface at the processing temperature and at the pressure, the substrate is exposed to a plasma effective to impart a reaction of the first material with the second material to form a reaction product third material of the first and second materials over the first material. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Guy T. Blalock
  • Patent number: 7144807
    Abstract: Low resistivity, C54-phase TiSi2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750° C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi2, forming a low-resistivity, C54-phase TiSi2 film on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSi2 is reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (<0.3 ?m) of low-resistivity, C54-phase TiSi2 films on heavily doped polysilicon are thus achieved.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: December 5, 2006
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Michael A. Vyvoda
  • Patent number: 7144816
    Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Mark Doczy
  • Patent number: 7132365
    Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Sue Ellen Crank, Shirin Siddiqui, Deborah J. Riley, Trace Quentin Hurd, Peijun J. Chen
  • Patent number: 7132352
    Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: November 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Simon Siu-Sing Chan, Paul R. Besser, Jeffrey P. Patton
  • Patent number: 7122474
    Abstract: A method for forming a barrier metal of a semiconductor device wherein a TiSiN layer having an atomic layer thickness is deposited by performing deposition of an Si layer inside a contact hole of a semiconductor device using an atomic layer deposition process and by performing deposition of a precursor layer on the Si layer. By repetition of this ALD process, the TiSiN layer is thickly formed at a desired thickness. Then, the TiSiN layer is plasma processed under the atmosphere of a nitrogen gas and a hydrogen gas, or an ammonia gas, and thus impurities are removed from the TiSiN layer. Therefore, it is easy to thickly form the TiSiN layer for the barrier metal. It is possible to reduce resistivity of the TiSiN layer to a relatively low level. Thereby, it is possible to decrease a contact resistance of the TiSiN layer and, further, to enhance an electrical characteristic of the semiconductor device.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: October 17, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Han-Choon Lee
  • Patent number: 7109108
    Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon. A high performance TFT can be realized.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: September 19, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
  • Patent number: 7074711
    Abstract: A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: July 11, 2006
    Assignee: Dongbu Electronics, Co., Ltd.
    Inventor: Byeong Ryeol Lee
  • Patent number: 7067391
    Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: June 27, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Wen Chan, Chih-Hao Wang, Lawrance Hsu, Hun-Jan Tao
  • Patent number: 7052946
    Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: May 30, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chien-Hao Chen, Chia-Lin Chen, Ju-Wang Hsu, Tze-Liang Lee, Shih-Chang Chen
  • Patent number: 7049222
    Abstract: A semiconductor device includes an element separating insulating film provided on a semiconductor substrate to separate an element region. A gate electrode is arranged above the element region. Source/drain regions are formed in the semiconductor substrate to sandwich a region below the gate electrode. A silicide film is provided on the source/drain regions, extending onto the element separating insulating film. A contact hole extends through the interlayer insulating film, which is provided on the element separating insulating film and the silicide film, and reaches the silicide film. Ends of the contact hole are positioned on the silicide film and on the element separating insulating film. The contact hole includes a trench portion whose one end contacts with the edge of the silicide film in the bottom of the contact hole and in an upper portion of the element separating insulating film. A wiring layer is arranged in the contact hole.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshihiko Iinuma
  • Patent number: 7045864
    Abstract: A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with power supply voltage and a ground voltage, respectively. The MISFETs are formed with a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leakage current of the MISFETs due to a voltage difference between the drain regions and wells can be reduced, and, thus, the power consumption can be reduced.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: May 16, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kota Funayama, Yasuko Yoshida, Masaru Nakamichi, Akio Nishida
  • Patent number: 7041543
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is NMOS devices using a highly tensile post-salicide silicon nitride capping layer on the source and drain regions. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in NMOS channel.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: May 9, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, William W. Crew, James S. Sims
  • Patent number: 7033930
    Abstract: Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate, forming a silver layer overlying the interface layer, annealing the substrate to form an intermetallic layer between the silver layer and the interface layer, the silver layer is in intimate contact with the intermetallic layer, and forming a protection layer overlying the silver layer. Other interconnect structures and processes are also described.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Michael Kozhukh, Oleg Rashkovskiy
  • Patent number: 7030006
    Abstract: Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method including forming many conductive layer patterns on a substrate, forming an interlayer insulating layer on a resulting structure where the conductive layer patterns are completed, exposing a conductive layer pattern which at least one sidewall of a contact region between conductive layer patterns is neighboring the contact region, and forming an insulating spacer on the sidewall of the exposed conductive layer pattern.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: April 18, 2006
    Assignee: Hynix Semiconductor Inc
    Inventors: Sung-Chan Park, Phil-Goo Kong, Kuk-Han Yoon
  • Patent number: 7019402
    Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Russell Alan Budd, Thomas Anthony Wassick
  • Patent number: 7015076
    Abstract: A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: March 21, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darin A. Chan, Simon Siu-Sing Chan, Paul L. King
  • Patent number: 7008873
    Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: March 7, 2006
    Assignees: HRL Laboratories, LLC, Raytheon Company
    Inventors: Lap-Wai Chow, William M. Clark, Jr., James P. Baukus
  • Patent number: 7005373
    Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: February 28, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
  • Patent number: 6967160
    Abstract: Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: November 22, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric Paton, Paul Raymond Besser, Simon S. Chan, Fred Hause
  • Patent number: 6960525
    Abstract: A method of forming a metal plug. First, a dielectric layer is formed on a substrate. Next, a patterned hard mask is formed on the dielectric layer. The dielectric layer is etched through the patterned hard mask to form a contact hole in the dielectric layer so as to expose parts of the substrate. An isolated layer is formed on the patterned hard mask. A barrier is then formed conformally on the isolated layer and the exposed substrate of the contact hole. A metal layer is formed to fill the contact hole and cover the barrier. A thermal treatment is performed to form a silicide between the barrier layer and the substrate. Finally, parts of the metal layer, barrier, isolated layer, and patterned hard mask are removed. The metal plug with a planar surface is thus formed in the contact hole.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: November 1, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Hui-Min Mao
  • Patent number: 6946735
    Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: September 20, 2005
    Assignee: Infineon AG
    Inventors: Stefan Gernhardt, Jenny Lian, Andreas Hilliger, Rainer Bruchhaus, Uwe Wellhausen, Nicolas Nagel
  • Patent number: 6908837
    Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Patent number: 6908850
    Abstract: A structure and method are provided for fabricating a field effect transistor (FET) having a metal gate structure. A metal gate structure is formed in an opening within a dielectric region formerly occupied by a sacrificial gate. The metal gate structure includes a first layer contacting a gate dielectric formed over a semiconductor region of a substrate. The first layer includes a material selected from the group consisting of metals and metal compounds. The gate further includes a silicide formed over the first layer. The FET further includes a source region and a drain region formed on opposite sides of the gate, the source and drain regions being silicided after the first layer of the gate is formed.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: June 21, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Huilong Zhu
  • Patent number: 6905922
    Abstract: A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: June 14, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Yee-Chia Yeo
  • Patent number: 6890808
    Abstract: A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Omer H. Dokumaci
  • Patent number: 6881663
    Abstract: Silicide interfaces for integrated circuits, thin film devices, and back-end integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high-temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Y. Jeff Hu
  • Patent number: 6875705
    Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Jie Tsai, Jeng Yang Pan, Chin-Nan Wu, Meng-Chang Liu, Su-Yu Yeh
  • Patent number: 6873019
    Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: March 29, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Jiro Ida, Naoko Nakayama
  • Patent number: 6869873
    Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Agere Systems Inc.
    Inventors: Robert Wayne Bradshaw, Daniele Gilkes, Sailesh Mansinh Merchant, Deepak A. Ramappa, Kurt George Steiner
  • Patent number: 6867135
    Abstract: A method of forming a copper/barrier layer interface comprising the following sequential steps. A structure having a lower copper layer formed thereover is provide. A patterned dielectric layer is formed over the lower copper layer. The patterned dielectric layer having an opening exposing a portion of the lower copper layer. The exposed portion of the lower copper layer is converted to a copper silicide portion. A barrier layer is formed upon the patterned dielectric layer and the copper silicide portion, lining the opening, whereby the lower copper layer/barrier layer interface is formed such that the barrier layer contacts the copper silicide portion to form an interface.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: March 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien I Bao, Syun-Ming Jang
  • Patent number: 6867118
    Abstract: A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Fumihiko Noro
  • Patent number: 6858525
    Abstract: A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi
  • Patent number: 6852588
    Abstract: Methods are provided for fabricating semiconductor structures and semiconductor device structures utilizing epitaxial Hf3Si2 layers. A process in accordance with one embodiment of the invention begins by disposing a silicon substrate in a processing chamber. The pressure within the processing chamber and a temperature of the silicon substrate in the range of approximately 250° C. to approximately 700° C. is established. A layer of Hf3Si2 then is grown overlying the silicon substrate at a rate in the range of about one (1) to about five (5) monolayers per minute.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: February 8, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhiyi Yu, Jay A. Curless, Yong Liang
  • Patent number: 6841453
    Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: January 11, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ubaldo Mastromatteo
  • Patent number: 6831012
    Abstract: After a silicidation blocking pattern is formed on a substrate including silicon, the silicidation blocking pattern is hardened by a thermal annealing process. The substrate is rinsed to remove a native oxide film formed on the substrate, and then a silicide film is formed on a portion of the substrate exposed by the silicidation blocking pattern. The silicide film can thus be formed in an exact portion of the substrate, and the substrate is not damaged during rinsing.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: December 14, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Keun Kang, Yong-Sun Ko, In-Seak Hwang, Byoung-Moon Yoon
  • Patent number: 6825088
    Abstract: Gate wiring is formed serving as first gate wiring in a DRAM-forming area, and gate wiring 33 is formed as second gate wiring in a logic-forming area. Then, cobalt silicide layer 37 is formed over a source/drain diffused layer in the DRAM-forming area, and cobalt silicide layer is formed over a source/drain diffused layer and the gate wiring in the logic-forming area. Such formation of the cobalt silicide layer reduces the resistance of the gate wiring and the contact resistance, and thereby enables the high-speed operation of a semiconductor device even if the device is microfabricated.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hidenori Sato, Yasunori Sogo
  • Patent number: 6819417
    Abstract: A new method is provided for monitoring silicon quality, the new method is applied at the time of pre-salicidation of the silicon substrate. The optical refractive index of the pre-salicide substrate is monitored, this monitoring provides insight into the quality of the silicon substrate at that time of a substrate processing cycle.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: November 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yun-Hung Shen, Bih-Huey Lee
  • Patent number: 6815264
    Abstract: A method of producing an antifuse, comprises the steps of: depositing a layer of undoped or lightly doped polysilicon on a layer of silicon dioxide on a semiconductor wafer; doping one region of the polysilicon P+; doping another region of the polysilicon N+, leaving an undoped or lightly doped region between the P+ and N+ regions; and forming electrical connections to the P+ and N+ regions.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: November 9, 2004
    Assignee: Zarlink Semiconductor Limited
    Inventors: Paul Ronald Stribley, John N Ellis, Ian G Daniels
  • Patent number: 6809024
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: October 26, 2004
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Patent number: 6806190
    Abstract: In order to prevent silicides from getting under side walls when the silicides are formed over MOSFET formed over an SOI substrate, trenches are defined in the SOI substrate and side walls are formed over the trenches, whereby the silicides are blocked so as not to get under a gate insulator with a lower portion of each side wall as a structure convex in a downward direction of the substrate. Thus, an increase in gate withstand voltage, a decrease in gate leakage current and control on a short channel effect are achieved.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: October 19, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Liu Guo Lin
  • Publication number: 20040195689
    Abstract: A butting contact structure using a silicide to connect a contact region and a conductor and a method to manufacture the same are disclosed. The method comprises the steps of: forming a first area having a first conduction type and a second area having a second conduction type which is adjacent to the first area; forming a silicide to be in contact with the first and second areas; and depositing an insulating layer covering the first portion of the silicide; etching a contact window in the insulating layer for exposing a surface of the silicide; and forming a conductor filling in the contact window. The difficulty from the reduction of the contact window is overcome without altering the manufacturing process and the layer of masks. Moreover, the density and performance of the semiconductor element is improved.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 7, 2004
    Inventors: Chorng-Wei Liaw, Ming-Jang Lin, Wei-Jye Lin
  • Patent number: 6797598
    Abstract: A method for forming an epitaxial cobalt silicide layer on a MOS device includes sputter depositing cobalt in an ambient to form a first layer of cobalt suicide on a gate and source/drain regions of the MOS device. Subsequently, cobalt is sputter deposited again in an ambient of argon to increase the thickness of the cobalt silicide layer to a second thickness.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: September 28, 2004
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Chong Wee Lim, Chan Soo Shin, Daniel Gall, Ivan Georgiev Petrov, Joseph E. Greene
  • Publication number: 20040175931
    Abstract: In a via-first Dual Damascene method, after a via hole and a wiring trench are formed, an SiN film, an exposed portion of an SiC film and an exposed portion of an SiC film are removed by etching. As a result, the via hole reaches a Cu wire, and the wiring trench reaches an SiOC film. A reaction product adheres mainly to a side wall portion of the wiring trench. The reaction product also adheres to other spots, but an amount of adherence to the side wall portion is the largest. Subsequently, oxygen plasma treatment is performed for insides of the via hole and the wiring trench. As a result of this oxygen plasma treatment, the reaction product is removed.
    Type: Application
    Filed: February 2, 2004
    Publication date: September 9, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Haruhito Nishibe, Michio Oryoji
  • Patent number: 6787451
    Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Yasuhiro Shimamoto, Katsunori Obata, Kazuyoshi Torii, Masahiko Hiratani
  • Patent number: 6787450
    Abstract: A method is described for filling of high aspect ratio contact vias provided over silicon containing areas. A via is formed in an insulating layer over the silicon containing area and a silicide forming material is deposited in the via. A silicide region is formed over the silicon containing area, the silicide forming material is removed from the via leaving the silicide region. The via is then filled with a conductor using an electroless plating process.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Paul A. Morgan