Silicide Formation Patents (Class 438/630)
  • Patent number: 6787436
    Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: September 7, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew S. Buynoski, Witold Maszara
  • Patent number: 6780758
    Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 6767823
    Abstract: Chemical vapor deposition methods of forming titanium silicide comprising layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide comprising layer on the substrate.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: July 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Irina Vasilyeva, Ammar Derraa, Philip H. Campbell, Gurtej S. Sandhu
  • Patent number: 6756254
    Abstract: An integrated circuit is formed by a method having the steps of providing a circuit substrate with a first metallized region, providing a first insulation layer covered by a silicon layer, patterning the first insulation layer and silicon layer to form a first insulation region and first silicon region, then forming a second metallized layer on the silicon region, heating the material so that the second metal layer diffuses into the silicon layer to form a metal silicide region, which is subsequently covered by a second insulating layer having a contact with an interconnect to enable contacting an antifuse formed by the metal silicide region.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: June 29, 2004
    Assignee: Infineon Technologies AG
    Inventor: Rene Tews
  • Patent number: 6757475
    Abstract: A method of making and an etchable wafer substrate for use in making optical fiber array plates includes forming a progressively increasing series of metrology holes when the plate holes are formed. The variation between designed plate hole diameter and actual plate hole diameter is determined by sequentially inserting a probe of known designed diameter into the metrology holes to determine the two size-adjacent metrology holes variation. The plate hole diameter can be determined by comparing one of the size-adjacent metrology hole diameter with the respective art work metrology hole diameter. Plate hole diameters can then be corrected for variation with further processing.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 29, 2004
    Assignee: Fiberguide Industries, Inc.
    Inventors: Jonathan Sherman, Randall Miller, Robert Sherman, Donald Russell
  • Patent number: 6753224
    Abstract: A new Inter Poly Dielectric (IPD) layer is provided for use in creating ultra-small gate electrodes. A first and a second high-k dielectric film are provided which remain amorphous at relatively high processing temperatures. The first high-k dielectric film is of Al3O5—ZrO2—Al3O5, the second high-k dielectric film is aluminum doped ZrO2 or HfO2.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: June 22, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yeou-Ming Lin, Tuo-Hung Hou
  • Publication number: 20040087138
    Abstract: A first depressed portion is formed on an insulating film. A burying material is applied onto the first depressed portion and the insulating film to bury the first depressed portion. Chemical mechanical polishing of the burying material is performed until the insulating film is exposed, thereby leaving the burying material only in the first depressed portion. A resist having a pattern of a second depressed portion that overlaps the first depressed portion is formed on the insulating film in which the burying material has been buried. The burying material and the insulating film are etched to a predetermined depth using the resist as a mask to form the second depressed portion. The resist and the burying material left are removed after the step of etching. A conductive material is deposited in the first depressed portion and the second depressed portion.
    Type: Application
    Filed: July 16, 2003
    Publication date: May 6, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takeo Ishibashi, Yoshiharu Ono
  • Patent number: 6730591
    Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: May 4, 2004
    Assignees: Chartered Semiconductor Manufactoring Ltd., Institute of Microelectronics
    Inventors: Licheng Han, Xu Yi, Simon Chooi, Mei Sheng Zhou, Joseph Zhifeng Xie
  • Publication number: 20040082163
    Abstract: An object is to provide a mask formation method, which can curtail a manufacturing cost.
    Type: Application
    Filed: February 19, 2003
    Publication date: April 29, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Yoshiaki Mori, Takuya Miyakawa, Mitsuru Sato, Shintaro Asuke, Kenichi Takagi
  • Patent number: 6727168
    Abstract: A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first dielectric layer and to within the contact openings. The second dielectric layer is etched selectively relative to the first dielectric layer to form at least a portion of a local interconnect outline within the second dielectric layer to extend between the first transistor gate and the second transistor source/drain region. The etching removes at least some of the second dielectric layer within the contact openings. Conductive material is formed within the local interconnect outline within the second dielectric layer which electrically connects the first transistor gate with the second transistor source/drain region. Other aspects are disclosed.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: April 27, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Todd R. Abbott
  • Patent number: 6727166
    Abstract: A method is presented for forming a transistor gate structure. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. A layer of silicon oxynitride is deposited on the gate material. The layer of silicon oxynitride, the gate material and the gate oxide layer are etched to form a gate structure. A silicon oxynitride region remains on top of the gate structure. A wet chemical process is performed to remove the silicon oxynitride region from the top of the gate structure. After performing the wet chemical process, spacers are formed around the gate structure.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: April 27, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Edward Yeh, Olivier Laparra
  • Patent number: 6716745
    Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: April 6, 2004
    Assignee: Micron Technology, IInc.
    Inventors: Salman Akram, Y. Jeff Hu
  • Patent number: 6713378
    Abstract: The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed as initially partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration. In subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: March 30, 2004
    Assignee: Micron Technology, Inc.
    Inventor: John M. Drynan
  • Publication number: 20040038517
    Abstract: A contact structure is formed by forming an interlayer dielectric on a substrate having a semiconductive region. A contact hole is formed in the interlayer dielectric to expose the semiconductive region. A conductive structure is formed adjacent to the contact hole. Spacers are formed on inner sidewalls of the contact hole. A cobalt silicide layer is formed at a bottom of the contact hole. The spacers are configured to electrically isolate the cobalt silicide layer from the conductive structure. A conductive layer is formed on the cobalt silicide layer in the contact hole.
    Type: Application
    Filed: June 30, 2003
    Publication date: February 26, 2004
    Inventors: Sang-Bum Kang, Kwang-Jin Moon, Seung-Gil Yang, Hee-Sook Park
  • Patent number: 6660634
    Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: December 9, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Shekhar Pramanick, Takeshi Nogami
  • Patent number: 6657301
    Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: December 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyoshi Maekawa, Yasuhiro Kanda
  • Patent number: 6653225
    Abstract: A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal expansion by patterning a refractory metal silicide layer after performing a thermal process on a refractory metal silicide layer, thereby having a stable operation characteristic, and a method for manufacturing the same are provided.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: November 25, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Byong-Sun Ju, Jae-Cheol Paik
  • Publication number: 20030211725
    Abstract: The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventors: Chia-chi Chung, Shin-Yi Tsai
  • Publication number: 20030211726
    Abstract: A semiconductor device (118) and method of fabrication thereof, wherein a plurality of conductive lines (124) are formed over a workpiece, a surface-smoothing conductive material (140) is disposed over the conductive lines 124), and a magnetic material (132) disposed is over the surface-smoothing conductive material (140). The surface-smoothing conductive material (140) has a smaller grain structure than the underlying conductive lines (124). The surface-smoothing conductive material (140) is polished so that the surface-smoothing conductive material (140) has a texturally smoother surface than the surface of the conductive lines (124).
    Type: Application
    Filed: May 10, 2002
    Publication date: November 13, 2003
    Applicant: Infineon Technologies North America Corp.
    Inventor: Kia-Seng Low
  • Publication number: 20030207561
    Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
    Type: Application
    Filed: May 28, 2003
    Publication date: November 6, 2003
    Inventors: Valery M. Dubin, Chin-Chang Cheng, Makarem A. Hussein, Phi L. Nguyen, Ruth A. Brain
  • Patent number: 6642119
    Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: November 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, Shankar Sinha, Simon S. Chan
  • Patent number: 6632740
    Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are fomxed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with nitrogen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: October 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jacques J. Bertrand, George J. Kluth
  • Patent number: 6605490
    Abstract: A semiconductor device having a pad for electrical connection provided on a semiconductor substrate, a first insulating film with which a surface of the semiconductor substrate is coated and having an opening to which the pad is exposed, a conductive film joined to the pad on a bottom surface of the opening of the first insulating film and extending to a surface of the first insulating film outside the opening, a second insulating film with which the conductive film is coated and having an opening to which a part of the conductive film is exposed, and a connecting member arranged so as to be joined to the conductive film inside the opening of the second insulating film.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: August 12, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Publication number: 20030143838
    Abstract: Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate, forming a silver layer overlying the interface layer, annealing the substrate to form an intermetallic layer between the silver layer and the interface layer, the silver layer is in intimate contact with the intermetallic layer, and forming a protection layer overlying the silver layer. Other interconnect structures and processes are also described.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Inventors: Michael Kozhukh, Oleg Rashkovskiy
  • Patent number: 6599832
    Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: July 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Y. Jeff Hu
  • Publication number: 20030139038
    Abstract: A method for manufacturing a semiconductor element is provided. The method includes a first silicon region, a second silicon region, and a metal silicide layer, wherein the metal silicide layer contacts with the first silicon region and the second silicon region separately, the method including steps of performing a first doping process to dope an N-type dopant into the first silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the first silicon region, and performing a second doping process to dope a P-type dopant into the second silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the second silicon region.
    Type: Application
    Filed: May 3, 2002
    Publication date: July 24, 2003
    Applicant: ProMos Technologies, Inc.
    Inventor: S.C. Sun
  • Publication number: 20030119304
    Abstract: A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a halogen and a halide salt.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventor: Brian A. Vaartstra
  • Patent number: 6583052
    Abstract: A method of fabricating a semiconductor device having the steps of forming an isolation layer in a silicon substrate to define an active region and a device isolation region; forming a junction region in the active region of the silicon substrate; forming an interlayer dielectric layer on the silicon substrate; forming a contact hole exposing the junction region by selectively removing the interlayer dielectric layer; selectively removing an exposed portion of the junction region under the contact hole; sequentially forming a thin metal layer and a buffer layer on the resultant structure including over the selectively removed portion of the junction region; and forming a silicide layer in the selectively removed portion of the junction region by performing a heat treatment.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 24, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Suk Shin, Yong Sun Sohn
  • Patent number: 6569759
    Abstract: A semiconductor integrated circuit device is implemented by circuit components and a multi-layered wiring structure, and titanium nitride is used for a part of the integrated circuit such as a conductive plug, an accumulating electrode and a conductive line, wherein the titanium nitride layer is laminated on a titanium silicide layer so as to absorb thermal stress due to the titanium nitride layer.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 27, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuya Taguwa
  • Publication number: 20030092256
    Abstract: In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection plugs 105a by charging copper into the first holes 101a; forming a semiconductor film 108 on one face side of the support side silicon wafer 101 through an intermediate insulating film 109; forming elements on the semiconductor film 108; exposing bottom faces of the primary connection plugs 105a by polishing the other face of the support side silicon wafer 101; forming second holes 111 extending from an element forming face of the semiconductor film 108 to the primary connection plugs 105; and forming auxiliary connection plugs 112a for electrically connecting the elements with the primary connection plugs 105a by charging copper into the second holes 111.
    Type: Application
    Filed: January 7, 2002
    Publication date: May 15, 2003
    Inventor: Naohiro Mashino
  • Publication number: 20030092255
    Abstract: A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.
    Type: Application
    Filed: November 14, 2001
    Publication date: May 15, 2003
    Inventor: Ende Shan
  • Publication number: 20030087514
    Abstract: A method used to form a semiconductor device comprises patterning a hard mask layer with a first pattern, then only partially etching through an underlying dielectric layer using the hard mask as a pattern. Next, the hard mask is patterned with a second pattern and the dielectric layer is completely etched through using the hard mask as a pattern. The dielectric etch stops on an etch stop layer. Finally, the etch stop layer is patterned which is defined only by the first pattern of the hard mask.
    Type: Application
    Filed: November 2, 2001
    Publication date: May 8, 2003
    Inventors: Sanh Dang Tang, James Mathew
  • Publication number: 20030082874
    Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.
    Type: Application
    Filed: December 9, 2002
    Publication date: May 1, 2003
    Inventors: Richard H. Lane, John K. Zahurak
  • Patent number: 6555424
    Abstract: The present invention discloses a thin film transistor with sub-gates and Schottky source/drain and a method of manufacturing the same. Doping of source/drain, and the following annealing steps used conventionally are omitted and the complexity of process and process costs are reduced. The temperature of the process is also decreased. A thin film transistor with sub-gates and Schottky source/drain of the invention is able to operate in both the n type and p type channel modes on the same transistor element depending on the biased voltage of the sub-gate. Moreover, an electric junction is formed by induction, using bias voltage applied on the sub-gate, which takes the place of the conventional source/drain extensions. Consequently, the off-state leakage current is reduced.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: April 29, 2003
    Assignee: S. M. Sze
    Inventors: Horng-Chih Lin, Ming-Shih Tsai, Tiao-Yuan Huang
  • Publication number: 20030077891
    Abstract: The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed as initially partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration. In subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 24, 2003
    Inventor: John M. Drynan
  • Patent number: 6551928
    Abstract: A method of forming a semiconductor device with a polysilicon layer having a multi-layer tungsten-silicide (WSix) film formed on a surface thereof includes the steps of (1) forming a first layer of tungsten-silicide on the surface of the polysilicon layer; (2) forming a second layer of a material selected from tungsten and silicon on the first layer; (3) forming a third layer of tungsten-silicide on the second layer; and (4) thermally treating the multi-layer film resulting from steps (a)-(c) to form a multi-layer WSix film on the surface of the polysilicon layer, the multi-layer WSix film having a uniform small grain size. In various embodiments, steps (1)-(3) may be repeated one or more times. A semiconductor device includes a semiconductor body having a polysilicon layer formed on a surface thereof and a multilayered WSix film formed on a surface of the polysilicon layer by the process described above.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: April 22, 2003
    Assignee: Promos Technologies, Inc.
    Inventor: Hsiao-Che Wu
  • Patent number: 6534400
    Abstract: Disclosed is a method for depositing a tungsten silicide layer on a wafer coated with a polysilicon layer in a CVD process chamber. A surface of the polysilicon layer is pre-treated by introducing a hydrogen compound gas including any elements among group III elements or group V elements of the periodic table into the CVD process chamber. The tungsten silicide layer is deposited on the polysilicon layer by introducing a silane source gas and a tungsten source gas into the CVD process chamber. Since the surface of the polysilicon layer is pre-treated using the hydrogen compound gas before the tungsten silicide layer is deposited on the polysilicon layer, void generation is prevented on an interfacial surface between the tungsten silicide layer and the polysilicon layer.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: March 18, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Young Ahn, Woo Sung Lee, Man Sug Kang, Hee Seok Kim
  • Publication number: 20030045091
    Abstract: A method of forming contact for a semiconductor device is disclosed.
    Type: Application
    Filed: December 28, 2001
    Publication date: March 6, 2003
    Inventors: In Cheol Ryu, Sung Gon Jin
  • Patent number: 6528413
    Abstract: A semiconductor device comprises impurity diffusion layers formed in a semiconductor substrate and containing a metal element, whose siliciding activation energy is less than 1.8 eV, at a concentration of more than 1×1011 atoms/cm2 and less than 1×1015 atoms/cm2, an insulating film formed on the semiconductor substrate, contact holes formed in the insulating film on the impurity diffusion layers, and contact plugs formed via the contact holes. Accordingly, there is provided the semiconductor device that has a connection structure between an impurity-containing semiconductor layer and a conductive film and is capable of suppressing a leakage current generated at a contact portion between the impurity diffusion layer and the conductive film.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventor: Kazuo Hashimi
  • Patent number: 6524952
    Abstract: A method of forming a silicide layer in contact with a silicon substrate. The method comprises forming the silicide layer by supplying a silicon-containing source that is different from the silicon substrate, such that the silicon in the silicide layer originates primarily from the silicon-containing source.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: February 25, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Ramanujapuram A. Srinivas, Brian Metzger, Shulin Wang, Frederick C. Wu
  • Patent number: 6518176
    Abstract: A contact level via and a method of performing selective deposition of a barrier layer to form a contact level via for selective aluminum metallization. Specifically, the method forms a self-aligned silicide region by depositing titanium atop a structure containing a contact level via, converting the titanium in the contact regions into titanium silicide, removing the unreacted titanium, and performing nitridation of the titanium silicide to complete a barrier layer located in only the contact region of the via. Once the barrier layer is formed, the layer can be optionally fortified through oxygen stuffing to create an effective barrier layer for aluminum metallization.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: February 11, 2003
    Inventors: Ted Guo, Liang-Yuh Chen, Suchitra Subrahmanyan, Roderick C. Mosely
  • Patent number: 6514859
    Abstract: A method of forming a self-aligned silicide (salicide) with a double gate silicide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously thicker than silicide formations over the source and drain areas.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeff Erhardt, Eric Paton
  • Publication number: 20030008496
    Abstract: The invention concerns a method for fabricating an electronic component with self-aligned source, drain and gate, comprising the following steps:
    Type: Application
    Filed: January 31, 2002
    Publication date: January 9, 2003
    Inventor: Simon Deleonibus
  • Publication number: 20030003712
    Abstract: The present invention discloses methods for fabricating a semiconductor device. A gate electrode having a hard mask layer at its upper portion is formed, and an interlayer insulating film is formed over the resultant structure. A landing plug contact hole is formed by etching the interlayer insulating film, and a conductive layer is formed over the resultant structure, filling up the landing plug contact hole. A first CMP process is performed to expose the hard mask layer, and a second CMP process is preformed to planarize the hard mask layer, the interlayer insulating film and the landing plug conductive layer. The CMP processes of the present invention reduce or prevent dishing of the mask insulating film or contact plug, to reduce or prevent the likelihood of a bridge forming between adjacent conductive plugs. As a result, the semiconductor device has improved properties and/or improved yield.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 2, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventors: Pan Ki Kwon, Sang Ick Lee, Chul Woo Nam
  • Publication number: 20020197780
    Abstract: This invention relates to a method for forming a metal oxide semiconductor type field effect transistor (MOSFET), more particularly, to the method for forming the MOSFET by forming a gate and a spacer in a trench. The present invention is used to form the gate and the spacer of the MOSFET in the trench which is preformed in the substrate to reduce the junction depth of the source/drain region. The present invention also can reduce the defects in the drain induced barrier lowering and the punch-through leakage to avoid the spiking leakage defects in the back-end process.
    Type: Application
    Filed: June 26, 2001
    Publication date: December 26, 2002
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Chao Lai, Hung-Sui Lin, Tao-Cheng Lu
  • Patent number: 6498088
    Abstract: The present invention minimizes or eliminates the disadvantages associated with multilevel interconnect structures by providing a method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: December 24, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi
  • Patent number: 6495460
    Abstract: A semiconductor device and method for manufacturing the semiconductor device employing mixed metal silicide technology is disclosed. A semiconductor device is provided having a doped silicon region, such as a source/drain. A first metal layer comprising titanium and a second metal layer comprising nickel are deposited over the semiconductor device. The device is subjected to rapid thermal annealing. The resulting device has a mixed metal silicide layer over the doped silicon region, the mixed metal silicide layer and the doped silicon region having smooth interface between them.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: December 17, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jacques Bertrand, George Kluth, Minh Van Ngo, Christy Mei-Chu Woo
  • Publication number: 20020177297
    Abstract: A method for forming a wire in a semiconductor device, in forming a titanium film and a titanium nitride film as a barrier metal layer, which can deposit a titanium film and a titanium nitride film each in a different chamber by removing a titanium oxide film used as an insulating film made of upper titanium bonding with oxygen in air as the upper portion of a titanium film is exposed to air by a plasma process and then depositing a titanium nitride film, and as a result can reduce the throughput time of chamber equipment since the partial utilization of the system of the chamber equipment is enabled by driving another chamber even in case one of the chambers breaks down.
    Type: Application
    Filed: April 5, 2002
    Publication date: November 28, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventor: Young-a Cho
  • Publication number: 20020177298
    Abstract: The present invention comprises the steps of performing a reforming process on a surface of a low dielectric constant insulation film formed on a substrate which includes one of a porous low dielectric constant insulation film and a non-porous low dielectric constant insulation film and forming an insulation film as at least one of an etching mask and a Chemical Mechanical Polishing stopper (CMP stopper) on the reformed surface of the low dielectric constant insulation film. For example, plasma is radiated as a reforming process mentioned above, the surface roughness of a low dielectric insulation film is increased and, as a result, adhesion between the films and also between the inter-layer insulation film and other neighboring films can be improved with so-called “anchor effect”.
    Type: Application
    Filed: March 12, 2002
    Publication date: November 28, 2002
    Inventors: Nobuo Konishi, Mitsuaki Iwashita, Hiroki Ohno, Shigeru Kawamura, Masahito Sugiura
  • Patent number: 6482737
    Abstract: In a method of fabricating a semiconductor device in which a metal film is formed that is to serve as the diffusion barrier layer material of a plug electrode material that is used when forming a plug electrode on a diffusion layer electrode or a gate electrode in which a metal silicide layer has been formed, increase in the resistance of the plug electrode is prevented. Immediately after the formation of a plug hole by a dry etching method, silicon ions are implanted with an acceleration voltage of at least 20 KeV and at a dosage of at least 1×1013 atoms/cm2, following which a titanium film and a titanium nitride film are formed as the metal film by a sputtering method without carrying out etching by an RF etching method.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: November 19, 2002
    Assignee: NEC Corporation
    Inventor: Nobuaki Hamanaka