Abstract: A method for forming a fine pattern of a semiconductor device overcomes resolution limits of exposure equipment. The method includes forming a first photoresist pattern over an underlying layer formed over a semiconductor substrate. An amorphous carbon film and a second photoresist film are sequentially deposited over the first photoresist pattern. The second photoresist film and the amorphous carbon film are planarized to expose the first photoresist pattern. A thick portion and a thin portion of the amorphous carbon film is formed. The first photoresist pattern and the second photoresist film are removed. Etching is performed on the thin portion of the amorphous carbon film and the underlying layer using the thick portion of the amorphous carbon film as an etch mask. The thick portion of the amorphous carbon film is removed to expose a fine pattern of the underlying layer.

Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.

Abstract: A method for forming a metal line of a semiconductor device uses a low dielectric constant material as an interlayer dielectric layer and treats a surface of the interlayer dielectric layer with plasma to prevent moisture and ammonia from being adsorbed in the low dielectric constant material. The method for forming a metal line of a semiconductor device includes forming a lower metal line layer on a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on an entire surface including the lower metal line layer, forming a plasma layer by treating a surface of the interlayer dielectric layer with plasma, forming a photoresist pattern on the plasma layer, forming a via hole using the photoresist pattern as a mask to open the lower metal line layer, and forming a via contact by burying a metal material in the via hole.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.

Abstract: Method for filling a trench in a semiconductor product is disclosed. A first material is deposited onto a semiconductor product having a surface in which at least one trench is formed. A first layer is formed within the trench and on the surface of the semiconductor product outside the trench. A second material is deposited to form a second layer above the first layer outside the trench and the trench is filled. Chemical mechanical polishing is performed so that the second layer is removed above the first layer outside the trench and whereby the first layer is at least uncovered outside the trench. Residual first material of the first layer is removed by wet-chemical etching.

Abstract: Disclosed are a method for forming a metal interconnection and a semiconductor device including the metal interconnection. The method includes the steps of forming a slope by etching a corner of a contact hole, which exposes a predetermined pattern formed on a substrate, forming a barrier metal layer on an interlayer dielectric layer, plasma-treating the barrier metal layer with hydrogen and nitrogen gases for about 27 to 37 seconds, heat-treating the substrate in a nitrogen atmosphere, forming a tungsten layer on the barrier metal layer through a two-step nucleation process and bulk deposition process, and performing a chemical mechanical polishing process on the tungsten layer until the interlayer dielectric layer is exposed. The method and the semiconductor device prevent defects of the metal interconnection, such as a volcano defect caused by fluorine penetration.

Abstract: A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.

Abstract: Provided herein are hardmask compositions that include an organosilane polymer prepared by the reaction of one or more compounds of Formula (I) Si(OR1)(OR2)(OR3)R4 wherein R1, R2 and R3 may each independently be alkyl acetoxy or oxime; and R4 may be hydrogen, alkyl, aryl or arylalkyl; and wherein the organosilane polymer has a polydispersity in a range of about 1.1 to about 2.

Abstract: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may be formed by performing only deposition on the first oxide film. A thickness of the first oxide film may be set to be above 5 k?. A first passivation layer may be formed by planarizing the first and second oxide films. In the planarizing process, a thickness of the first passivation layer may be 4 k?. A second passivation layer of a nitride film may be formed on the first passivation layer and the first and second passivations may be selectively etched so as to expose the upper metal pad.

Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.

Abstract: Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or more layers are measured. A barrier metal layer and a metal layer are sequentially formed in the trench and/or via hole. Portions of the metal layer, the barrier metal layer and the interlayer insulating layer are removed. After that, the combined thickness of the two or more insulating layers is measured again.

Abstract: The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an aspect of the invention, a semiconductor substrate in which contact plugs are formed within contact holes of a first dielectric layer is first provided. An etch-stop layer and a hard mask pattern are formed over the first dielectric layer and the contact plugs. The etch-stop layer is patterned along the hard mask pattern. The exposed first dielectric layer and the contact plugs are etched to thereby form trenches in the first dielectric layer over the contact plugs. A metal layer is formed to gap-fill the trenches. A polishing process is performed to expose the etch-stop layer.

Abstract: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a nitrogen containing compound and depositing a metal barrier layer on at least a portion of the metal nitride barrier layer by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a reductant. A soak process may be performed on the substrate surface before deposition of the metal nitride barrier layer and/or metal barrier layer.

Abstract: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.

Abstract: Compositions and methods for processing a substrate having a conductive material layer disposed thereon are provided. In one embodiment, a composition for processing a substrate having a conductive material layer disposed thereon is provided which composition includes an acid based electrolyte, a chelating agent, a corrosion inhibitor, a passivating polymeric material, a pH adjusting agent, a solvent, and a pH between about 3 and about 10. The composition is used in a method to form a passivation layer on the conductive material layer, abrading the passivation layer to expose a portion of the conductive material layer, applying a bias to the substrate, and removing the conductive material layer.

Abstract: A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive patterns. A hard mask including an amorphous carbon layer and an oxide based layer are formed in sequential order over the insulation layer and the conductive pattern. The amorphous carbon layer and the oxide layer are selectively etched to form a mask pattern. The insulation layer is etched using the mask pattern as a mask to form a contact hole.

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326.

Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a top electrode layer deposited over the active material layer. The device uses a chemical or electrochemical liquid phase deposition process to selectively and conformally fill the insulative layer opening with the conductive bottom composite electrode layer. Conformally filling the conductive material within the opening reduces structural irregularities within the opening thereby increasing material density and resistivity within the device and thereby improving device performance and reducing programming current.

Abstract: A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough to the first insulating film, assuming that the ratio of a width of the wiring trench portion in a direction orthogonal to its extending direction to a height of the wiring trench portion is 2.8 times even at a maximum. A barrier metal film is formed to cover the cap film and the wiring trench portion. A wiring film is deposited to cover the barrier metal film. The wiring film and the barrier metal film are chipped away until the surface of the cap film is exposed from the surface of the wiring film, thereby to form a wiring portion which buries the wiring trench portion.

Abstract: The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal exposure time for the NiSi transistor contacts. A lower thermal budget for interconnect fabrication is necessary to prevent damage to the NiSi transistor contacts and minimize thermal stressing of previously formed interconnect layers. Microwave-cured dielectric films also have higher mechanical strength and strong adhesion to overlying layers deposited during subsequent semiconductor device manufacturing steps.

Abstract: A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area. An insulating layer is deposited over the semiconductor substrate. The insulating layer is planarized through a chemical mechanical polishing (CMP) process including a first polishing step and a second polishing step having different removal rates with respect to the insulating layer formed over the cell area and the scribe area.

Abstract: A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar surface over the low-k dielectric layer using spin-on method, and stress free polishing the metal layer. Preferably, the metal layer comprises copper or copper alloys. The metal layer preferably includes a first sub layer having a substantially non-planar surface and a second sub layer having a substantially planar surface on the first sub layer.

Abstract: In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Abstract: A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.

Abstract: A method for manufacturing a semiconductor device includes forming a predetermined structure including a first inorganic insulating film covering a copper interconnection, an organic insulating film formed above the first inorganic insulating film and having a hole pattern, and a second inorganic insulating film formed above the organic insulating film and having a trench pattern, dry etching the first inorganic insulating film by an etching gas containing a fluorocarbon family gas, using the organic insulating film having the hole pattern as a mask, to form a through-hole reaching the copper interconnection, and performing a plasma treatment using a mixed gas of an oxygen gas and a hydrocarbon gas, thereby removing fluorine remaining on a surface of the copper interconnection exposed by the through-hole, and thereby dry etching the organic insulating film using the second inorganic insulating film having the trench pattern as a mask.

Abstract: A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.

Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.

Abstract: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.

Abstract: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore, a part or all of the metal hard mask 107 is removed before the formation of TaN and Cu layers in the wiring groove 111. This enables a reduction in possible damage, which may increase the dielectric constant of the surface of low-dielectric-constant film, and thus in possible inter-wire leakage current. As a result, a reliable semiconductor device can be provided.

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

Abstract: Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with the present invention, a chemical mechanical polishing (CMP) process that is the last process of the storage node contact isolation process is performed by using the slurry without the selectivity or the reverse selectivity, thereby removing the plurality of cruspidal patterns at every interface of the plurality of bit line patterns BL and the plurality of storage node contacts.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and a planarization process can be performed on the sacrificial oxide layer and the IMD layer to substantially eliminate a height difference of the IMD layer.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.

Abstract: A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

Abstract: An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric layers. At least one of the dummy metals is substantially thinner than the interconnect metal lines. To form this structure, first and second pluralities of trenches are formed in the dielectric layer. At least one of the second plurality of trenches is shallower than the first plurality of trenches. The first and second pluralities of trenches are filled with a conductive layer and then planarized.

Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.

Abstract: A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on the substrate while under a vacuum of the type found in a vacuum chamber. A catalytic layer is deposited over the barrier layer without breaking the vacuum. A conductive material layer is deposited over the catalytic layer by electroless deposition.

Abstract: A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

Abstract: A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first co