Abstract: The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a semiconductor wafer to reduce the amount of material removed during chemical mechanical planarization (CMP) of the metal layer. This hardened layer may be produced, for example, by oxidizing the metal surface and/or coating the metal surface with a polymer. In one implementation, a relatively thick and dense oxide layer is formed on the wafer metal surface prior to CMP, by injecting, for example, an oxidant, such as oxygen or ozone, near the end of an annealing cycle. The hardened metal beneficially protects recessed regions from CMP chemical attack and CMP pad deformation, and thus reduces the thickness-to-planarity, dishing, and waste generation realized during CMP.

Abstract: A method and apparatus for processing barrier and metals disposed on a substrate in an electrochemical mechanical planarizing system are provided. In certain embodiments a method for electroprocessing a substrate is provided. The method comprises contacting the substrate with the non-conductive surface of a polishing pad assembly, establishing a first electrically conductive path through an electrolyte between an exposed layer of barrier material and a first electrode, establishing a second electrically conductive path through the electrolyte between the exposed layer of barrier material and a second electrode, applying a voltage to the first electrode to cause a voltage drop between the substrate and the second electrode, and removing the barrier material from the substrate.

Abstract: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP).

Abstract: A method of patterning a structure in a thin film on a substrate is described. A film stack on the substrate includes the thin film on the substrate, a developable anti-reflective coating (ARC) layer on the thin film, and a first photo-resist layer on the developable ARC layer. The first photo-resist layer and the developable ARC layer are imaged with a first image pattern and developed to form the first image pattern in the first photo-resist layer and the developable ARC layer. Thereafter, the first photo-resist layer is removed, and the developable ARC layer is modified by thermal treatment. A second photo-resist layer is then formed on the modified ARC layer, and the second photo-resist layer is imaged with a second image pattern and developed to form the second image pattern in the second photo-resist layer. The first and second image patterns are then transferred to the thin film.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: A semiconductor wafer including an underlying layer including an insulating film having at least one recess therein and a metallic material layer formed over a top surface of the underlying layer and filling the recess, on a semiconductor substrate, is subjected to a polishing treatment while supplying a basic CMP slurry containing metal ions on the semiconductor wafer to at least partially remove the metallic material layer. Then, an organic acid which chelates the metal ions is added to the basic CMP slurry, and polishing is conducted, using the organic acid-added CMP slurry, until a surface of the insulating film is exposed.

Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having thermally labile groups with an oxidizing gas in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: A contact plug is formed in a contact hole which is formed in an interlayer insulation film and then a barrier metal layer and a main wiring layer, which form a wiring layer in all, are formed on both of the interlayer insulation film and the contact plug. After a surface of the main wiring layer is flattened by means of CMP, an antireflection film is formed on the main wiring layer. After that, a resist pattern is formed on the antireflection film to pattern the wiring layer. Thus, it is possible to pattern the wiring layer finely without influence of unevenness caused by the contact plug located under the wiring layer.

Abstract: First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the opening. A physical sputter etch is performed on the structure while it is in a sputter etch module (206) to remove the parts of the first material overlying the substructure's surface and situated above the opening and to remove part of the second material overlying the first material in the opening so that remaining parts of the first and second materials are situated in the opening. The so-modified structure is transferred from the sputter etch module under a substantial vacuum, normally via a transfer module (202), to a deposition module (203, 204, or 205) where a layer of third material is deposited over the substructure's surface and over the parts of the first and second materials in the opening.

Abstract: The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order to suppress the polysilicon removal rate relative to silicon oxide and silicon nitride and improve the planarity of the polished substrate. Exemplary surfactants include alkyl and aryl alcohols of ethylene oxide (EO) and propylene oxide (PO) block copolymers and may be present in the slurry compositions in an amount of up to about 5 wt %, although much smaller concentrations may be effective. Other slurry additives may include viscosity modifiers, pH modifiers, dispersion agents, chelating agents, and amine or imine surfactants suitable for modifying the relative removal rates of silicon nitride and silicon oxide.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by minimizing an isolation area between moat areas, which includes the steps of forming a sacrificial layer on a substrate; forming a moat pattern by coating a photoresist on the sacrificial layer and performing exposure and development process to the coated photoresist with a mask pattern of the STI layer; patterning the sacrificial layer by using the moat pattern as a mask; forming an insulating layer on an entire surface of the substrate including the patterned sacrificial layer after removing the moat pattern; forming insulating layer sidewalls at the side of the sacrificial layer by anisotropically etching the insulating layer; removing the sacrificial layer and forming a silicon layer on the substrate; and planarizing the surface of the silicon layer and the insulating layer sidewalls by CMP.

Abstract: A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a barrier metal layer in the via hole, filling a refractory metal in an upper part of the barrier metal layer, planarizing the substrate filled with the refractory metal by performing a second CMP process, forming a refractory metal oxide layer by oxidizing a residual refractory metal region created by the second CMP process, and forming a refractory metal plug by removing the refractory metal oxide layer through a third CMP process.

Abstract: A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing) or other methods. The citric acid treatment may take place during a cleaning operation that takes place in a wafer scrubber, or subsequent to such an operation. The citric acid treatment removes copper oxides that form on copper surfaces exposed to the environment and prevents hillock formation during subsequent high temperature operations. The copper surface is then annealed and the annealing followed by an NH3 plasma treatment which again removes any copper oxides that may be present. The NH3 plasma operation roughens exposed surfaces improving the adhesion of subsequently-formed films such as a dielectric film preferably formed in-situ with the NH3 plasma treatment. The subsequently-formed film is formed over an oxide-free, hillock-free copper surface.

Abstract: In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.

Abstract: A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over the first dielectric layer and the metal layer. A surface treatment process is performed to the material layer so as to form a cap layer on the surface of the metal layer. The material layer and a portion of the first dielectric layer are removed. A second dielectric layer is formed over the substrate, and the surface of the second dielectric layer is higher than that of the cap layer. A planarization process is performed at least to remove a portion of the second dielectric layer and a portion of the cap layer so as to expose the top of the opening.

Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

Abstract: Provided is a method for fabricating a metal line of a semiconductor device. In a method according to one embodiment, an interlayer insulating layer is formed on a semiconductor substrate. After that, a first trench and a second trench having a wider width than that of the first trench are formed in the interlayer insulating layer. A seed layer is formed on the semiconductor substrate including the first and second trenches, and a first copper layer is formed on the seed layer. Subsequently, the first copper layer is polished until the interlayer insulating layer is exposed, and a second copper layer is formed on the first copper layer. Then, the second copper layer is planarized to form a copper line.

Abstract: A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a halogen and a halide salt.

Abstract: Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and R is selected from C4-C24 alkyl, C4-C24 alkenyl, C4-C24 alkoxy, C8-C24 alkenoxy, substituted C4-C24 hydrocarbon, non-substituted C1-C4 hydrocarbon or substituted C1-C4 hydrocarbon; and, partially etching the filler filling the via and an interlayer dielectric to form a trench, which is connected to the via in the region where the dual damascene interconnections are to be formed. Then, the filler remaining in the via is removed, and the trench and the via are filled with an interconnection material to complete the dual damascene interconnections.

Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Abstract: A composition for chemical mechanical polishing includes a slurry. A sufficient amount of a selectively oxidizing and reducing compound is provided in the composition to produce a differential removal of a metal and a dielectric material. A pH adjusting compound adjusts the pH of the composition to provide a pH that makes the selectively oxidizing and reducing compound provide the differential removal of the metal and the dielectric material. A composition for chemical mechanical polishing is improved by including an effective amount for chemical mechanical polishing of a hydroxylamine compound, ammonium persulfate, a compound which is an indirect source of hydrogen peroxide, a peracetic acid or periodic acid. A method for chemical mechanical polishing comprises applying a slurry to a metal and dielectric material surface to produce mechanical removal of the metal and the dielectric material.

Abstract: A method for forming a zeolite-carbon doped oxide (CDO) composite dielectric material is herein described. Zeolite particles may be dispersed in a solvent. The zeolite solvent solution may then be deposited on an underlying layer, such as a wafer of other dielectric layer. At least some solvent may then be removed to form a zeolite film. A CDO may then be deposited in the zeolite film to form a zeolite-CDO composite film/dielectric. The zeolite-CDO composite film/dielectric may then be calcinated to form a solid phase zeolite-CDO composite dilectric.

Abstract: A polishing-rate distribution of a target film is compared with a desired post-polishing film-thickness distribution of the target film, thereby obtaining a pre-polishing film-thickness distribution of the target film by a reverse calculation, so that film growing conditions can be controlled in advance so as to allow the target film to have, after polishing, a film-thickness distribution that is the same as the desired film-thickness distribution. Therefore, even if there is a possibility that variation in the step height of the wafer surface might be produced by polishing, the finally obtained target film's film-thickness distribution can be the desired film-thickness distribution. Accordingly, semiconductors in which device-to-device variation in characteristic is reduced can be provided.

Abstract: According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

Abstract: In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.

Abstract: The metal polishing slurry according to the present invention for use in chemical mechanical polishing during semiconductor device fabrication contains at least one compound of formula (A) below and at least one compound of formula (B) or formula (C) below: [wherein R1, R2, R3, R4 and R5 are each independently hydrogen, methyl, ethyl, phenyl, amino, sulfo, carboxy, aminomethyl, carboxymethyl, sulfomethyl, o-aminophenyl, m-aminophenyl, p-aminophenyl, o-carboxyphenyl, m-carboxyphenyl, p-carboxyphenyl, o-sulfophenyl, m-sulfophenyl or p-sulfophenyl].

Abstract: Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.

Abstract: Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous layer. A plasma can then be used to react a plurality of second molecules with the first layer of first molecules to form a first layer of a barrier layer. The barrier layers can seal the pores of the porous material, function as a diffusion barrier, be conformal, and/or have a negligible impact on the overall ILD k value of the porous material.

Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

Abstract: A method for fabricating a semiconductor device includes forming a barrier metal film on a substrate with an opening defined therein, forming a copper-containing film on said barrier metal film after having formed said barrier metal film on a surface of said substrate and an inner wall of said opening, and polishing said copper-containing film and said barrier metal film while applying a voltage to said substrate in a state that said copper-containing film and said barrier metal film are exposed.

Abstract: Processes are disclosed for producing electronic interconnect devices, particularly semi-conductor wafers, with metal interconnect traces thereon wherein the surface of said device has improved planarity. Said planarity is achieved initially through the use of pulse reverse electrolytic plating techniques. Planarity is further enhanced by cathodically protecting the metal interconnect traces during the polishing operation. Cathodic protection is achieved by overtly applying a cathodic charge to said traces and/or by contacting said traces, during polishing, with a metal that is capable of sacrificial corrosion when in contact with the metal of the interconnect traces.

Abstract: The invention provides a process for forming a planar copper structure on a wafer surface in a first module and a second module of a system. During the process, a copper layer is formed on the wafer surface by utilizing an electrochemical deposition process in the first module. After the deposition, the wafer is moved to the second module of the system and an electrochemical mechanical polishing process is applied to planarize the copper layer to a predetermined thickness. The first and second modules can be positioned in a cluster tool. The wafer is subsequently processed by selective copper CMP and selective barrier layer CMP, which are conducted in another cluster tool.

Abstract: A first chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, and an oxide film removal retarder which reduces a removal rate of the silicon oxide film. A second chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, an oxide film removal retarder which reduces a removal rate of silicon oxide, and a defect prevention agent which inhibits scratch defects and/or corrosion defects at a surface of an aluminum film. In a one-step CMP process, either of the first or second slurry is used throughout CMP of an aluminum layer until an upper surface of an underlying silicon oxide layer is exposed. In a two-step CMP process, the first slurry is used in an initial CMP of the aluminum layer, and then the second slurry is used in a subsequent CMP until the upper surface of the underlying silicon layer is exposed.

Abstract: A magnetic device having a magnetic feature, the magnetic feature including a magnetic portion comprising a magnetic material, a region of non-magnetic material adjacent to the magnetic portion, and a stop layer disposed above the region of non-magnetic material, defining a planar upper boundary of the magnetic portion.

Abstract: A method for chemical mechanical polishing of mirror structures. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a first dielectric layer overlying the semiconductor substrate and forming an aluminum layer overlying the first dielectric layer, the aluminum layer having an upper surface with a predetermined roughness of greater than 20 Angstroms RMS. The method also includes processing regions overlying the upper surface of the aluminum layer using a touch polishing process to reduce a surface roughness of the upper surface of aluminum layer to less than 5 Angstroms to form a mirror surface on the aluminum layer. Preferably, a protective layer is formed overlying the mirror surface on the aluminum layer.

Abstract: Embodiments relate to a method for forming a conductive plug of a semiconductor device that may include preparing a semiconductor substrate having multilayer metal interconnections, forming interlayer insulating layers above the semiconductor substrate, etching part of each interlayer insulating layer such that each multilayer metal connection is exposed, and forming a via hole, depositing a conductive layer such that the via hole is filled, and performing chemical mechanical polishing (CMP) on the conductive layer such that each interlayer insulating layer is exposed, and forming the plug. The step of performing the CMP on the conductive layer may be performed using a polishing pad having a polishing speed of about 3200 angstroms/min to about 5000 angstroms/min.

Abstract: Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected, forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film, and forming a trench having a width wider than that of the via hole on the intermetal insulating film. The method also includes the steps of exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source, performing a nitrogen passivation process for the exposed lower metal film, and forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. The dry etching of the third insulating film and the second insulating film is performed using a gas containing fluorine at a pressure of 0.1 Pa to 4 Pa. Ashing is preferably performed using at least one of hydrogen and an inert gas.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device.

Abstract: A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further includes annealing the layer of iridium, forming a dielectric layer on the layer of iridium, and forming a conductive layer on the dielectric layer.

Abstract: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a nitrogen containing compound and depositing a metal barrier layer on at least a portion of the metal nitride barrier layer by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a reductant. A soak process may be performed on the substrate surface before deposition of the metal nitride barrier layer and/or metal barrier layer.

Abstract: Disclosed is a method for forming a gate in a semiconductor device. The method includes the steps of: sequentially forming a gate insulation layer and an inter-layer insulation layer on a substrate; patterning the inter-layer insulation layer into a predetermined configuration, thereby forming a patterned inter-layer insulation layer; forming a nitride layer on the patterned inter-layer insulation layer; simultaneously etching the nitride layer and the substrate, thereby obtaining a spacer on sidewalls of the patterned inter-layer insulation layer and a trench having a predetermined depth in the substrate; forming a conductive layer on the trench; and planarizing the conductive layer, thereby forming the gate.

Abstract: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2?t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)?GD2 for the second copper layer.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection region (4), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer (6), a hard mask layer (7), and a second dielectric layer (8) are deposited on the semiconductor body (1), where at the location of the connection region (4) to be formed, a via (44) is formed in the first dielectric layer (6) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned photoresist layer deposited on top of the structure and at the location of the connection conductor (6) to be formed, a trench (55) is formed in the second dielectric layer (8) by means of plasma etching

Abstract: There is provided a substrate processing method which, even when a material having a low mechanical strength is employed as an interlayer dielectric, can produce a semiconductor device having a multi-layer interconnect structure of fine interconnects in higher yield. A substrate processing method according to the present invention includes steps of: providing a substrate having interconnect recesses formed in a surface; forming a metal film on the surface of the substrate by plating to embed the metal film in the interconnect recesses; removing the metal film formed in an ineffective region of the substrate and an extra metal film formed in an effective region of the substrate; and flattening the surface of the substrate after removal of the metal film by performing chemical-mechanical polishing.