Having Viahole Of Tapered Shape Patents (Class 438/640)
  • Patent number: 10197973
    Abstract: The invention relates to a silicon-based component with at least one chamfer formed from a method combining at least one oblique side wall etching step with a “Bosch” etching of vertical side walls, thereby enabling aesthetic improvement and improvement in the mechanical strength of components formed by micromachining a silicon-based wafer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 5, 2019
    Assignee: Nivarox-FAR S.A.
    Inventor: Alex Gandelhman
  • Patent number: 9972534
    Abstract: A semiconductor device includes a through-substrate via structure, a first metal layer, an electronic component over the through-substrate via structure, a second metal layer and another electronic component below the through-substrate via structure. The through-substrate via structure includes a through hole penetrating from a first surface to an opposite second surface of a semiconductor substrate, and an acute angle is included between a sidewall of the through hole and the second surface on a side of the semiconductor substrate. The through-substrate via structure also includes a conductive layer that fills the through hole, and a semiconductor layer disposed in the through hole and interposed between the conductive layer and the semiconductor substrate.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 15, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Li-Che Chen, Tzu-Hsuan Chen, Hsing-Chao Liu
  • Patent number: 9741605
    Abstract: A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for semiconductor device(s), the metallization structure including a bottom layer of contact(s) surrounded by a dielectric material. The starting metallization structure further includes an etch-stop layer over the bottom layer, a layer of dielectric material over the etch-stop layer, a first layer of hard mask material over the dielectric layer, a layer of work function hard mask material over the first hard mask layer, a second layer of hard mask material over the work function hard mask layer, via(s) to the first hard mask layer and other via(s) into the etch-stop layer. The method further includes protecting the other via(s) while removing the second hard mask layer and the layer of work function hard mask material, and filling the vias with metal.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Sunil Kumar Singh
  • Patent number: 9607992
    Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventor: Ruth A. Brain
  • Patent number: 9583429
    Abstract: A method comprises depositing a first dielectric layer over a substrate, forming a first metal line and a second metal line in the first dielectric layer, wherein the first metal line and the second metal line are separated from each other by a width approximately equal to a width of the first metal line, applying an etching process to the first metal line and the second metal line to form a first trench and a second trench, depositing a liner layer over the first dielectric layer and forming a via over the first metal line, wherein a bottom of the via is in direct contact with a top surface of the first metal line and the bottom of the via is conformal to the first trench.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Su-Jeng Sung
  • Patent number: 9425048
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
  • Patent number: 9362373
    Abstract: A semiconductor device includes a semiconductor substrate which functions as an n? drift layer, a trench IGBT formed in the front surface, an interlayer insulator film, and a metal electrode layer on the interlayer insulator film. There is a contact hole in the interlayer insulating film which has a first opening formed on the metal electrode layer side and a second opening on the semiconductor substrate side. Width w1 of the first opening on the metal electrode layer side is wider than width w2 of first opening on the semiconductor substrate side, in a direction perpendicular to the extending direction of the trench in the planar pattern of trenches. The metal electrode layer is connected to a p-type channel region and an n+ source region via the contact hole. The method of manufacturing improves the reliability of the device.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: June 7, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Koji Sasaki
  • Patent number: 9269611
    Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: February 23, 2016
    Assignees: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Thanh Khae Pham, Xiuyu Cai, Bala Subramanian Pranatharthi Haran, Charan Veera Venkata Satya Surisetty, Jin Wook Lee, Shom Ponoth, David V. Horak
  • Patent number: 9269618
    Abstract: A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. An barrier film is formed over sidewalls of the bit line, and a storage node contact plug is obtained by filling a space between the bit lines so that an upper portion of the storage node contact is wider than a lower portion of the storage node contact. As a result, the process can be simplified and a short between the storage node contact plug and the bit line can be prevented.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: February 23, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hyung Jin Park
  • Patent number: 9257279
    Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 9153721
    Abstract: A solar cell assembly, a solar cell array, and a method for manufacturing the same are provided. The solar cell assembly may include a solar cell and an interconnection member, the interconnection member comprising a first portion and a second portion attached to the first portion with an angle formed therebetween. The solar cell array may comprise at least two said solar cell assemblies. In an embodiment, the top surfaces of the first solar cell and the second solar cell are arranged such that the second portion of the first interconnect member and the second portion of the second interconnection member are adjacent to each other, and at least the end portion of the second portion of the first interconnection member is bended together with at least the end portion of the second portion of the second interconnection member.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: October 6, 2015
    Assignee: SolAero Technologies Corp.
    Inventor: Cory Tourino
  • Patent number: 9107315
    Abstract: Disclosed is a via structure in a multi-layer substrate, comprising a first metal layer, a dielectric layer and a second metal layer. The first metal layer has an upper surface. The dielectric layer covers the first metal layer in which a via is opened to expose the upper surface. The second metal layer is formed in the via and contacts an upper surface and an inclined wall of the via. A contacting surface of the second metal layer has a top line lower than the upper edge of the inclined wall. Alternatively, the second metal layer can be formed on the dielectric layer as being a metal line simultaneously as formed in the via as being a pad. The metal line and the pad are connected electronically. The aforesaid metal second layer can be formed in the via and on the dielectric layer by a metal lift-off process.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 11, 2015
    Assignee: PRINCO MIDDLE EAST FZE
    Inventor: Chih-kuang Yang
  • Patent number: 9059249
    Abstract: An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.
    Type: Grant
    Filed: September 1, 2012
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maxime Darnon, Qinghuang Lin
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 9006103
    Abstract: A method of manufacturing a wiring substrate, includes, forming an etching stop layer and a first wiring layer on a supporting member, forming a first insulating layer on the first wiring layer, forming a via hole reaching the first wiring layer, and forming the wiring layers of an n-layer and the insulating layers of an n-layer, removing the supporting member and the etching stop layer, thereby forming a build-up intermediate body, forming a second insulating layer on the wiring layer of an n-th layer, and forming a third insulating layer on first wiring layer, forming a via hole reaching the wiring layer of the n-th layer, and forming a via hole reaching the first wiring layer, forming a roughened face to the third insulating layer, and forming a second wiring layer connected to the wiring layer, and forming a third wiring layer connected to the first wiring layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiro Kobayashi, Kotaro Kodani, Junichi Nakamura, Kentaro Kaneko
  • Patent number: 9006102
    Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventors: Yu Hong, Liu Huang, Zhao Feng
  • Patent number: 9000489
    Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Patent number: 8987916
    Abstract: A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • Patent number: 8957526
    Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-ho Chun, Byung-lyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
  • Patent number: 8956969
    Abstract: A hole formation method including applying a pillar-forming liquid to a base material, to thereby form a pillar; applying an insulating film-forming material to the base material on which the pillar has been formed, to thereby form an insulating film; removing the pillar to form an opening in the insulating film; and heat treating the insulating film in which the opening has been formed.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: February 17, 2015
    Assignees: Ricoh Company, Ltd., Sijtechnology, Inc.
    Inventors: Yuji Sone, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Kazuhiro Murata, Kazuyuki Masuda
  • Patent number: 8952500
    Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8946077
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
  • Patent number: 8946906
    Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: February 3, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Patent number: 8940634
    Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: January 27, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc., STMicroelectronics, Inc.
    Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
  • Patent number: 8927410
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 8912660
    Abstract: An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: December 16, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Jun Sasaki, Kosuke Yamada
  • Patent number: 8906801
    Abstract: Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: December 9, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Ralf Richter, Hans-Jürgen Thees
  • Patent number: 8906802
    Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jeremy A. Wahl, Gerard M. Schmid, Richard A. Farrell, Chanro Park
  • Patent number: 8901701
    Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 2, 2014
    Inventor: Chia-Sheng Lin
  • Patent number: 8900929
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu, Kang Chen
  • Patent number: 8896127
    Abstract: An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20140332867
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
  • Patent number: 8878212
    Abstract: A light emitting device includes a substrate, at least one electrode, a first contact layer, a second contact layer, a light emitting structure layer, and an electrode layer. The electrode is disposed through the substrate. The first contact layer is disposed on a top surface of the substrate and electrically connected to the electrode. The second contact layer is disposed on a bottom surface of the substrate and electrically connected to the electrode. The light emitting structure layer is disposed above the substrate at a distance from the substrate and electrically connected to the first contact layer. The light emitting structure layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The electrode layer is disposed on the light emitting structure layer.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 4, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Woo Sik Lim, Sung Kyoon Kim, Sung Ho Choo, Hee Young Beom
  • Patent number: 8853862
    Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo Vega
  • Publication number: 20140264922
    Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.
    Type: Application
    Filed: April 3, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 8836129
    Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
  • Patent number: 8815734
    Abstract: A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8809185
    Abstract: A method for profiling a film stack includes receiving a film stack having an insulation layer, a dielectric hard mask layer, and a patterned metal hard mask layer. The pattern in the patterned metal hard mask layer is transferred to the dielectric hard mask layer using a first dry etching process. The pattern in the dielectric hard mask layer is then transferred to the insulation layer using a second dry etching process including one or more halogen-containing gases. The second etching process etches the insulation layer and removes a portion of the patterned metal hard mask layer, which exposes a corner of the underlying dielectric hard mask layer. Portions of the dielectric hard mask layer that overhang the insulation layer are removed using a third dry etching process including a process composition that is more selective to the dielectric hard mask layer relative to the insulation layer.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yannick Feurprier
  • Patent number: 8803245
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 12, 2014
    Assignee: McAfee, Inc.
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 8796140
    Abstract: A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiaoxiong Gu, Michael Mcallister
  • Patent number: 8778793
    Abstract: A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takahisa Furuhashi, Naohito Suzumura
  • Patent number: 8772944
    Abstract: A semiconductor substrate includes a via-hole that extends from a first surface to a second surface. An electrode pad layer that serves as the bottom of the via-hole is disposed on the second surface. An insulating layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole. A metal layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole with the insulating layer interposed therebetween and is directly formed on the bottom of the via-hole. An inclined surface is formed on the sidewall of the via-hole such that the bottom of the via-hole has a smaller opening size than the open end of the via-hole. The inclined surface has asperities.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadanori Suto
  • Patent number: 8772930
    Abstract: A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 8, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Pui Chung Simon Law, Dan Yang, Xunqing Shi
  • Patent number: 8765604
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Patent number: 8759691
    Abstract: A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 24, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Shinji Ouchi, Shigeru Yamada, Makoto Terui, Yoshinori Shizuno
  • Patent number: 8759983
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Patent number: 8759211
    Abstract: A method includes applying, between connection conductors of adjacent substrates, a junction material containing the first metal or alloy component and the second metal or alloy component having a higher melting point than said first metal or alloy component. The method further includes melting the junction material by a heat treatment.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 24, 2014
    Assignee: Napra Co., Ltd.
    Inventors: Shigenobu Sekine, Yurina Sekine, Yoshiharu Kuwana, Ryuji Kimura
  • Patent number: 8753974
    Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brian Griffin, Russ Benson
  • Patent number: 8748221
    Abstract: The present invention discloses a nanoball solution coating method and applications thereof. The method comprises steps: using a scraper to coat a nanoball solution on a substrate to attach a plurality of nanoballs on the substrate; flushing or flowing through the substrate with a heated volatile solution to suspend the nanoballs unattached to the substrate in the volatile solution; and using the scraper to scrape off the volatile solution carrying the suspended nanoballs, whereby is simplified the process to coat nanoballs. The method can be used to fabricate nanoporous films, organic vertical transistors, and large-area elements and favors mass production.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 10, 2014
    Assignee: National Chiao Tung University
    Inventors: Hsin-Fei Meng, Hsiao-Wen Zan, Yen-Chu Chao, Kai-Ruei Wang, Yung-Hsuan Hsu
  • Patent number: 8742588
    Abstract: The present invention provides a method of forming a via hole (9), or a via (7), from a lower side (5) of a substrate (3) for electronic devices towards an upper side (4) of a substrate (3) at least partly through the substrate (3). The method comprises the steps of: etching a first lengthwise portion (11) of the via hole (9) and etching a second lengthwise portion (12) of the via hole (9); whereby the first lengthwise portion (11) and the second lengthwise portion (12) substantially form the via hole (9) and a constriction (23) is formed in the via hole (9). The constriction (23) defines an aperture (24) of the via hole (9) and the method further comprises the step of opening the via hole (9) by etching, with the constriction (23) functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: June 3, 2014
    Assignee: ÅAC Microtec AB
    Inventors: Peter Nilsson, Jürgen Leib, Robert Thorslund