Having Adhesion Promoting Layer Patents (Class 438/644)
  • Patent number: 9721896
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 9704703
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film containing a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a first process gas containing the predetermined element and a halogen element to the substrate; supplying a second process gas containing carbon and nitrogen to the substrate; supplying a third process gas containing carbon to the substrate; and supplying a fourth process gas to the substrate, the fourth process gas being different from each of the first to the third process gases.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: July 11, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Atsushi Sano
  • Patent number: 9559059
    Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
  • Patent number: 9428842
    Abstract: The present invention generally related to adding Indium precursors to deposition processes for thin films. Indium precursors are added in order to increase the growth rate per cycle of the deposition process. A plurality of deposition processes are disclosed herein which comprising a plurality of deposition cycles and providing an In-precursor pulse before at least one reactant pulse in at least one deposition cycle. The In-precursor can be added for increasing the average growth rate per cycle by at least 50% and in many examples above 500% compared to the growth rate of a similar deposition process without providing an In-precursor. Examples disclosed herein include the deposition of thin films comprising pnictides or chalcogenides, made by atomic layer deposition.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 30, 2016
    Assignee: ASM IP Holding B.V.
    Inventor: Viljami Pore
  • Patent number: 9287311
    Abstract: It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 15, 2016
    Assignee: SONY CORPORATION
    Inventors: Kan Shimizu, Keishi Inoue
  • Patent number: 9257303
    Abstract: Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: February 9, 2016
    Assignee: ASM INTERNATIONAL N.V.
    Inventors: Suvi P. Haukka, Antti Niskanen, Marko Tuominen
  • Patent number: 9187826
    Abstract: A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b).
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: November 17, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kimihiko Nakatani, Kazuhiro Harada, Hiroshi Ashihara, Ryuji Yamamoto
  • Patent number: 9045831
    Abstract: A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Koji Ono
  • Patent number: 8994073
    Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 31, 2015
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Zoltan Ring
  • Patent number: 8969196
    Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Patent number: 8951911
    Abstract: Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Mehul B. Naik, Zhenjiang Cui
  • Patent number: 8946079
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Tera Probe, Inc.
    Inventors: Shinji Wakisaka, Takeshi Wakabayashi
  • Patent number: 8937378
    Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: January 20, 2015
    Assignee: MDS Co., Ltd.
    Inventors: Sung-kwan Paek, Se-chuel Park
  • Patent number: 8871636
    Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8866313
    Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
  • Publication number: 20140203437
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8772155
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • Patent number: 8765597
    Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8735195
    Abstract: Disclosed is a method of manufacturing a ZnO-based semiconductor device having at least p-type ZnO-based semiconductor layer, which includes a step of forming a contact metal layer on the p-type ZnO-based semiconductor layer wherein the contact metal layer contains at least one of Ni and Cu; and a step of performing heat treatment of the contact metal layer and the p-type ZnO-based semiconductor layer under an oxygen-free atmosphere to form a mixture layer including elements of the p-type ZnO-based semiconductor layer and the contact metal layer at a boundary region therebetween while maintaining a metal phase layer on a surface of the contact metal layer.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 27, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Naochika Horio
  • Patent number: 8716737
    Abstract: An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 6, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiu Jen Lin, Jian Shian Lin, Shau Yi Chen, Chieh Lung Lai
  • Patent number: 8696921
    Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Patent number: 8669182
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Patent number: 8669177
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiro Kouno, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada
  • Publication number: 20140061914
    Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng
  • Patent number: 8569165
    Abstract: An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: October 29, 2013
    Assignee: President and Fellows of Harvard College
    Inventors: Roy Gerald Gordon, Harish B. Bhandari, Yeung Au, Youbo Lin
  • Patent number: 8563423
    Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8507803
    Abstract: The invention offers a board-connecting structure that can provide electrodes with a fine pitch and that can combine the insulating property and the connection reliability. The structure of connecting printed wiring boards 10 and 20 electrically connects a plurality of first electrodes 12 and 13 provided to be adjacent to each other on a first board 11 with a plurality of second electrodes 22 and 23 provided to be adjacent to each other on a second board 21 through an adhesive 30 that contains conductive particles 31 and that has anisotropic conductivity. By heating and pressing the adhesive placed between the mutually facing first electrode 12 and second electrode 22 and between the mutually facing first electrode 13 and second electrode 23, an adhesive layer 30a is formed between the first board 11 and the second board 21 and in the adhesive layer 30a, a cavity portion 33 is formed between the first electrodes 12 and 13 and between the second electrodes 22 and 23.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: August 13, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masamichi Yamamoto, Kyouichirou Nakatsugi, Ayao Kariya, Katsuhiro Satou, Yasuhiro Okuda
  • Patent number: 8377822
    Abstract: A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8372739
    Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: February 12, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Satohiko Hoshino, Kuzuhiro Hamamoto, Shigeru Mizuno, Yasushi Mizusawa
  • Patent number: 8349725
    Abstract: The present invention is a method of manufacturing a semiconductor device comprising: forming a recess in an interlayer insulating film formed on a substrate surface, the recess being configured to be embedded with an upper conductive channel mainly made of copper to be electrically connected to a lower conductive channel; supplying a gas containing an organic compound of manganese, and forming a barrier layer made of a compound of manganese for preventing diffusion of copper to the interlayer insulating film, such that the barrier layer covers an exposed surface of the interlayer insulating film; after the formation of the barrier layer, supplying organic acid to the barrier layer in order to increase a ratio of manganese in the compound of manganese forming the barrier layer; after the supply of the organic acid, forming a seed layer mainly made of copper on a surface of the barrier layer; after the formation of the seed-layer, heating the substrate in order to separate out manganese from on the surface of
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: January 8, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Sato, Hitoshi Itoh, Kenji Matsumoto
  • Publication number: 20120319282
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Applicant: Tessera, Inc.
    Inventors: Cyprian Uzoh, Belgacem Haba, Craig Mitchell
  • Patent number: 8268722
    Abstract: Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu—O bonds is contacted with trimethylaluminum to form a precursor layer having Al—O bonds and Al—C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al—N, Al—H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH3, H2, N2, and mixtures thereof. A dielectric diffusion barrier layer is then deposited.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 18, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Jengyi Yu, Hui-Jung Wu, Girish Dixit, Bart van Schravendijk, Pramod Subramonium, Gengwei Jiang, George Andrew Antonelli, Jennifer O'loughlin
  • Patent number: 8236687
    Abstract: A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid -solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time for performing a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiu-Jen Lin, Jian-Shian Lin, Shau-Yi Chen, Chieh-Lung Lai
  • Patent number: 8211794
    Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: July 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Valli Arunachalam, Satyavolu Srinivas Papa Rao, Sanjeev Aggarwal, Stephan Grunow
  • Patent number: 8212359
    Abstract: A semiconductor integrated circuit device can be mounted on a circuit board through capacitive coupling even when being miniaturized. A passivation film disposed on a principal surface of a semiconductor substrate provided with a plurality of wirings laminated sequentially with insulating films therebetween has an opening at which at least a portion of the uppermost layer wiring is exposed. An electrode is arranged to cover the uppermost layer wiring exposed at the opening of the passivation film and the periphery of the opening of the passivation film. A dielectric layer is arranged to cover the electrode. An extension portion of the electrode on the surface of the passivation film and an electrode of a circuit board are capacitively coupled with a dielectric layer therebetween.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: July 3, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuki Ito
  • Patent number: 8183153
    Abstract: Disclosed is a method for manufacturing a semiconductor device which is decreased in resistance of a copper wiring containing a ruthenium-containing film and a copper-containing film, thereby having improved reliability. Also disclosed is an apparatus for manufacturing a semiconductor device. Specifically, an Ru film is formed on a substrate having a recessed portion by a CVD method using a raw material containing an organic ruthenium complex represented by the general formula and a reducing gas (step S12). Then, a Cu film is formed on the Ru film by a CVD method using a raw material containing an organic copper complex represented by the general formula and a reducing gas, thereby forming a copper wiring containing the Ru film and the Cu film in the recessed portion (step S14).
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: May 22, 2012
    Assignee: Ulvac, Inc.
    Inventors: Hideaki Zama, Michio Ishikawa, Takumi Kadota, Chihiro Hasegawa
  • Patent number: 8178436
    Abstract: Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: May 15, 2012
    Assignee: Intel Corporation
    Inventors: Sean King, Jason Klaus
  • Patent number: 8173538
    Abstract: By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom of a via in advanced metallization structures of highly scaled semiconductor devices.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 8, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Carsten Peters, Thomas Foltyn
  • Patent number: 8169077
    Abstract: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Louis C. Hsu, Rajiv V. Joshi
  • Patent number: 8163602
    Abstract: There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy C. Krywanczyk, Donald W. Brouillette, Steven A. Martel, Matthew R. Whalen
  • Patent number: 8119524
    Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu
  • Patent number: 8110502
    Abstract: A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: February 7, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ting Cheong Ang
  • Patent number: 8105935
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: January 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoki Ohara, Hirofumi Watatani, Tamotsu Owada, Kenichi Yanai
  • Patent number: 8089113
    Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: January 3, 2012
    Assignee: Spansion LLC
    Inventors: Suzette K. Pangrle, Steven Avanzino, Sameer Haddad, Michael VanBuskirk, Manuj Rathor, James Xie, Kevin Song, Christie Marrian, Bryan Choo, Fei Wang, Jeffrey A. Shields
  • Publication number: 20110285024
    Abstract: A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer.
    Type: Application
    Filed: May 21, 2010
    Publication date: November 24, 2011
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8053361
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: November 8, 2011
    Assignees: Globalfoundries Singapore Pte. Ltd
    Inventors: Jing Hui Li, Wu Ping Liu, Lawrence A. Clevenger
  • Publication number: 20110221044
    Abstract: Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 15, 2011
    Inventors: Michal Danek, Tom Mountsier, Jonathan Reid, Juwen Gao, Aaron Fellis
  • Patent number: 7989342
    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: August 2, 2011
    Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
  • Patent number: 7968455
    Abstract: A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 28, 2011
    Assignee: Enthone Inc.
    Inventors: Xuan Lin, Richard Hurtubise, Vincent Paneccasio, Qingyun Chen
  • Publication number: 20110151659
    Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: THUY B. DAO, CHANH M. VUONG