Having Noble Group Metal (i.e., Silver (ag), Gold (au), Platinum (pt), Palladium (pd), Rhodium (rh), Ruthenium (ru), Iridium (ir), Osmium (os), Or Alloy Thereof) Patents (Class 438/650)
  • Patent number: 7470617
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20080318417
    Abstract: A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate.
    Type: Application
    Filed: September 5, 2008
    Publication date: December 25, 2008
    Applicant: ASM JAPAN K.K.
    Inventors: Hiroshi Shinriki, Hiroaki Inoue
  • Publication number: 20080315426
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Patent number: 7468108
    Abstract: A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer including non-metal components from the precursor. The chemisorbed layer can be treated with an oxidant and the non-metal components removed to form a treated layer of metal. A capacitor electrode can be formed including the treated layer and, optionally, additional treated layers. Preferably, treating the layer does not substantially oxidize the metal and the treated layers exhibit the property of inhibiting oxygen diffusion. The chemisorbing and the treating can be performed at a temperature below about 450° C. or preferably below about 350° C.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: December 23, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 7462555
    Abstract: Disclosed is a ball grid array substrate having a window formed on a core material instead of a thin core material, and wherein a semiconductor chip is mounted thereon, thereby reducing the thickness of a package, and a method of fabricating the same. The ball grid array substrate comprises a first external layer which includes first circuit patterns, wire bonding pad patterns, and a window corresponding in size to a first chip mounted therein and wherein the chip is wire-bonded to the wire bonding pad patterns. A second external layer includes second circuit patterns, a portion corresponding in position to the window of the first external layer, and solder ball pad patterns. Second chips mounted on the solder ball pad patterns. An insulating layer interposed between the first and second external layers. The window is formed though the insulating layer at a position corresponding to the window of the first external layer.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: December 9, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jong Jin Lee
  • Publication number: 20080296768
    Abstract: A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process.
    Type: Application
    Filed: December 14, 2006
    Publication date: December 4, 2008
    Inventors: Ramanan V. Chebiam, Valery M. Dubin
  • Patent number: 7459392
    Abstract: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Juan E. Dominguez, Michael L. McSwiney
  • Patent number: 7459387
    Abstract: A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad may include a lower layer of aluminum, copper, or alloys thereof, and an upper layer including at least one film of a metal and/or metallic alloy including nickel, palladium, or alloys thereof, and being deposited by an electroless chemical process.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 2, 2008
    Assignee: STMicroelectronics S.r.L.
    Inventors: Roberto Tiziani, Carlo Passagrilli
  • Patent number: 7456101
    Abstract: Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: November 25, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Sanjay Gopinath, Jeremie Dalton, Jason M. Blackburn, John Drewery, Willibrordus Gerardus Maria van den Hoek
  • Patent number: 7436067
    Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g., ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: October 14, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej Sandhu
  • Patent number: 7435605
    Abstract: A method for fabricating a component having an electrical contact region on an n-conducting AlGaInP-based or AlGaInAs-based outer layer of an epitaxially grown semiconductor layer sequence, in which electrical contact material, which includes Au and at least one dopant, is applied and the outer layer is then annealed. The dopant contains at least one element selected from the group consisting of Ge, Si, Sn and Te. Also, a component is disclosed which includes an epitaxially grown semiconductor layer sequence with an active zone which emits electromagnetic radiation, the semiconductor layer sequence having an n-conducting AlGaInP-based or AlGaInAs-based outer layer, to which an electrical contact region is applied using the method described.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: October 14, 2008
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Illek, Peter Stauss, Andreas Ploessl, Gudrun Diepold, Ines Pietzonka, Wilhelm Stein, Ralph Wirth, Walter Wegleiter
  • Patent number: 7435679
    Abstract: Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Juan E. Dominguez
  • Patent number: 7436066
    Abstract: It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an electrode main entirely or mostly of silver having high reflection efficiency is formed in contact with a nitride semiconductor layer. A semiconductor element comprises a nitride semiconductor layer, an electrode connected to said nitride semiconductor layer, and an insulating film covering at least part of said electrode, wherein the electrode comprises: a first metal film including silver or a silver alloy and in contact with the nitride semiconductor layer; and a second metal film completely covering the first metal film, and the insulating film comprises a nitride film.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: October 14, 2008
    Assignee: Nichia Corporation
    Inventors: Shinya Sonobe, Masakatsu Tomonari, Yoshiki Inoue
  • Patent number: 7435678
    Abstract: Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a noble metal layer or a noble metal oxide layer on a bottom structure.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: October 14, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Sang-jun Choi
  • Publication number: 20080242079
    Abstract: The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Dingying Xu, Amram Eitan
  • Patent number: 7416974
    Abstract: A method of manufacturing a semiconductor device, comprising a first step of forming a layer insulation film on a lower layer wiring provided on a substrate and forming a connection hole in the layer insulation film, a second step of forming an alloy layer composed of a first metallic material constituting the lower layer wiring and a second metallic material different from the first metallic material, on the surface side of the lower layer wiring in the region to be a bottom portion of the connection hole, a third step of sputter-etching the alloy layer, and a fourth step of forming a via in the connection hole in the state of reaching the lower layer wiring; and the semiconductor device.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: August 26, 2008
    Assignee: Sony Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 7416982
    Abstract: Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer formed on the barrier metal layer, and a copper line layer made of a Cu—Ag—Au solid solution. A disclosed example method of manufacturing a semiconductor device reduces and/or prevents contact characteristic degradation of the barrier metal layer with the silicon substrate or the damascene insulating layer. In addition, by forming the copper line layer made of the Cu—Ag—Au solid solution, long term device reliability may be improved.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: August 26, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae-Suk Lee
  • Patent number: 7393785
    Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Uhlenbrock, Eugene P. Marsh
  • Patent number: 7381614
    Abstract: The semiconductor memory device comprises a glue layer defining a cylinder shell, a bottom electrode made of a material of the platinum group and covering the inner face and the outer face of the cylinder shell, a dielectric layer formed over the bottom electrode, and a top electrode positioned over the dielectric layer. The bottom electrode, the dielectric layer, and the top electrode comprise a cell capacitor.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: June 3, 2008
    Assignee: Fujitsu Limited
    Inventor: Nobuyuki Nishikawa
  • Patent number: 7374701
    Abstract: A composition of (i) an organometallic precursor containing a hydrazine compound coordinating with a central metal thereof and (ii) an organometallic compound of a main group metal and a method of forming metal film or pattern using this composition.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: May 20, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Euk Che Hwang, Sang Yoon Lee, Young Hun Byun, Joon Sung Ryu, Hae Jung Son
  • Patent number: 7341947
    Abstract: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the surface of the semiconductor substrate from metal of the at least one metal-containing precursor. The invention also includes semiconductor constructions having metal-containing layers which include one or more of copper, cobalt, gold and nickel in combination with one or more of palladium, platinum, iridium, rhodium and ruthenium.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: March 11, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Chien M. Wai, Hiroyuki Ohde, Steve Kramer
  • Publication number: 20080054472
    Abstract: A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 6, 2008
    Applicant: ASM JAPAN K.K.
    Inventors: Hiroshi SHINRIKI, Hiroaki INOUE
  • Patent number: 7312127
    Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: December 25, 2007
    Assignee: LSI Corporation
    Inventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
  • Patent number: 7288479
    Abstract: A method for improving adhesion of Cu to a Ru layer in Cu metallization. The method includes providing a substrate in a process chamber of a deposition system, depositing a Ru layer on the substrate in a chemical vapor deposition process, and forming a Cu seed layer on the Ru layer to prevent oxidation of the Ru layer. The Cu seed layer is partially or completely oxidized prior to performing a Cu bulk plating process on the substrate. The oxidized portion of the Cu seed layer is substantially dissolved and removed from the substrate during interaction with a Cu plating solution, thereby forming a bulk Cu layer with good adhesion to the underlying Ru layer.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: October 30, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Kenji Suzuki
  • Patent number: 7279231
    Abstract: The present invention relates to a cobalt electroless plating bath composition. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Ramanan V. Chebiam, Valery M. Dubin
  • Patent number: 7273814
    Abstract: A method for forming a ruthenium metal layer includes providing a patterned substrate in a process chamber of a deposition system, where the patterned substrate contains one or more vias or trenches, or combinations thereof, depositing a first ruthenium metal layer on the substrate in an atomic layer deposition process, and depositing a second ruthenium metal layer on the first ruthenium metal layer in a thermal chemical vapor deposition process. The deposited ruthenium metal layer can be used as a diffusion barrier layer, a seed layer for electroplating, or both.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: September 25, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Tsukasa Matsuda
  • Patent number: 7262132
    Abstract: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20070190782
    Abstract: A ruthenium film deposition method is disclosed. In one embodiment of the method, a first ruthenium film is deposited by using a PEALD process until a substrate is substantially entirely covered with the first ruthenium film. Then, a second ruthenium film is deposited on the first ruthenium film by using a thermal ALD process having a higher deposition speed than that of the PEALD process. In the method, a ruthenium metal film having a high density is formed in a short time by combining a PEALD process of depositing a ruthenium film at a low deposition speed and a deposition process of depositing a ruthenium film at a higher deposition speed. Accordingly, it is possible to form a ruthenium film having high density, a smooth surface, good adhesiveness, and a short incubation period.
    Type: Application
    Filed: February 14, 2007
    Publication date: August 16, 2007
    Inventor: Hyung-Sang Park
  • Patent number: 7253102
    Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Mark Visokay, Thomas M. Graettinger, Steven D. Cummings
  • Patent number: 7253103
    Abstract: Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: August 7, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura
  • Patent number: 7238611
    Abstract: A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein the second thermal process includes a first step performed at 600˜700 degrees centigrade for 10˜60 seconds and a second step performed at 750˜850 degrees centigrade for 10˜60 seconds. If the metal layer is selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal process is performed at 450˜550 degrees centigrade for 10˜60 seconds.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: July 3, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Min-Hsian Chen, Ching-Hsing Hsieh
  • Patent number: 7229913
    Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Kum Foo Leong, Chee Key Chung, Kian Sin Sim
  • Patent number: 7229917
    Abstract: A film-formation method for a semiconductor process includes seed film formation and main film formation. In the seed film formation, a metal-containing raw material gas and a first assist gas to react therewith are supplied into a process container, which accommodates a target substrate having an underlying layer, thereby forming a seed film on the underlying layer by CVD. In the main film formation, the raw material gas and a second assist gas to react therewith are supplied into the process container, thereby forming a main film on the seed film by CVD. The seed film formation includes first and second periods performed alternately and continuously. In each first period, the raw material gas is supplied into the process container while the first assist gas is stopped. In each second period, the first assist gas is supplied into the process container while the raw material gas is stopped.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: June 12, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Takahito Umehara, Masahiko Tomita, Hirotake Fujita, Kazuhide Hasebe
  • Patent number: 7226861
    Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: June 5, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Uhlenbrock, Eugene P. Marsh
  • Patent number: 7220669
    Abstract: Methods are provided for forming uniformly thin layers in magnetic devices. Atomic layer deposition (ALD) can produce layers that are uniformly thick on an atomic scale. Magnetic tunnel junction dielectrics, for example, can be provided with perfect uniformity in thickness of 4 monolayers or less. Furthermore, conductive layers, including magnetic and non-magnetic layers, can be provided by ALD without spiking and other non-uniformity problems. The disclosed methods include forming metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal. The oxides tend to maintain more stable interfaces during formation.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: May 22, 2007
    Assignee: ASM International N.V.
    Inventors: Juha Hujanen, Ivo Raaijmakers
  • Patent number: 7220665
    Abstract: Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H2 plasma treatment, and depositing a capping adhesion/barrier layer on the core conductive layer after the H2 plasma treatment. The multilayer dielectric structure provides an insulating layer for around the core conducting layer and at least one sacrificial layer for processing. The H2 plasma treatment removes unwanted oxide from the surface region of the core conducting layer such that the interface between the core conducting layer and the capping adhesion/barrier is substantially free of oxides. In an embodiment, the core conducting layer is copper with a titanium nitride or zirconium capping adhesion/barrier layer.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: May 22, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 7214602
    Abstract: A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further includes annealing the layer of iridium, forming a dielectric layer on the layer of iridium, and forming a conductive layer on the dielectric layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 7214611
    Abstract: The present invention first obtains a nano-metal line by an e-beam lithography and an electroless plating, and imprints the line into a material with low-K to obtain a damascene metal line with low cost and high throughput, as a future solution for a metallization process for a general low-K metal damascene structure through CMP.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: May 8, 2007
    Assignee: National Tsing Hua University
    Inventors: Jen Fu Liu, Yung Jen Hsu, Jiann Heng Chen, Fon Shan Huang
  • Patent number: 7211509
    Abstract: Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc,
    Inventors: Sanjay Gopinath, Jeremie Dalton, Jason M. Blackburn, John Drewery, Willibrordus Gerardus Maria van den Hoek
  • Patent number: 7199043
    Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: April 3, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Kyun Park
  • Patent number: 7163835
    Abstract: A method is described for producing thin semiconductor films on a substrate by contacting a substrate with a solution containing a metal salt, a source of a Group VIa element, and chelating agent, and a noble metal in its elemental form. The resulting semiconductor films are useful for electronic and photovoltaic applications.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 16, 2007
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: Jeffrey Scott Meth
  • Patent number: 7157383
    Abstract: After cleaning a surface of a silicon substrate (1), impurities and natural oxide film existing on the silicon substrate (1) are removed by soaking the silicon substrate (1) in a 0.5%-by-volume HF aqueous solution for 5 minutes. The silicon substrate (1) is rinsed (cleaned) with ultrapure water for five minutes. Then, the silicon substrate (1) is soaked for 30 minutes in azeotropic nitric acid heated to an azeotropic temperature of 120.7° C. In this way, an extremely thin chemical oxide film (5) is formed on the surface of the silicon substrate (1). Subsequently, a metal film (6) (aluminum-silicon alloy film) is deposited, followed by heating in a hydrogen-containing gas at 200° C. for 20 minutes. Through the heat processing in the hydrogen-containing gas, hydrogen reacts with interface states and defect states in the chemical oxide film (5), causing disappearance of the interface states and defect states. As a result, the quality of the film can be improved.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: January 2, 2007
    Assignee: Japan Science and Technology Agency
    Inventor: Hikaru Kobayashi
  • Patent number: 7105401
    Abstract: A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor, wherein the capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer layer disposed between the lower electrode and the thin dielectric layer, the buffer layer including a metal oxide of Group 3, 4, or 13. In an embodiment, the method of fabricating includes absorbing CO on a surface of a lower electrode of a platinum group metal, placing the lower electrode under a reducing atmosphere to produce a lattice oxygen, using the lattice oxygen to form a thin dielectric layer by performing an ALD process using a precursor for the thin dielectric layer, and forming an upper electrode of a platinum group metal on the thin dielectric layer.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: September 12, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Yo-sep Min, Young-jin Cho
  • Patent number: 7081405
    Abstract: A package module of an IC device comprises a substrate, at least one semiconductor device, and an interconnected layer. The substrate has a first surface and a second surface, wherein the substrate further contains a plurality of metal plugs, which penetrate the substrate and connect the first surface and the second surface. The semiconductor device is located on the first surface of the substrate, wherein the semiconductor device contains a plurality of metal pads, each of which is connected to one of the metal plugs. The interconnected layer is formed on the second surface of the substrate, wherein the interconnected layer is comprised of a plurality of metal circuits, a plurality of land pads, and a plurality of via pads, wherein each of the metal plugs is connected to one of the metal circuits.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: July 25, 2006
    Assignee: Via Technologies, Inc.
    Inventor: Ray Chien
  • Patent number: 7067407
    Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a gaseous inorganic reducing agent, thereby forming a metal layer. In preferred arrangements, the reducing agent comprises of thermal hydrogen (H2), hydrogen radicals (H*) and/or carbon monoxide (CO).
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: June 27, 2006
    Assignee: ASM International, N.V.
    Inventors: Juhana Kostamo, Maarten Stokhof
  • Patent number: 7064050
    Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: June 20, 2006
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Christophe Detavernier, Rajarao Jammy, Katherine L. Saenger
  • Patent number: 7049237
    Abstract: A planarization method includes providing a second and/or third Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes an oxidizing gas.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: May 23, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Stefan Uhlenbrock, Don Westmoreland
  • Patent number: 7041596
    Abstract: An excited surfactant species is created by generating plasma discharge in a surfactant precursor gas. A surfactant species typically includes at least one of iodine, led, thin, gallium, and indium. A surface of an integrated circuit substrate is exposed to the excited surfactant species to form a plasma-treated surface. A ruthenium thin film is deposited on the plasma-treated surface using a CVD technique.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: May 9, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Jeremie James Dalton, Sanjay Gopinath, Jason M. Blackburn, John Stephen Drewery
  • Patent number: 7033930
    Abstract: Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate, forming a silver layer overlying the interface layer, annealing the substrate to form an intermetallic layer between the silver layer and the interface layer, the silver layer is in intimate contact with the intermetallic layer, and forming a protection layer overlying the silver layer. Other interconnect structures and processes are also described.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Michael Kozhukh, Oleg Rashkovskiy
  • Patent number: 7026243
    Abstract: A method of forming a conductive metal silicide by reaction of metal with silicon is described. A method includes providing a semiconductor substrate with an exposed elemental silicon-containing surface. At least one of a nitride, boride, carbide, or oxide-comprising layer is atomic layer deposited onto the exposed elemental silicon-containing surface to a thickness no greater than 15 Angstroms. This ALD-deposited layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal-rich silicide is deposited onto the plasma-exposed layer. Metal of the conductive reaction layer is reacted with elemental silicon of the substrate effective to form a conductive metal silicide-comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Cem Basceri