Abstract: In a method of forming an electrically conductive lamination pattern, an insulating film is formed on a surface of a chromium-containing bottom layer, before an aluminum-containing top layer is formed over the insulating film, so that the insulating film separates the aluminum-containing top layer from the chromium-containing bottom layer. A first selective wet etching process is carried out for selectively etching the aluminum-containing top layer with a first etchant. A second selective wet etching process is carried out for selectively etching the chromium-containing bottom layer with a second etchant in the presence the insulating film which suppresses a hetero-metal-contact-potential-difference between the chromium-containing bottom layer and the aluminum-containing top layer during the second selective wet etching process.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.

Abstract: A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper can be deposited facilitates conventional electrolytic processing. An ultra-thin adhesion layer is applied to a degassed, pre-cleaned substrate. The degassed and pre-cleaned substrate is exposed to a precursor gas containing the adhesion layer, optionally deposited by a plasma-assisted CVD process, resulting in the deposition of an adhesion layer inside the exposed feature. The treated wafer is then coated with a diffusion barrier material, such as ruthenium, so that the adhesion layer reacts with incoming diffusion barrier atoms. The adhesion layer may be selectively bias-sputter etched prior to the deposition of the diffusion barrier layer. A copper layer is then deposited on the diffusion barrier layer.

Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

Abstract: A process produces a layer of material which functions as a copper barrier layer, adhesion layer and a copper seed layer in a device of an integrated circuit, particularly in damascene or dual damascene structures. The method includes a step of depositing a diffusion barrier layer over a dielectric, a step of depositing a layer of graded metal alloy of two or more metals, and a step of depositing a copper seed layer, which step is essentially a part of the step of depositing the alloy layer.

Abstract: The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The desired layers can be formed by initially depositing a metal-containing layer which comprises metal and halogen atoms. Subsequently, trialkylaluminum is utilized to remove the halogen atoms from the layer. The layer remaining after removal of the halogen atoms can comprise, consist essentially, or consist of any suitable metal, and in particular aspects can consist essentially of, or consist of, titanium or titanium/aluminum.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 ? to 300 ?, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 ? to 3000 ?, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about ?4V to ?5V, having a pulse width of between about 75 nsec to 1 ?sec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 ?sec.

Abstract: Embodiments of the present invention generally relate to an apparatus and method of integration of titanium and titanium nitride layers. One embodiment includes providing one or more cycles of a first set of compounds, providing one or more cycles of a second set of compounds, and providing one or more cycles of a third set of compounds. One cycle of the first set of compounds includes introducing a titanium precursor and a reductant. One cycle of the second set of compounds includes introducing the titanium precursor and a silicon precursor. One cycle of the third set of compounds includes introducing the titanium precursor and a nitrogen precursor. Another embodiment includes depositing a titanium layer utilizing titanium halide. Then, a passivation layer is deposited over the titanium layer utilizing titanium halide. The passivation layer may comprise titanium silicide, titanium silicon nitride, and combinations thereof.

Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

Abstract: A semiconductor devices includes: a diffusion barrier layer composed of ternary compound elements formed on a substrate, wherein the diffusion barrier contains ruthenium, titanium and oxygen; and a capacitor formed on the diffusion barrier layer, wherein the capacitor includes a bottom electrode formed on the diffusion barrier layer, a dielectric layer formed on the bottom electrode and a top electrode formed on the dielectric layer.

Abstract: A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.

Abstract: Electronic components such as semiconductor wafer VLSI and ULSI integrated circuit devices are provided having a robust barrier layer in the device interconnects. The robust barrier layer provides excellent step coverage, low resistance and enhanced adhesion to CVD copper and the interconnect has a double structure of a layer of a barrier material and a metal layer thereon. The metal layer is preferably tungsten and is formed by replacing silicon or other such atoms on the surface of the barrier layer with tungsten metal. A layer of silicon can be formed on the barrier layer, silicon atoms can be formed on the surface by reacting the barrier layer with a silicon containing reactant or a silicon containing barrier layer can be used.

Abstract: A process for providing one or more protected copper elements on a surface of a workpiece is set forth. In accordance with the process, a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for subsequent electroplating processes, a separate seed layer is applied over the surface of the barrier layer. One or more copper elements are then electroplated on selected portions of the seed layer or, if suitable, the barrier layer. If used, the seed layer is then substantially removed. At least a portion of a surface of the barrier layer is rendered unplatable while leaving the copper elements suitable for electroplating. A protective layer is then electroplated onto surfaces of the one or more copper elements.

Abstract: A method for handling a thin silicon wafer including the steps of successively forming on a surface of the wafer a first protection layer, a first etch stop layer, and an external layer; forming on a surface of a support wafer a gluing layer of the same material as the external layer of the wafer, the surface of the support wafer including a plurality of pads, the respective upper portions of which are substantially planar and coplanar; fastening, by direct gluing, the external layer of the wafer and the gluing layer of the support wafer; processing the wafer to form circuits therein; depositing a second protection layer on the wafer surface which is not glued to the support wafer; and removing by an etch process the material forming the external layer of the wafer and the gluing layer of the support wafer.

Abstract: A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through a dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.

Abstract: The adhesion properties of a metal interconnect structure are enhanced by selectively depositing a barrier layer component having good adhesion to an underlying metal on the bottom surface of a via. Then, a further barrier layer having superior adhesion characteristics for the dielectric is formed on the dielectric sidewalls of the via, so that excellent adhesion to the dielectric and the underlying metal is achieved. The selectivity of the deposition may be accomplished by exploiting the capabilities of modem IPVD tools.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.

Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.

Abstract: Disclosed is a method for forming metal wiring in a semiconductor device. The method comprises forming a TiN thin layer on a semiconductor substrate by using Ti compound containing a halogen element which corresponds to a 17 group element in the periodic table and NH3 reactant and adsorbing halogen atoms to the surface of the TiN thin layer; and forming a copper (Cu) thin layer on the TiN thin layer by using the adsorbed halogen atoms as catalyst. Wiring can be carried out in situ in a single chamber system in order to obtain excellent interface characteristics and a short process time.

Abstract: A semiconductor wafer including a substrate, a copper dual damascene structure positioned on the substrate, a dielectric layer covering the copper dual damascene structure, and a via hole positioned in the dielectric layer, the hole continuing to a surface of the copper layer. First, a tantalum nitride (TaN) layer is formed on a bottom surface within the via hole and on walls within the via hole. A titanium nitride (TiN) layer is then formed on the tantalum nitride layer. By performing a chemical vapor deposition (CVD) process, a tungsten layer is formed to cover a surface of the titanium nitride layer as well as to fill the via hole. Finally, a chemical mechanical polishing (CMP) process is performed to make a top of the tungsten layer in the via hole aligned with the surface of the dielectric layer so as to form a tungsten plug.

Abstract: In a semiconductor device with a via contact including a barrier metal layer and a method for fabricating the same, a lower metal interconnection is formed over a substrate. An ILD is formed on the lower metal interconnection and has a lower barrier layer and an upper barrier layer that have an etch selectivity with respect to each other. An upper metal interconnection is formed over the ILD and is separated from the lower metal interconnection by the ILD. A via contact plug penetrates the ILD to connect the lower and upper metal interconnections. The via contact plug is formed such that a portion crossing the lower barrier layer is formed to have a greater width as compared to a portion crossing the upper barrier layer. The barrier metal layer, which is formed to encompass sidewalls and a bottom of an inner metal layer of the via contact plug, forms a discontinuous part which does not exist at the portion crossing the lower barrier layer.

Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Abstract: A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.

Abstract: A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.

Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: A multilayered copper structure has been provided for improving the adhesion of copper to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The multilayered copper structure comprises a thin high-resistive copper layer to provide improved adhesion to the underlying diffusion barrier layer, and a low-resistive copper layer to carry the electrical current with minimum electrical resistance. The invention also provides a method to form the multilayered copper structure.

Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.

Abstract: In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers.

Abstract: A method for fabricating a metal silicide layer includes forming a dielectric layer on a substrate, followed by forming a polysilicon material conductive layer on the dielectric layer. An adhesion layer is then formed on the conductive layer, wherein the adhesion layer is a nitrogen rich layer or a nitrogen ion implanted layer. A metal silicide layer is then formed on the adhesion layer. The adhesion between the metal silicide layer and the conductive layer is more desirable due the adhesion layer.

Abstract: A semiconductor device having a bump electrode comprising a substrate having a dielectric layer formed thereon, an aluminum contact pad on the substrate wherein at least a portion of the aluminum contact pad is exposed through the dielectric layer on the substrate. The aluminum contact pad is provided with an under bump metallurgy including a aluminum layer formed on the exposed portion of the aluminum contact pad, a nickel-vanadium layer formed on the aluminum layer and a titanium layer formed on the nickel-vanadium layer. A gold bump formed on the titanium layer acts as the bump electrode.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.

Abstract: This invention aims to provide a protecting method for a semiconductor wafer which can prevent breakage of a semiconductor wafer even when a semiconductor wafer is thinned to a thickness of 200 &mgr;m or less, and a surface protecting adhesive film for a semiconductor wafer used in the protecting method.

Abstract: A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the conductive lines (118) during subsequent processing steps. The metal cap layer (120) comprises a material other than the conductive line (118) material that is resistant to oxidation. The structure (100) is particularly beneficial for MRAM devices.

Abstract: A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.

Abstract: There is a method for forming a multilayer electronic device. The method has the following steps: a) depositing a thin molecular layer on an electrically conductive substrate and b) depositing metal atoms or ions on the thin molecular layer at an angle of about 60 degrees or less with respect to the plane of the exposed surface of the thin molecular layer.

Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: A method for forming an adhesion/barrier liner to improve adhesion and a specific contact resistance of semiconductor wafer metal interconnect including providing a semiconductor wafer having a process surface including at least one anisotropically etched opening extending through at least one dielectric insulating layer and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least 400° C.; cleaning the at least one anisotropically etched opening according to a plasma assisted reactive pre-cleaning process (RPC) including a supplying a fluorine containing gas to maintain the plasma; and, blanket depositing at least a first adhesion/barrier layer.

Abstract: A method has been provided for improving the adhesion of copper to a nitrided metal diffusion barrier material, such as TiN, in an integrated circuit substrate. The method provided a multilayered diffusion barrier structure, comprising a conducting diffusion barrier layer and a poorly conducting adhesion-promoter layer in selected locations. The formation of a poorly conducting adhesion-promoter layer in selected locations permits the optimization of both contact resistance and adhesion property. The poorly conducting adhesion-promoter layer is formed either by the partial incorporation of oxygen into the diffusion barrier or by deposition in an oxygen ambient.

Abstract: A method is provided for promoting adhesion of CVD copper to diffusion barrier material in integrated circuit manufacturing. The method uses a two-step CVD copper metallization process. Following deposition of a diffusion barrier layer on the IC substrate, a first layer of CVD copper is deposited on the barrier material. The first layer is preferably thin (less than 300 Å) and deposited using a precursor which yields an adherent conforming layer of copper. The suggested precursor for use in depositing the first layer of CVD copper is (hfac)Cu(1,5-Dimethylcyclooctadiene). The first layer of CVD copper serves as a “seed” layer to which a subsequently-deposited “fill” or “bulk” layer of CVD copper will readily adhere. The second copper deposition step of the two-step process is the deposit of a second layer of copper by means of CVD using another precursor, different from (hfac)Cu(1,5-Dimethylcyclooctadiene).