Abstract: The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut generated by etching. The structure further comprises an underlying layer under the conductive line. The underlying layer includes Ni, Cu or Pt. The conductive line includes gold or copper. The at least one patterned conductive layer includes at least Ti/Cu. The protection layer includes electro-less plating Sn, Au, Ag or Ni.

Abstract: An electrode for a photoelectric conversion device, a method of preparing the same and a photoelectric conversion device including the same. In one embodiment, an electrode for a photoelectric conversion device includes a transparent conductive layer, a metal electrode layer and an intermediate electrode layer. The transparent conductive layer is formed on a substrate. The metal electrode layer is disposed on the transparent conductive layer to have a pattern. The intermediate electrode layer is interposed between the transparent conductive layer and the metal electrode layer to join the transparent conductive layer and the metal electrode layer. Accordingly, the photoelectric conversion device is enhanced.

Abstract: According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Nb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element.

Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.

Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.

Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.

Abstract: Provided is a method for manufacturing a semiconductor device having favorable electric characteristics with a high yield. A groove and/or a contact hole reaching a semiconductor region or a conductive region is formed in an insulating film covering the semiconductor region or the conductive region; a first conductive film is formed in the groove and/or the contact hole; the first conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas and to an atmosphere containing water to be fluidized partially or entirely; and a second conductive film is formed over the first conductive film.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: The present invention provides a method for manufacturing a semiconductor memory element including a chalcogenide material layer and an electrode layer, each having an improved adhesion, and a sputtering apparatus thereof. One embodiment of the present invention is the method for manufacturing a semiconductor memory element including: a first step of forming the chalcogenide material layer (113); and a second step of forming a second electrode layer (114b) on the chalcogenide material layer (113) by sputtering through the use of a mixed gas of a reactive gas and an inert gas, while applying a cathode voltage to a target. In the second step, introduction of the reactive gas is carried out at a flow rate ratio included in a hysteresis area (40) appearing in the relationship between a cathode voltage applied to the cathode and the flow rate ratio of the reactive gas in the mixed gas.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.

Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.

Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

Abstract: Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.

Abstract: There is provided a silicon carbide semiconductor device equipped with an ohmic electrode that exhibits both low contact resistance and favorable surface conditions, the silicon carbide semiconductor device including a p-type silicon carbide single crystal, and an ohmic electrode for the p-type silicon carbide single crystal, wherein the ohmic electrode includes an alloy layer containing at least titanium, aluminum and silicon, and ratios of titanium, aluminum, and silicon in the alloy layer are Al: 40 to 70% by mass, Ti: 20 to 50% by mass, and Si: 1 to 15% by mass.

Abstract: An electronic component includes at least one patterned layer of an electrically conductive material on a substrate, a protective layer of a second material being deposited on the patterned layer of the electrically conductive material. The second material is baser than the electrically conductive material of the patterned layer. In a method for producing the electronic component, the patterned layer of the electrically conductive material is deposited on the substrate in a first step, and the protective layer of the second material, which is baser than the electrically conductive material of the patterned layer, is deposited on the patterned layer in a second step.

Abstract: Provided are a photoresist composition having superior adhesion to an etch target film, a method of forming a pattern by using the photoresist composition, and a method of manufacturing a thin-film transistor (TFT) substrate. The photoresist composition includes an alkali-soluble resin; a photosensitive compound; a solvent; and 0.01 to 0.1 parts by weight of a compound represented by Formula 1: wherein R is one of hydrogen, an alkyl having 1 to 10 carbon atoms, a cycloalkyl having 4 to 8 carbon atoms, and a phenyl group.

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: A method of forming a contact in a semiconductor device provides a titanium contact layer in a contact hole and a MOCVD-TiN barrier metal layer on the titanium contact layer. Impurities are removed from the MOCVD-TiN barrier metal layer by a plasma treatment in a nitrogen-hydrogen plasma. The time period for plasma treating the titanium nitride layer is controlled so that penetration of nitrogen into the underlying titanium contact layer is substantially prevented, preserving the titanium contact layer for subsequently forming a titanium silicide at the bottom of the contact.

Abstract: Disclosed is a semiconductor device including: a substrate; a wiring layer formed on the substrate and made of copper or a copper alloy; a copper diffusion barrier film formed on the wiring layer and made of an amorphous carbon film formed by CVD using a processing gas containing a hydrocarbon gas; and a low-k insulating film formed on the copper diffusion barrier film.

Abstract: The semiconductor manufacturing method comprises the step of forming a metal alloy film of an alloy of a metal of Ni or others and a noble metal over a semiconductor substrate containing a region where silicon is partially exposed; the step of selectively reacting the silicon in the region and the metal alloy film by thermal processing to form metal silicide film containing the metal of Ni or others and the noble metal on the region; and the step of removing the metal alloy film remaining unreacted by using a solution containing hydrogen peroxide with a transition metal, which has higher ionization tendency than the metal of Ni or others, dissolved in.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.

Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Abstract: Disclosed is a semiconductor device comprising a p-type SiC semiconductor and an ohmic electrode having an Ni/Al laminated structure provided on the p-type SiC semiconductor. The semiconductor device simultaneously has improved contact resistance and surface roughness in the ohmic electrode. The semiconductor device comprises an ohmic electrode (18) comprising a nickel (Ni) layer (21), a titanium (Ti) layer (22), and an aluminum (Al) layer (23) stacked in that order on a p-type silicon carbide semiconductor region (13). The ohmic electrode (18) comprises 14 to 47 atomic % of a nickel element, 5 to 12 atomic % of titanium element, and 35 to 74 atomic % of an aluminum element, provided that the atomic ratio of the nickel element to the titanium element is 1 to 11.

Abstract: A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.

Abstract: An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.

Abstract: Provided is a method for manufacturing a dual gate in a semiconductor device. The method includes forming a gate insulating layer and a gate conductive layer on a semiconductor substrate, forming a diffusion barrier layer on the gate conductive layer, forming a barrier metal layer on the diffusion barrier layer, depositing a first gate metal layer on the barrier metal layer, forming a metal nitride barrier layer on a surface of the first gate metal layer by supplying nitrogen (N2) plasma on the first gate metal layer, forming a second gate metal layer on the metal nitride barrier layer, and forming a hard mask layer on the second gate metal layer.

Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.

Abstract: After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.

Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Abstract: The amount of atoms diffused into a substrate may be made uniform or the thickness of a thin film may be made uniform in a low species utilization process by stopping the flow of gas into a reaction chamber during the low species utilization process. Stopping the flow of gas into a reaction chamber may entail closing the gate valve (the valve to the vacuum pump), stabilizing the pressure within the reaction chamber, and maintaining the stabilized pressure while stopping the gas flowing into the chamber. Low species utilization processes include the diffusion of nitrogen into silicon dioxide gate dielectric layers by decoupled plasma nitridation (DPN), the deposition of a silicon dioxide film by rapid thermal processing (RTP) or chemical vapor deposition (CVD), and the deposition of silicon epitaxial layers by CVD.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes the following step: a step (S10) of forming a GaN-based semiconductor layer, a step (S20) of forming an Al film on the GaN-based semiconductor layer, a step (S30, S40) of forming a mask layer composed of a material having a lower etching rate than that of the material constituting the Al film, a step (S50) of partially removing the Al film and the GaN-based semiconductor layer using the mask layer as a mask to form a ridge portion, a step (S60) of retracting the positions of the side walls at the ends of the Al film from the positions of the side walls of the mask layer, a step (S70) of forming a protection film composed of a material having a lower etching rate than that of the material constituting the Al film on the side surfaces of the ridge portion and on the upper surface of the mask layer, and a step (S80) of removing the Al film to remove the mask layer and the protection film formed on the upper surface of t

Abstract: An electrode of a semiconductor device includes a TiCN layer and a TiN layer. A method for fabricating an electrode of a semiconductor device includes preparing a substrate, forming a TiCN layer, and forming a TiN layer.

Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.

Abstract: A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion barrier layers, on a substrate by using a vapor deposition process with a tantalum halide precursor compound, a silicon precursor compound, and an optional nitrogen precursor compound.

Abstract: A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film; and a barrier layer provided between the first interconnection layer and the second interconnection layer in an interlevel connection opening formed in the interlevel insulation film. The barrier layer includes a first sublayer provided in contact with the first interconnection layer to reduce a contact resistance, a second sublayer provided in contact with the second interconnection layer to improve a bonding strength, and a third sublayer provided between the first sublayer and the second sublayer. The first sublayer, the second sublayer and the third sublayer are, for example, a first tantalum sublayer, a second tantalum sublayer and a tantalum nitride sublayer, respectively.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: A low on-resistance silicon carbide semiconductor device is provided to include an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. Specifically, the silicon carbide semiconductor device includes at least an insulating film, formed on an upper surface of a silicon carbide substrate, and includes at least an ohmic electrode, formed of an alloy comprising nickel and titanium, or formed of a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide substrate.

Abstract: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The first conductor layer makes contact with the surface of the silicon substrate and includes aluminum and silicon. The second conductor layer makes contact with the first conductor layer and includes titanium. The third conductor layer is separated from the first conductor layer by the second conductor layer and includes nickel.

Abstract: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.

Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.

Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches.

Abstract: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure >50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.

Abstract: Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer.

Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

Abstract: A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer and the nitrogen-rich region form a barrier layer between the material layer and the conductor.

Abstract: Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.