Abstract: A method for manufacturing DRAM capacitor that utilizes a self-aligned etching process for fabricating the lower electrode of a capacitor instead of a conventional photolithographic process whose processing accuracy is dependent upon the resolution of light source used. Using a polysilicon layer as a mask and a silicon nitride layer as an etching stop layer, the self-aligned etching process is carried out to form a rather narrow contact window in the insulating layer. By forming this narrow contact window, proper isolation between a word line and its neighboring conductive layer is ensured. Hence, device reliability is increased.

Abstract: A method for increasing landing pad area is disclosed. Firstly, providing a fundamental structure, wherein shallow trench isolation (STI) is used and acting as an electrical isolation inside of substrate. Moreover, there are at least two gates with an isolation layer on top of the substrate and covered with a dielectric layer. Between the neighboring gates there is a contact hole that penetrates the dielectric layer from the top of the dielectric layer to the substrate. Taking this fundamental structure as the starting point for forming a conductor within the contact hole. Etching back the dielectric layer and exposing its top surface and a portion of sidewalls. Finally, a protection layer on top of the exposed portion of sidewalls of the conductor is formed in order to expand the landing pad area. After all, one would still be able to increase the landing pad area even though the distance between two gates is rather small.

Abstract: A method for creating a metal filled, high aspect ratio, contact opening, in thick insulator layers, allowing contact between a metal interconnect structure and a region of a semiconductor substrate, has been developed. The process features creating a stacked contact hole opening, comprised of a upper contact hole opening, of a specific diameter size, overlying a lower contact hole opening, having an opening larger in diameter than the opening used for the upper contact hole opening. The lower contact hole opening is created via an anisotropic RIE procedure, followed by a wet etch procedure, used to enlarge the diameter of the lower contact hole opening. The upper contact hole opening, created using an anisotropic RIE procedure, is formed using the original diameter opening, used previously for the pre-wet etched, lower contact hole opening, and is easily aligned to a metal filled, enlarged lower contact hole opening.

Abstract: A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.

Abstract: An etching process is provided for etching through a tungsten silicide layer and an underlying polysilicon layer during the formation of a control gate in a semiconductor device. The etching process prevents the formation of a tungsten silicide residue while etching a layer of tungsten silicide, by employing a plasma that exhibits strong physical sputtering capabilities. The plasma effectively etches away exposed portions of the silicide layer, especially in narrow patterned regions. The plasma exhibits an etching selectivity (ratio of tungsten silicide etch rate to polysilicon etch rate) that is less than about 1.0.

Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.

Abstract: A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief layer to expose a desired buried contact area of the substrate; c) masking over the stress relief layer and over the desired buried contact area; d) with the masking in place, exposing the substrate to oxidation conditions effective to grow field oxide regions in unmasked areas of the substrate; e) after forming the field oxide regions, removing the masking from the substrate and effectively leaving the buried contact area exposed; f) providing a layer of electrically conductive material over field oxide and exposed buried contact area; and g) patterning the conductive material layer into a conductive line which overlies both field oxide and the buried contact area.

Abstract: A semiconductor processing method of reducing thickness depletion of a nitride layer at a junction of different underlying layers includes, a) providing a substrate, the substrate comprising a first material and a second material, the first and second materials joining at a surface junction, the first and second materials being different from one another; b) exposing the substrate to a nitrogen containing gas under pressure and elevated temperature conditions effective to nitridize an outer portion of both the first and second materials with the nitrogen containing gas to provide a nitrogen containing nucleation layer at the outer portion of both of the first and second materials over the surface junction; and c) chemical vapor depositing a nitride layer atop the nucleation layer over the first and second materials and the surface junction.

Abstract: A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer.

Abstract: A semiconductor fabrication method is provided for fabricating a data-storage capacitor for DRAM (dynamic random-access memory) device, which can allow the resulting capacitor to have a large capacitance and also allows a higher yield rate for the DRAM manufacture process. This method is used on a semiconductor substrate that is already formed with a transfer field effect transistor having a gate and a pair of source/drain regions. By this method, a dielectric layer, an etch-end layer, and an insulating layer are successively formed over the dielectric layer. Then, a contact hole is formed to expose a selected one of the source/drain regions of the transistor. In this contact hole and over the insulating layer, a main conductive trunk is formed, which is substantially T-shaped in cross section, with the root thereof being electrically connected to the source/drain region. Subsequently, an overhanging conductive branch is formed to the main conductive trunk.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate oxide layer. The first polysilicon layer is etched away where it is not covered by a mask to form a floating gate. Source and drain regions associated with the floating gate are formed within the substrate. An oxide layer is deposited overlying the floating gate and the substrate. The oxide layer is polished away until the top of the oxide layer is even with the top of the floating gate. A second polysilicon layer is deposited overlying the oxide layer and the first polysilicon layer of the floating gate wherein the second polysilicon layer has a smooth surface. An interpoly dielectric layer is deposited overlying the second polysilicon layer. A third polysilicon layer is deposited overlying the interpoly dielectric layer.

Abstract: A contactless, nonvolatile metal oxide semiconductor memory device having a rectangular array of memory cells interconnected by word-lines in the row direction of the array and bit-lines in the column direction of the array. Each memory cell has a structurally asymmetrical pair of floating gate, MOS field effect transistors of the same row that share a common source region (bit line) within a semiconductor substrate. The asymmetry of the structure of the floating gates of the two transistors enables programming/reading and monitoring of the cell to be effected simultanetdsly. The structure of the floating gate is also responsible for a relatively large capacitive coupling between the floating gates and the control gate (word line) which lies above them. Since the floating gates essentially serve as a mask for implantation of program/read and monitor drain regions within the substrate, fabrication of the device incorporates self-aligning process steps.

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.

Abstract: Amorphous silicon layers are formed on an n-type single-crystal/poly-crystal layer and a p-type single-crystal/poly-crystal layer, and titanium is sputtered on the amorphous silicon layers; although the n-type dopant impurity are piled on the n-type single-crystal/poly-crystal layers, the amorphous silicon layers takes the piles of n-type dopant impurity thereinto, and promote the silicidation of the titanium layer.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: Electrical interconnection with studs is formed by depositing conductive stud material in contact holes in a dielectric layer; patterning the conductive stud material and removing a shallow portion of the dielectric layer surrounding the stud material; depositing a thin layer of dielectric material over the conductive stud and first dielectric layer; forming a trench in the dielectric layers and over the top of the stud material; and depositing conductive material in the trench.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to apposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

Abstract: A semiconductor device having a nitrogen-bearing gate electrode and method of fabricating the same is provided. Consistent with the invention, a semiconductor device is formed by forming a gate oxide layer on a surface of a substrate. Over the gate oxide layer is formed a lower polysilicon layer with a first nitrogen concentration. Over the lower polysilicon layer, there is formed an upper polysilicon layer with a second nitrogen concentration less than the first nitrogen concentration. The two polysilicon layers are used to form at least one gate electrode.

Abstract: A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.

Abstract: A method is disclosed for forming a buried contact within an integrated circuit ("IC"). Initially, a gate oxide layer is deposited onto a surface of a silicon substrate. A first polysilicon layer is deposited onto the gate oxide layer using an ionized cluster beam ("ICB") technique. The first polysilicon layer and the gate oxide layer are patterned and etched at predetermined locations, exposing the underlying silicon substrate surface at these locations. A small amount of undesirable native oxide grows on the exposed substrate surface. This oxide represents an unwanted impedance, which degrades IC device performance. The ICB machine is then used to deposit a second layer of polysilicon on the silicon substrate, including over the oxide layer regions and over the exposed silicon substrate surface at the predetermined locations. This second polysilicon deposition step breaks up and removes the unwanted native oxide from the silicon substrate.

Abstract: A method of making a semiconductor device having a structure capable of obtaining an increased alignment margin for a mask without any increase in the area of the semiconductor device is shown by forming a contact plug on a drain while forming a contact pad on a source, without forming contact plugs on both the source and the drain in a simultaneous manner. The contact pad has an upper portion partially overlapping with a portion of an insulating film surrounding a contact hole in which the contact pad is buried. Accordingly, it is possible to easily carry out the contact process.

Abstract: The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

Abstract: Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

Abstract: Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase.

Abstract: The method of forming a polycide layer in a semiconductor device is provided. The method of forming a polycide layer comprises the steps of depositing a doped polysilicon layer on a silicon substrate on which an insulating layer is formed and depositing a tungsten silicide on the doped polysilicon layer, the doped polysilicon layer comprises a lower, intermediate and upper doped polysilicon layers sequentially formed, also the intermediate polysilicon layer has a lower concentration of impurity ion than the upper and lower polysilicon layers. The impurity ions contained within the upper and lower polysilicon layers are diffused into the intermediate layer having the lowest concentration of impurity during a subsequent annealing process, therefore the impurity ions contained within the upper and lower polysilicon layers are not diffused to the junction and the tungsten silicide.

Abstract: This invention proposes a new process to form MOS transistor with a gate-side air-gap structure and an extension ultra-shallow S/D junction for high speed devices. After growing the thin gate oxide film on silicon substrate, a stacked-amorphous-Si (SAA) film is deposited. A thin CVD oxide film is deposited and then patterned. The top two amorphous-Si layers are etched back and then form the nitride spacers. The pad CVD oxide film is removed by diluted HF solution followed by S/D/G implant. High temperature thermal oxidation process is used to convert the bottom amorphous-Si layers outside the nitride spacers into thermal oxide and simultaneously to form shallow junction. The nitride spacers are removed and then the low energy/high dose ion implantation is performed for extension S/D junction. The bottom amorphous-Si layer is etched back and then RTP anneal in N.sub.2 O or NO ambient is used to recover the etching damage to form an extension S/D junction. A thick CVD oxide film is deposited on all regions.

Abstract: A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A method for fabricating a damascene interconnect includes the steps of depositing a metal layer of the surface of an insulating film; etching the metal layer and the insulating film to form an insulating groove; depositing a silicon layer on an upper surface on the metal layer and on each sidewall and a bottom of the insulating groove; annealing the silicon layer and the metal layer to form a silicide layer; implanting ions in the bottom of the insulating groove; and depositing an interconnect material in the insulating groove using selective chemical vapor deposition. In one embodiment, the metal layer is a titanium layer, the interconnect material is tungsten, and the implanted ions are arsenic ions.

Abstract: A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.

Abstract: Described is an improved polysilicon/tungsten silicide (WSi.sub.x) composite layer formed over an integrated circuit structure on a semiconductor wafer and characterized by improved step coverage and non tungsten-rich tungsten:silicon ratio of the WSi.sub.x layer, and a method of forming same. A doped layer of polysilicon is formed in a first deposition chamber over an integrated circuit structure previously formed on a semiconductor substrate and a capping layer of undoped polysilicon is then deposited in the first deposition chamber over the doped polysilicon layer. The substrate is then transferred from the first deposition chamber into a second deposition chamber without exposing the surface of the polysilicon layer to an oxidizing media.

Abstract: A method for forming a capacitor of a dynamic random access memory cell is disclosed. The method includes patterning a first polysilicon layer (124) over a semiconductor substrate, wherein at least a portion of the first polysilicon layer is communicated to the substrate. An anti-oxidation layer (125) is formed on the first polysilicon layer, wherein a portion of the first polysilicon layer is exposed. The first polysilicon layer is then thermally oxidized using the anti-oxidation layer as a mask, thereby forming poly-oxide (128) on sidewalls and the exposed surface of the first polysilicon layer. A portion of the first polysilicon layer is etched using the poly-oxide as an etch mask, thereby forming a trench in the first polysilicon. Thereafter, a pair of inner dielectric spacers (130A) is formed on inner sidewalls of the trench, and a pair of outer dielectric spacers (130B) on outer sidewalls of the poly-oxide.

Abstract: A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysilicon in the polysilicon gate 8 to form a metal silicide sidewall 20, and removing the metal silicide sidewall 20 by etching.

Abstract: A method of making ohmic contact between a thin film polysilicon layer of a first conductivity type and a subsequently provided conductive layer includes: a) providing a semiconductor substrate having an outer region; b) providing a first insulating layer outwardly of the outer region; c) etching a first contact opening of a first diameter through the first insulating layer to the substrate outer region; d) providing conductivity enhancing dopant impurity of the first conductivity type into the substrate outer region to render the outer region electrically conductive; e) providing a thin film polysilicon layer of the first conductivity type into the first contact opening and in ohmic electrical connection with the substrate outer region; f) providing a second insulating layer outwardly of the thin film polysilicon layer and the first insulating layer; g) etching a second contact opening of a second diameter into the second insulating layer, the second contact opening overlapping with the first contact opening

Abstract: In a method for manufacturing an LDD-structured MOS transistor and a bipolar transistor, a gate insulating layer is formed on a MOS transistor region and a bipolar transistor region. Then, a gate electrode is formed on the MOS transistor region. Then, an insulating layer is formed on the entire surface, and as etched back by a reactive ion etching process to form a sidewall spacer. The MOS transistor region and the bipolar transistor region are etched by a wet etching process using the gate electrode and its sidewall spacer as a mask.

Abstract: A method for fabricating polycide contacts to semiconductor substrates, and more specifically for self-aligned contacts on substrates having field effect transistors (FETs) is achieved. After forming conventional FETs from a patterned first polysilicon layer provided with contact areas, an insulating layer is deposited. Self-aligned contact openings are etched in the insulating layer to the contact areas on the substrate, and a patterned polycide (second polysilicon/silicide) layer is used to form the electrical contacts and interconnections. However, in prior art when a photoresist mask and plasma etching are used to pattern a polycide layer, misalignment of the mask can result in notching in the sidewalls of the patterned second polysilicon layer resulting in contact damage and high leakage currents. The method of the present invention utilizes a critical pre-etch rapid thermal anneal (RTA) that essentially eliminates the notching during etching of these marginally misaligned contacts.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract: A method for forming metal plugs using fewer masks and photolithographic processes than a conventional one and therefore able to simplify the overall manufacturing processes and reduce cost. The steps are:providing a substrate having a polysilicon gate, a source/drain region and a spacer formed on the sidewall of the polysilicon gate;forming a self-aligned metal silicide layer above the substrate and covering the polysilicon gate as well as the surface of the source/drain region;forming a first dielectric layer above the substrate, and then a first conducting layer above the first dielectric layer;using a photolithographic process to define a pattern on the first conducting layer and then etching the first dielectric layer to a certain depth;forming a second dielectric layer above the substrate;etching the first dielectric layer and the second dielectric layer until the metal silicide layer is exposed so as to form contact windows in designated regions; andforming metal plugs inside the contact windows.

Abstract: An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

Abstract: A Fabrication process for a semiconductor device, in which an element separation region and a gate insulation layer are formed on a surface of a silicon layer of a semiconductor substrate. Then, a gate electrode wiring is formed on the surface of the silicon layer and an insulation layer spacer is formed at the side surface of the gate electrode wiring. Diffusion layers to be a source and drain regions are formed in a predetermined region on the surface of the silicon layer. At least the surface of the diffusion region is converted into an uneven surface. Then, a refractory metal (e.g. titanium layer) is deposited on the entire surface, a refractory metal silicide layer is selectively formed on at least one of the surfaces of the diffusion layers by annealing, and a non-reacted refractory metal layer is selectively removed. Thus, in advance of deposition of titanium layer, unevenness is formed on the exposed surfaces of the diffusion layers and the upper surface of the polycrystalline silicon layer.

Abstract: A manufacturing method of the present invention comprises the first step of forming an epitaxial base layer in an opening of an element-isolating oxide film on a semiconductor substrate in a non-selection condition, the second step of growing a silicon oxide film on the epitaxial base layer and a base polysilicon layer, and the third step of etching the silicon oxide film to expose the polysilicon layer by the etch-back or the CMP. According to this method, the silicon oxide film is left only on the epitaxial base layer, and the planarization of the device can be attained. The present invention also reduces the resistance of the base electrode by providing silicide to the device.

Abstract: A method of making ohmic contact between a thin film polysilicon layer of a first conductivity type and a subsequently provided conductive layer includes: a) providing a semiconductor substrate having an outer region; b) providing a first insulating layer outwardly of the outer region; c) etching a first contact opening of a first diameter through the first insulating layer to the substrate outer region; d) providing conductivity enhancing dopant impurity of the first conductivity type into the substrate outer region to render the outer region electrically conductive; e) providing a thin film polysilicon layer of the first conductivity type into the first contact opening and in ohmic electrical connection with the substrate outer region; f) providing a second insulating layer outwardly of the thin film polysilicon layer and the first insulating layer; g) etching a second contact opening of a second diameter into the second insulating layer, the second contact opening overlapping with the first contact opening

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: A process for forming an increased surface area, buried contact region, for a MOSFET device, has been developed. The process features creating a mini-trench, in an insulator filled shallow trench, exposing a vertical surface of the semiconductor substrate, along the side of the mini-trench. An angled, phosphorous, ion implantation procedure, creates a buried contact region along a top surface, as well as along the vertical surface of the semiconductor substrate, exposed in the mini-trench.

Abstract: A polysilicon emitter of a bipolar device is formed utilizing a self-aligned Damascene technique. An oxide mask is patterned over epitaxial silicon implanted to form the intrinsic base. The oxide mask is then etched to form a window. Polysilicon is uniformly deposited over the oxide mask and into the window. The polysilicon is then polished to remove polysilicon outside of the window. Etching of the oxide mask follows, with good selectivity of oxide over silicon. This selectivity produces a polysilicon emitter atop an intrinsic base, the base flush with the silicon surface rather than recessed because of overetching associated with conventional processes.

Abstract: A method for making low-resistance contacts between polysilicon and metal silicide on semiconductor integrated circuits is described. The method is particularly useful for making low contact resistance (R.sub.c) between the tungsten polycide word lines and the access (pass) transistors (FETs) on DRAMs. A first polysilicon/first silicide (polycide) layer is patterned to form a first polycide conducting layer for the FET gate electrodes. A dielectric layer is deposited over the patterned first polycide layer, and contact openings are anisotropically plasma etched in the dielectric layer to the surface of the first silicide layer. A second doped polysilicon layer is deposited on the substrate and over and in the contact openings contacting the first silicide layer. Prior to depositing a second silicide layer, a high-temperature rapid thermal process (RTP) or annealing is carried out to alter the second polysilicon/first silicide interface to reduce the contact resistance (about 10 ohms).

Abstract: The present invention relates to a method of manufacturing a polysilicon film having a grain size of 0.5 .mu.m or more by forming a nucleus site of low density at low temperature of about 450.degree. C. with Si.sub.2 H.sub.6 gas, by growing an amorphous silicon film to some degree with the nucleus site, forming an amorphous silicon film of a device to a desired thickness by carrying out a main deposition process at the temperature of 500 through 600.degree. C. with SiH.sub.4 or SiH.sub.4 containing a small amount of impurity, and carrying out a heat treatment process for a long period at the temperature range of 600 through 700.degree. C. with N.sub.2 gas.