Abstract: The present invention provides an electrically conductive paste for a front electrode of a solar cell and a preparation method thereof. The electrically conductive paste is composed of a corrosion binder, a metallic powder and an organic carrier. The corrosion binder is one or more glass-free Pb—Te based crystalline compounds having a fixed melting temperature in a range of 440° C. to 760° C. During a sintering process of the electrically conductive paste for forming an electrode, the corrosion binder is converted into a liquid for easily corroding and penetrating an antireflective insulating layer on a front side of the solar cell, so that a good ohmic contact is formed. At the same time, the electrically conductive metallic powder is wetted, and the combination of the metallic powder is promoted. As a result, a high-conductivity front electrode of a crystalline silicon solar cell is formed.

Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10?9 ?·cm2.

Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.

Abstract: A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

Abstract: Provided is a physical vapor deposition apparatus with one or multiple deposition chambers for depositing films on substrates. The deposition chambers includes a heater and various cooling features to cool the chamber, the heater and the substrate. The sidewalls and top of the chamber are cooled by a cooling feature. The heater includes a cooling plate. A fitted heated cover is disposed between the heater and the substrate. A cooling pipe delivers a coolant throughout the cooling plate and extends in a high spatial density throughout the surface of the cooling plate. The cooling pipe occupies an area of about 14-20% of the area of the cooling plate and no location on the cooling plate surface is greater than about 15-20 mm from the cooling pipe. The cooling pipe cools the heater rapidly and enables deposition operations of long duration and using high power to be carried out.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects, such as corrosion, pits and damage, in the metal gate and improve reliability of the semiconductor device.

Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A Co film is formed by supplying cobalt alkylamidinate, and a combined gas containing H2 gas with at least one member selected from the group consisting of NH3, N2H4, NH(CH3)2, N2H3CH, and N2 as a reducing gas, or at least one gas selected from the group consisting of NH3, N2H4, NH(CH3)2, N2H3CH, and N2 as a reducing gas, on the surface of a base material, which consists of an SiO2 film or a barrier film serving as a primary layer. A Cu interconnection film is formed on the surface of the Co film.

Abstract: Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition.

Abstract: An object of the present invention is to provide an apparatus for successive deposition used for manufacturing a semiconductor element including an oxide semiconductor in which impurities are not included. By using the deposition apparatus capable of successive deposition of the present invention that keeps its inside in high vacuum state, and thus allows films to be deposited without being exposed to the air, the entry of impurities such as hydrogen into the oxide semiconductor layer and the layer being in contact with the oxide semiconductor layer can be prevented; as a result, a semiconductor element including a high-purity oxide semiconductor layer in which hydrogen concentration is sufficiently reduced can be manufactured. In such a semiconductor element, off-state current is low, and a semiconductor device with low power consumption can be realized.

Abstract: A manganese-containing film forming method for forming a manganese-containing film on an underlying layer containing silicon and oxygen includes: degassing the underlying layer formed on a processing target by thermally treating the processing target, the underlying layer containing silicon and oxygen; and forming a manganese metal film on the degassed underlying layer by chemical deposition using a gas containing a manganese compound. Forming a manganese metal film includes: setting a film formation temperature to be higher than a degassing temperature; introducing a reducing reaction gas; and forming a manganese-containing film including an interfacial layer formed in an interface with the underlying layer and a manganese metal film formed on the interfacial layer, the interfacial layer being made up of a film of at least one of a manganese silicate and a manganese oxide.

Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.

Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.

Abstract: A mobile terminal is provided. The mobile terminal comprises at least one element, a connector selectively connected to another device to provide a data exchange path between the at least one element and the other device, and a thermal conduction frame having one side coming into contact with the at least one element and the other side coming into contact with the connector to transfer heat generated from the at least one element to the connector. The connector is connected to the element included in the mobile terminal and the other device through the thermal conduction frame to effectively transfer heat generated from the element to the other device through the connector.

Abstract: A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween.

Abstract: A semiconductor device comprises: a semiconductor structure formed with openings for exposing pads on an one surface thereof, a first conductive layer formed in the openings to make the one surface of the semiconductor structure more uniform, and conductive patterns formed on portions of the one surface of the semiconductor structure including the first conductive layers.

Abstract: A liquid treatment apparatus of continuously performing a plating process on multiple substrates includes a temperature controlling container for accommodating a plating liquid; a temperature controller for controlling a temperature of the plating liquid in the temperature controlling container; a holding unit for holding the substrates one by one at a preset position; a nozzle having a supply hole through which the temperature-controlled plating liquid in the temperature controlling container is discharged to a processing surface of the substrate; a pushing unit for pushing the temperature-controlled plating liquid in the temperature controlling container toward the supply hole of the nozzle; and a supply control unit for controlling a timing when the plating liquid is pushed by the pushing unit. The temperature controller controls the temperature of the plating liquid in the temperature controlling container based on the timing when the plating liquid is pushed by the pushing unit.

Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Abstract: Vias (holes) are formed in a wafer or a dielectric layer. A low viscosity conductive ink, containing microscopic metal particles, is deposited over the top surface of the wafer to cover the vias. An external force is applied to urge the ink into the vias, including an electrical force, a magnetic force, a centrifugal force, a vacuum, or a suction force for outgassing the air in the vias. Any remaining ink on the surface is removed by a squeegee, spinning, an air knife, or removal of an underlying photoresist layer. The ink in the vias is heated to evaporate the liquid and sinter the remaining metal particles to form a conductive path in the vias. The resulting wafer may be bonded to one or more other wafers and singulated to form a 3-D module.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the step of forming a silicon dioxide film. The step of forming an electrode includes the steps of forming a metal film containing Al and Ti on the silicon carbide substrate, and heating the metal film. The step of heating the metal film has the steps of increasing temperature of the metal film from a temperature of less than 300° C. to a temperature of not less than 300° C. and not more than 450° C. with a first temperature gradient, holding the metal film within a temperature range of not less than 300° C. and not more than 450° C. with a second temperature gradient, and increasing the temperature of the metal film to a temperature of not less than 500° C. with a third temperature gradient. The second temperature gradient is smaller than the first temperature gradient and the third temperature gradient.

Abstract: An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.

Abstract: A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.

Abstract: The invention is directed to a polymer thick film conductive composition comprising (a) a conductive silver-coated copper powder; and (b) an organic medium comprising two different resins and organic solvent, wherein the ratio of the weight of the conductive silver-coated copper powder to the total weight of the two different resins is between 5:1 and 45:1. The invention is further directed to a method of electrode grid and/or bus bar formation on thin-film photovoltaic cells using the composition and to cells formed from the method and the composition.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A photovoltaic cell such as a solar cell is disclosed. The cell comprises (a) a semiconductor substrate having a front surface, (b) one or more anti-reflection coating layers on the front surface of the semiconductor substrate, (c) a plurality of silver-containing fingers in contact with the one or more anti-reflection coating layers and in electrical contact with the semiconductor substrate; and (d) one or more base metal containing buss bars each in contact with the one or more anti-reflection coating layers and the silver-containing fingers. The base metal may be selected from one or more of copper, nickel, lead, tin, iron, indium, zinc, bismuth and cobalt. Methods for making protovoltaic cells with base metal containing buss bars are also disclosed.

Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions can be achieved through a reaction-preventative or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).

Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).

Abstract: A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.

Abstract: A method of manufacturing a semiconductor device including forming a first sacrificial layer on a substrate, the first sacrificial layer including a conductive material, forming a second sacrificial layer on the first sacrificial layer, the second sacrificial layer including an insulating material, patterning the second sacrificial layer and the first sacrificial layer to form an opening successively penetrating the second and first sacrificial layers, conformally forming a seed layer on the second and first sacrificial layers including the opening, and forming a conductive pattern filling the opening having the seed layer by a plating process.

Abstract: A method can be used for locally rendering a carbonic isolating layer conductive. In one embodiment, a laser beam is directed onto the carbonic isolating layer so as to convert amorphous carbon of the carbonic isolating layer into graphite-like carbon. In another embodiment, the carbonic layer is heated so as to form a conducting portion of the layer so that a lateral path through the conducting portion connects two circuit elements of the integrated circuit.

Abstract: A method for manufacturing a layer arrangement in accordance with various embodiments may include: providing a first layer having a side; forming one or more nanoholes in the first layer that are open towards the side of the first layer; depositing a second layer over the side of the first layer.

Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.

Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

Abstract: The device for knife coating a layer of ink based on copper and indium on a substrate includes a supply tank of an ink, said tank collaborating with a coating knife. In addition, the device includes means that allow the ink, the substrate and the coating knife to be kept at different and increasing respective temperatures.

Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.

Abstract: Disclosed is a method of forming wiring. The method includes the steps of: depositing a metal thin film (12) of copper (Cu) on a glass substrate (11) serving as a base; forming an insulating film or a metal insulating film (131) containing no Cu on the metal thin film (12); patterning a photoresist (14) by photolithography on the insulating film (131); etching a liner film (13) by isotropic dry etching using the photoresist (14) as an etching mask; and after the etching of the liner film (13), removing the photoresist (14), and then removing part of the metal thin film (12) by isotropic wet etching using the liner film (13) as an etching mask, thereby forming metal wiring (12a).

Abstract: A method of fabricating a semiconductor device includes forming a bottom electrode material layer containing aluminum and copper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.

Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

Abstract: A method for forming a metal compound film includes: providing a substrate structure; forming a first metal layer on the substrate structure; performing a first microwave annealing process to conduct a reaction between the first metal layer and the substrate structure so as to form a first polycrystalline film of a metal compound; and performing a second microwave annealing process to transform the first polycrystalline film into a second polycrystalline film of the metal compound with an enlarged grain size, wherein a microwave power output used in the second microwave annealing process is higher than that used in the first microwave annealing process.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract: In various embodiments, a method of processing a contact pad may include providing a contact pad, a topmost layer of the contact pad containing aluminum or an aluminum alloy, at least part of the topmost layer of the contact pad being exposed; subjecting the contact pad to a thermally activated atmosphere containing water or reactive components of water.

Abstract: A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.

Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.