Abstract: Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.

Abstract: A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.

Abstract: The invention prevents a conductive fuse blown out by laser trimming from reconnecting by a plating electrode in a plating process and prevents a plating solution etc from entering a fuse blowout portion. On a semiconductor substrate of a multilayered wiring structure including a fuse blowout groove formed by blowing out a conductive fuse by laser trimming in a trimming element forming region, a second protection layer is formed so as to cover the trimming element forming region and then a plating electrode is formed on an draw-out pad electrode made of a topmost metal wiring. A third protection layer is then formed so as to cover the semiconductor substrate including the second protection layer and have an opening on the plating electrode.

Abstract: A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate.

Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.

Abstract: Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.

Abstract: A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning conductor ions from the dielectric layer by dissolving the conductor in a low pH solution, dissolving the dielectric layer under the conductor ions, mechanically enhanced cleaning, or chemisorbing a hydrophobic layer on the dielectric layer.

Abstract: Methods for fabricating integrated circuits having low resistance device contacts are provided. One method includes depositing an ILD layer of insulating material overlying a device region that includes a metal silicide region. The ILD layer is etched to form a sidewall that defines a contact opening formed through the ILD layer exposing the metal silicide region. A liner is formed overlying the sidewall and the metal silicide region and defines an inner cavity in the contact opening. A copper layer is formed overlying the liner and at least partially filling the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract: In order to better and more efficiently assemble back contact solar cells into modules, the cell to cell soldering and other soldered connections are replaced by electro and/or electroless plating. Back contact solar cells, diodes and external leads can be first laminated to the module front glass for support and stability. Conductive materials are deposited selectively to create a plating seed pattern for the entire module circuit. Subsequent plating steps create an integrated cell and module metallization. This avoids stringing and tabbing and the associated soldering steps. This process is easier for mass manufacturing and is advantageous for handling fragile silicon solar cells. Additionally, since highly corrosion resistant metals can be plated, the moisture barrier requirements of the back side materials can be greatly relaxed. This can simplify and reduce the cost of the back side of the module.

Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.

Abstract: The present invention relates to a kit intended for the deposition of nickel or cobalt in the cavities of a semiconductor substrate intended to form through-silicon vias (TSV) for making interconnections in integrated circuits in three dimensions. The invention also relates to a method of metallization of the insulating surface of such a substrate which comprises contacting the surface with a liquid aqueous solution containing: at least one metal salt of nickel or cobalt; at least one reducing agent; at least one polymer bearing amine functions, and at least one agent stabilizing the metal ions. The step coverage of the layer of nickel or cobalt obtained can be greater than 80%, which facilitates subsequent filling of the vias with copper by electrodeposition.

Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.

Abstract: An apparatus and system for stirring liquid inside a flow cell. In one implementation, the apparatus includes a rotatable disc configured to receive liquid at a top side of the disc and distribute the liquid substantially evenly around a periphery of the flow cell. The disc has a triangular cross sectional area. The apparatus may further include a set of fins attached to a bottom side of the disc, wherein the set of fins is configured to draw the liquid from the periphery of the flow cell into the center of the flow cell.

Abstract: A substrate 1 having metal layers 2A and 2B arranged to form a gap is dipped in an electroless plating solution mixed an electrolyte solution including metal ions with a reducing agent and a surfactant. Metal ions are reduced by the reducing agent to be precipitated on the metal layers 2A and 2B, and the surfactant is adhered to a surface of the metal on the metal layers, thereby forming a pair of electrodes 4A, 4B to be controlled to have a nanometer sized gap. These steps enable to provide a method for fabricating nanogap electrodes, a nanogap electrodes array, and a nanodevice with the same.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: To provide a method of manufacturing a through hole electrode substrate which comprises forming a plurality of through holes passing through the front and back of a wafer-shaped substrate, forming an insulation film on a surface of the substrate and the though hole, forming a seed layer from a metal on at least one side of the substrate and/or the through hole, forming a metal layer having a cap shape on a bottom part of the through hole on a surface on which the seed layer is formed by an electrolytic plating method supplying direct current to the seed layer for a first time period, and filling a metal material into the plurality of through holes by an electrolytic plating method supplying a pulse current to the seed layer and the metal layer.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material, resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.

Abstract: Proposed are a composite material having a high adhesiveness, wherein non-penetrating pores that are formed in a silicone surface layer are filled up with a metal or the like without leaving any voids by using the plating technique and the silicone surface layer is coated with the metal or the like, and a method of producing the composite material. A composite material, which has a high adhesiveness between a second metal or an alloy of the second metal (106a, 106b) and a silicone surface, can be obtained by filling up non-penetrating pores that are formed in the surface of a silicone substrate (100) substantially with a second metal or an alloy of the second metal (106a) with the use of the autocatalytic electroless plating technique wherein a first metal located at the bottom of the non-penetrating pores as described above serves as the starting point, and coating the surface of the silicone substrate (100) with the second metal (106b).

Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.

Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract: A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.

Abstract: A method of fabrication of electrical contact structures on a semiconductor material includes depositing an oxide of a desired contact material by a chemical electroless process on a face of the semiconductor material and reducing the oxide via a chemical electroless process to produce a contact of the desired contact material. A method of fabrication of a semiconductor device incorporating such electrical contact structures and a semiconductor device incorporating such electrical contact structures are also described.

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

Abstract: The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.

Abstract: A method of forming a metal layer on an electrically insulating substrate comprises depositing a photocatalyst layer onto the substrate and depositing a mask layer comprising voids on the substrate, such as a layer of latex microparticles with voids between them, to give an open pore structure to the mask. An electroless plating solution is then provided on the photocatalyst layer, and the photocatalyst layer and electroless plating solution are illuminated with actinic radiation whereby deposition of metal from the electroless plating solution to form a metal layer on the photocatalyst layer is initiated whereby the metal deposits in the voids of the mask layer. The mask layer is subsequently removed to leave a porous metal layer on the substrate. The method allows for deposition of porous metal films with controlled thickness and excellent adhesion onto electrically insulating substrates. The method is suitable for providing metal layers with controlled, regular porosity.

Abstract: The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

Abstract: Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the conductive layer and v) etch away an amount of the solder deposit layer containing tin or tin alloy sufficient to remove the solder deposit layer from the solder mask layer area leaving a solder material layer on the at least one contact area.

Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.

Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.

Abstract: Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate, masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.

Abstract: A first metal mask has a portion exposed at an opening of a second metal mask. The second metal mask is formed to be thicker than the first metal mask. The thickness of the first and second metal masks is such that the etching at an opening of the first mask reaches a source electrode when the etching at the opening of the second mask substantially reaches a semiconductor device forming layer.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

Abstract: A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided.

Abstract: There is provided an electroless plating apparatus which, despite using a high-productivity batch processing method, can reduce the amount of a liquid chemical brought out of a processing tank, thereby reducing the cleaning time in a cleaning step, and can perform flushing easily and quickly. The electroless plating apparatus includes a pre-plating treatment module including a pre-plating treatment tank, a plating module, and an inter-module substrate transport device. The pre-plating treatment tank is provided with a pre-plating treatment solution circulation line having a temperature control function for a pre-plating treatment solution. The plating tank is provided with a plating solution circulation line having a filter and a temperature control function for a plating solution. The plating solution circulation line is connected to a flushing line for flushing the interior of the plating solution circulation line and the interior of the plating tank.

Abstract: A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed.

Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.

Abstract: A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer.

Abstract: A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and secon

Abstract: One embodiment of the present invention is a method of electroless deposition of cap layers for fabricating an integrated circuit. The method includes controlling the composition of an electroless deposition bath so as to substantially maintain the electroless deposition properties of the bath. Other embodiments of the present invention include electroless deposition solutions. Still another embodiment of the present invention is a composition used to recondition an electroless deposition bath.

Abstract: Disclosed is a method for making a nickel film for use as an electrode of an n-p diode or solar cell. A light source is used to irradiate an n-type surface of the n-p diode or solar cell, thus producing electron-hole pairs in the n-p diode or solar cell. For the electric field effect at an n-p interface, electrons drift to and therefore accumulate on the n-type surface. With a plating agent, the diode voltage is added to the chemical potential for electroless plating of nickel on the n-type surface. The nickel film can be used as a buffer layer between a contact electrode and the diode or solar cell. The nickel film reduces the contact resistance to prevent a reduced efficiency of the diode or solar cell that would otherwise be caused by diffusion of the atoms of the electrode in following electroplating.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.