Evaporative Coating Of Conductive Layer Patents (Class 438/679)
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Publication number: 20040137710Abstract: For forming a fine structure of a desired material, nanoparticles of the same material are prepared in a suspension. A layer of the suspension is applied by a drop-on-demand printing system to a substrate. At least part of the layer is exposed to laser light for melting the nanoparticles at least partially. Upon solidification, the molten particles are sintered together to form the desired structure. Due to the low melting point of nanoparticles as compared to the melting point of bulk material, this procedure avoids damage to the substrate and provides a better control over the structure generation process. It can be used for generating metallic and non-metallic structures on various substrates. The laser light may have non-Gaussian intensity distribution or can combine multiple beams of Gaussian and non-Gaussian distribution for improving the quality of the generated structure, or it may be pulsed for improved control of the heat flow into the substrate.Type: ApplicationFiled: July 16, 2003Publication date: July 15, 2004Inventors: Constantine P. Grigoropoulos, Nicole Renee Bieri, Dimos Poulikakos, Jaewon Chung
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Publication number: 20040102037Abstract: A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask layer to form a projection electrode of the second metal; and removing the stopper mask layer after the metal supplying step.Type: ApplicationFiled: November 12, 2003Publication date: May 27, 2004Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Mitsuo Umemoto
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Patent number: 6740164Abstract: Plating apparatus and plating method that can plate more uniformly on a processing surface of a workpiece are provided. The plating apparatus is comprised of a plating solution bathe which is provided with a first electrode held in a state soaked in a plating solution; a workpiece holding mechanism which holds a workpiece to contact its processing surface to the plating solution; and a contact member, disposed in the workpiece holding mechanism, that electrically contacts with the circumferential edge of the workpiece so to form a conductive layer on the workpiece surface as a second electrode. The contact member is divided along the circumferential direction of the workpiece with which they are electrically contacted. Thus, even if the contact resistance between each section of the contact member with the workpiece is variable, it is possible to adjust the plating electric current for each section of the contact member.Type: GrantFiled: January 30, 2002Date of Patent: May 25, 2004Assignee: Tokyo Electron LimitedInventors: Wataru Okase, Takenobu Matsuo
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Publication number: 20040084709Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.Type: ApplicationFiled: July 29, 2003Publication date: May 6, 2004Applicant: Samsung Electronics Co, Ltd.Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
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Publication number: 20040058529Abstract: This invention relates to a method of depositing a layer on an exposed surface of an insulating layer of material. The method includes treating the exposed surface with hydrogen or a gaseous source of hydrogen in the presence of a plasma, prior to or during deposition of a metallic layer.Type: ApplicationFiled: September 4, 2003Publication date: March 25, 2004Inventors: Knut Beekman, Paul Rich, Claire Louise Wiggins
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Publication number: 20040058526Abstract: Methods and devices are disclosed which provided lined conductive structures in semiconductor devices. Openings are formed in a dielectric layer to expose an underlying conductor. A first liner is deposited in the opening and on the underlying conductor by a physical vapor deposition process. A conformally deposited second liner is formed over the first liner, and a conductive structure is formed in the opening. Also, a sacrificial liner can be employed to getter undesirable compounds from the dielectric layer before forming a liner.Type: ApplicationFiled: September 24, 2002Publication date: March 25, 2004Applicant: Infineon Technologies North America Corp.Inventors: Andrew Cowley, Michael Stetter, Erdem Kaltalioglu, Mark Hoinkis
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Patent number: 6699788Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.Type: GrantFiled: November 13, 2001Date of Patent: March 2, 2004Assignee: Chartered Semiconductors Manufacturing LimitedInventors: Guy Eristoff, Sarion C. S. Lee, Liew San Leong, Goh Khoon Meng
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Patent number: 6699789Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.Type: GrantFiled: March 27, 2002Date of Patent: March 2, 2004Assignee: Mosel Vitelic, Inc.Inventors: Zhih-Sheng Yang, Chung-Yan Cheng, Ying-Yan Huang, Jason C. S. Chu
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Publication number: 20040014314Abstract: A method and apparatus for forming a thermally-evaporated bina (or greater) thin film are disclosed in which the surface area of an evaporatio container is effectively increased by using an inert medium added to source materials that are to form the binary (or greater) film. Using this method a apparatus, films having better uniformity and stoichiometry are achievable.Type: ApplicationFiled: April 24, 2002Publication date: January 22, 2004Inventor: Joseph F. Brooks
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Patent number: 6673716Abstract: A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with controlling the deposition temperatures by integrating cooling steps into the Ti/TiN deposition processes to modulate the via and contact resistance. The Ti and TiN layers are deposited within a single deposition chamber, without the use of a collimator or a shutter.Type: GrantFiled: January 30, 2002Date of Patent: January 6, 2004Assignee: Novellus Systems, Inc.Inventors: Gerard C. D'Couto, George Tkach, Michael Woitge, Michal Danek
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Patent number: 6670283Abstract: Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.Type: GrantFiled: November 20, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Faye D. Baker, Casey J. Grant, Mousa H. Ishaq, Joel M. Sharrow, James D. Weil
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Patent number: 6667231Abstract: An integrated circuit structure and method of making the same is disclosed, in which the adhesion of copper conductors (12, 22) to a low-dielectric constant insulating layer (10, 16) is improved. During the fabrication of the structure, exposed surfaces of the low-k insulating layers (10, 16), including the surfaces of these layers within contact, via, or trench openings, are exposed to nitrogen gas, preferably in a sputtering chamber. An optional plasma treatment of the insulating layers (10, 16) in the presence of nitrogen gas may also be performed. As a result, the surface portions of the insulating layers (10, 16) is made to be nitrogen-rich. A liner layer (8, 21) is then formed by reactive sputtering of tantalum nitride over the nitrogen-rich surfaces of the insulating layers (10, 16), followed by the sputtering of tantalum. Copper electrodes (12, 22) are then deposited into the openings in the corresponding insulating layers (10, 16) with improved adhesion resulting.Type: GrantFiled: July 12, 2002Date of Patent: December 23, 2003Assignee: Texas Instruments IncorporatedInventor: Lixin Wu
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Patent number: 6667215Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.Type: GrantFiled: May 2, 2002Date of Patent: December 23, 2003Assignee: 3M Innovative PropertiesInventors: Steven D. Theiss, Paul F. Baude, Michael A. Haase, Silva K. Theiss
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Patent number: 6649521Abstract: A method for determining relevant deposition parameters in i-PVD processes, includes, first calculating the reaction rates for desired reagents of the gas plasma and of a metal and/or metal compound to be deposited, then simulating the edge coverage of a predetermined structure with the deposited metal based upon the calculated reaction rates with systematic variation of the relevant deposition parameters, and compiling variant tables therefrom. By comparing an experimental verification of the simulated edge coverage by imaging the edge coverage of the metal layer deposited over the determined structure, e.g., using a TEM cross-section, with the simulated deposition parameters for the edge coverages that have been recorded in the variant table, it is possible to read the deposition parameters that are of relevance to the process from the variant table.Type: GrantFiled: July 29, 2002Date of Patent: November 18, 2003Assignee: Infineon Technologies AGInventors: Alfred Kersch, Alexander Ruf
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Patent number: 6627544Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.Type: GrantFiled: May 22, 2002Date of Patent: September 30, 2003Assignees: Sharp Kabushiki Kaisha, Meltex Inc., Sumitomo Osaka Cemento Co., Ltd.Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
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Patent number: 6624070Abstract: Disclosed are catalyst compositions suitable for depositing electroless metal seed layers and for enhancing discontinuous seed layers. Also disclosed are methods of depositing electroless seed layers and enhancing discontinuous seed layers.Type: GrantFiled: October 24, 2001Date of Patent: September 23, 2003Assignee: Shipley Company, L.L.C.Inventors: David Merricks, Martin T. Goosey, Narinder Bains
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Patent number: 6610596Abstract: A method is provided for forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing process. A semiconductor device manufactured by this method is also provided. In the method of forming a metal interconnection, a recess region is formed in a portion of an insulation layer formed over a substrate, i.e., where a metal interconnection layer will be formed. A diffusion prevention layer is formed over the substrate, the insulation layer, and the recess region. Then, a metal seed layer is formed over the diffusion prevention layer only in the recess region using a chemical mechanical polishing process or an etch back process. A conductive plating layer is then formed on the metal seed layer only in the recess region. Thereafter, surface polarization is performed to form a metal interconnection layer in the recess region.Type: GrantFiled: September 14, 2000Date of Patent: August 26, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-won Lee, Bo-un Yoon, Kun-tack Lee, Sang-rok Hah
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Publication number: 20030153177Abstract: In one embodiment of the present inventions, an exhaust outlet in a vacuum processing chamber includes a nonsealing flow restrictor which can facilitate rapid opening and closing of the flow restrictor in some applications. Because the flow restrictor is a nonsealing flow restrictor, the conductance of the flow restrictor in the closed position may not be zero. However, the flow restrictor can restrict the flow of an exhaust gas from the chamber to permit the retention of sufficient processing gas in the chamber to deposit a film on the substrate or otherwise react with the substrate. After a film has been deposited, typically in a thin atomic layer, the exhaust flow restrictor may be opened such that the flow restrictor conductance is significantly increased to a second, higher flow rate to facilitate exhausting residue gas from the chamber. The nonsealing flow restrictor may be closed again to deposit a second layer, typically of a different material onto the substrate.Type: ApplicationFiled: February 11, 2002Publication date: August 14, 2003Applicant: Applied Materials, Inc.Inventors: Avi Tepman, Lawrence Chung-Iai Lei
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Patent number: 6589887Abstract: The present invention pertains to methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods may be used to form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Under specific conditions, the metal vapor reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.Type: GrantFiled: October 11, 2001Date of Patent: July 8, 2003Assignee: Novellus Systems, Inc.Inventors: Jeremie Dalton, Ronald A. Powell, Sridhar K. Kailasam, Sasangan Ramanathan
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Publication number: 20030119312Abstract: A method of forming a film on a substrate using Group IIIA metal complexes. The complexes and methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.Type: ApplicationFiled: December 19, 2002Publication date: June 26, 2003Applicant: MICRON TECHNOLOGY, INC.Inventor: Brian A. Vaartstra
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Patent number: 6573185Abstract: The present method of manufacturing a semiconductor device has a step of forming a metal film on the surface of a group of semiconductor wafers by bringing the internal temperature of a chamber of a film formation device to a film formation temperature at which the metal film is deposited, followed by a step of lowering the temperature of the chamber to a standby temperature at a constant rate and holding the temperature of the chamber at the standby temperature until the film formation for the next group of the semiconductor wafers.Type: GrantFiled: March 13, 2001Date of Patent: June 3, 2003Assignee: NEC Electronics CorporationInventor: Atsushi Kariya
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Publication number: 20030096499Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.Type: ApplicationFiled: November 13, 2001Publication date: May 22, 2003Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITEDInventors: Guy Eristoff, Sarion C.S. Lee, Liew San Leong, Goh Khoon Meng
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Patent number: 6562715Abstract: A barrier layer structure and a method of forming the structure. The barrier layer structure comprises a bilayer, with a first layer formed by chemical vapor deposition and a second layer formed by physical vapor deposition. The first barrier layer comprises a metal or a metal nitride and the second barrier layer comprises a metal or a metal nitride. The barrier bilayer is applicable to copper metallization.Type: GrantFiled: August 9, 2000Date of Patent: May 13, 2003Assignee: Applied Materials, Inc.Inventors: Ling Chen, Christophe Marcadal
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Patent number: 6551931Abstract: A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed.Type: GrantFiled: November 7, 2000Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Sung Kwon Kang, Maurice McGlashan-Powell, Eugene J. O'Sullivan, George F. Walker
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Patent number: 6541375Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by DC reactive sputtering.Type: GrantFiled: August 3, 1998Date of Patent: April 1, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichiro Hayashi, Koji Arita
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Publication number: 20030017697Abstract: Methods of forming metal layers include techniques to form metal layers using atomic layer deposition techniques that may be repeated in sequence to build up multiple atomic metal layers into a metal thin film. The methods include forming a metal layer by chemisorbing a metallic precursor comprising a metal element and at least one non-metal element that is ligand-bonded to the metal element, on a substrate. The metal element may include tantalum. The chemisorbed metallic precursor is then converted into the metal layer by removing the at least one non-metal element from the metallic precursor through ligand exchange. This removal of the non-metal element may be achieved by exposing the chemisorbed metallic precursor to an activated gas that is established by a remote plasma, which reduces substrate damage. The activated gas may be selected from the group consisting of H2, NH3, SiH4 and Si2H6 and combinations thereof. These steps may be performed at a temperature less than about 650° C.Type: ApplicationFiled: July 17, 2002Publication date: January 23, 2003Inventors: Kyung-In Choi, Sang-Bum Kang, Byung-Hee Kim, Gil-Heyun Choi
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Publication number: 20030017700Abstract: This invention produces a film which is resistant to hillocking without compromising the electrical conductivity of the interconnects, the circuit architecture or any other function affecting the operation of the integrated circuit. The invention works on the principle that hillocking is caused by the squeezing or extrusion of certain grains (crystals) in the film due to a compressive residual stress state that arises from annealing (heating) treatments applied to the film following the deposition of the film. These grains are in a “weak” crystallographic orientation relative to the great majority of the grains. The coordinated orientation of this great majority of grains is known as the texture and aluminum films are deposited with a strong (111) texture, where (111) refers to specific crystallographic planes and <111>. Refers to the direction normal to the (111) plane.Type: ApplicationFiled: July 23, 2001Publication date: January 23, 2003Inventors: Gary S. Was, David Srolovitz, Zhenqiang Ma, Liang Dong
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Publication number: 20020197863Abstract: A system and method to form a stacked barrier layer for copper contacts formed on a substrate. The substrate is serially exposed to first and second reactive gases to form an adhesion layer. Then, the adhesion layer is serially exposed to third and fourth reactive gases to form a barrier layer adjacent to the adhesion layer. This is followed by deposition of a copper layer adjacent to the barrier layer.Type: ApplicationFiled: June 20, 2001Publication date: December 26, 2002Inventors: Alfred W. Mak, Mei Chang, Jeong Soo Byun, Hua Chung, Ashok Sinha, Moris Kori
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Patent number: 6486054Abstract: The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a first exposure, a negative photoresist (preferably DFR) is patterned to form a conventional cylindrical mold. However, exposure and development time are adjusted in such a way that a layer of unexposed and undeveloped resist of reduced thickness remains covering the floor of the mold. This residual resist layer is given a second exposure and, after development, forms an annular insert in the bottom of the first mold. After the mold has been filled with solder (either through electroplating or by using solder paste) it is removed, the result being a solder bump made up of two contiguous coaxial cylinders the upper one having the larger diameter. After remelt, bumps having this shape form oblate spheroids rather than spheres.Type: GrantFiled: January 28, 2002Date of Patent: November 26, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Hsiu-Mei Yu, Li-Hsin Tseng, Kuang-Peng Lin, Ta-Yang Lin
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Patent number: 6472309Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.Type: GrantFiled: February 17, 2000Date of Patent: October 29, 2002Assignee: Micron Technology, Inc.Inventor: Weimin Li
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Patent number: 6472310Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.Type: GrantFiled: April 8, 2002Date of Patent: October 29, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Sergey Lopatin
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Patent number: 6458700Abstract: The invention comprises integrated circuitry fabrication methods of making a conductive electrical connection, methods of forming a capacitor and an electrical connection thereto, methods of forming DRAM circuitry, integrated circuitry, and DRAM integrated circuitry. In one implementation, an integrated circuitry fabrication method of making a conductive electrical connection includes forming a conductive layer including a conductive metal oxide over a substrate. The conductive layer has an outer surface. At least a portion of the conductive layer outer surface is exposed to reducing conditions effective to reduce at least an outermost portion of the metal oxide of the conductive layer, most preferably by removing oxygen. Conductive material is formed over the reduced outermost portion and in electrical connection therewith. In one implementation, integrated circuitry includes a conductive metal oxide comprising layer received over a substrate.Type: GrantFiled: October 25, 2000Date of Patent: October 1, 2002Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 6432821Abstract: An electroplating process for filling damascene structures on substrates, such as wafers having partially fabricated integrated circuits thereon, includes immersing a substrate, under bias, into a copper plating solution to eliminate thin seed layer dissolution and reduce copper oxide, an initiation step to repair discontinuities in a copper seed layer, superfill plating to fill the smallest features, reverse plating to remove the adsorbed plating additives and their by-products from the substrate, a second superfill plating to fill intermediate size features, a second reverse plating to remove adsorbed plating additives and their by-products from the substrate, and a bulk fill plating with high current density to fill large features. The superfill and reverse plating operations may be repeated more than twice prior to bulk filling in order to provide the desired surface morphology.Type: GrantFiled: December 18, 2000Date of Patent: August 13, 2002Assignee: Intel CorporationInventors: Valery M. Dubin, Dave W. Jentz, Christopher Collazo-Davila
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Patent number: 6423636Abstract: The present invention generally provides an apparatus and a method for electrochemical deposition of a metal layer on a substrate that achieves high throughput and minimal edge exclusion. The invention provides a method for forming a metal layer on a substrate comprising: depositing a full coverage seed layer over the substrate; electrochemically depositing a metal layer over the seed layer; and removing any exposed seed layer from an annular edge portion of the substrate. The invention also provides an apparatus for forming a metal layer on a substrate comprising: an electrochemical deposition cell having a cathode contact member adapted to contact a peripheral portion of a substrate at less than about 3 mm from an edge of the substrate, a processing cell adapted to remove any exposed seed layer on a peripheral portion of the substrate; and a transfer chamber having a robot adapted to transfer a substrate between the electrochemical deposition cell and the processing cell for removing exposed seed layer.Type: GrantFiled: November 19, 1999Date of Patent: July 23, 2002Assignee: Applied Materials, Inc.Inventors: Yezdi Dordi, Michael Sugarman
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Patent number: 6420263Abstract: A method of forming a semiconductor device having aluminum lines therein, wherein the occurrence of lateral extrusions and voids are reduced. The method comprises the formation of a metal stack on a surface of the substrate, wherein the aluminum layer of the metal stack is deposited under controlled conditions; etching the metal lines in the metal stack; and exposing the substrate to a subsequent anneal.Type: GrantFiled: February 28, 2000Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Roger W. Cheek, George A. Dunbar, III, Robert M. Geffken, William J. Murphy, Prabhat Tiwari, David H. Yao
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Patent number: 6403498Abstract: A substrate processing method of processing a surface of a substrate in manufacture of a semiconductor device, characterized by comprising a surface processing step for making a substance having an adsorption heat higher than that of an organic matter whose adsorption on the surface of the substrate, which has been cleaned, is undesirable, adsorbed on the surface of the substrate, and a film formation step for forming a thin film on the surface of the substrate which was processed in the above step.Type: GrantFiled: November 30, 1998Date of Patent: June 11, 2002Assignee: Tokyo Electron LimitedInventors: Takenobu Matsuo, Tsuyoshi Wakabayashi, Teruyuki Hayashi, Misako Saito
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Patent number: 6368954Abstract: A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.Type: GrantFiled: July 28, 2000Date of Patent: April 9, 2002Assignees: Advanced Micro Devices, Inc., Genus Inc.Inventors: Sergey D. Lopatin, Carl Galewski, Takeshi T. N. Nogami
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Patent number: 6358821Abstract: A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.Type: GrantFiled: July 19, 2000Date of Patent: March 19, 2002Assignee: Chartered Semiconductor Manufacturing Inc.Inventors: Subhash Gupta, Simon Chooi, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono
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Patent number: 6333264Abstract: In accordance with one aspect of the invention, a semiconductor processing method of treating a semiconductor wafer provides a wafer within a volume of liquid. The wafer has some electrically conductive material formed thereover. The volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere and at a temperature of at least 200° C., and below and within 10% of the melting point of the electrically conductive material. In accordance with another aspect, the volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere. After establishing the pressure of greater than 1 atmosphere, the pressure of the volume of liquid is lowered to a point effective to vaporize said liquid and the vapor is withdrawn from the chamber.Type: GrantFiled: September 2, 1998Date of Patent: December 25, 2001Assignee: Micron Technology, Inc.Inventors: David A. Cathey, Mark Durcan
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Patent number: 6316360Abstract: A contact interface having a substantially annular silicide ring along sides of a depression formed in an active surface of the semiconductor substrate, wherein the depression is formed by an etching process to form a contact opening through a dielectric layer. The contact interface is formed by depositing a layer of conductive material, such as titanium, with a high bias power IMP deposition. The conductive material is turned to a silicide by an annealing process, thereby forming the contact interface.Type: GrantFiled: September 9, 1998Date of Patent: November 13, 2001Assignee: Micron Technology, Inc.Inventors: Randle D. Burton, John H. Givens
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Patent number: 6300245Abstract: An apparatus and method for performing material deposition on semiconductor devices. The apparatus provides an enclosure for defining a chamber. The chamber includes a metallic portion such as a conductor coil powered by a voltage generator. A gas, having a suspension of particles for treating the semiconductor devices, is introduced into the chamber and the powered conductor coil converts the gas to inductively coupled plasma and vaporizes the particles. The particles can then be deposited on the semiconductor devices.Type: GrantFiled: December 13, 1999Date of Patent: October 9, 2001Assignee: Ball Semiconductor, Inc.Inventors: Ivan Herman Murzin, Ram K. Ramamurthi
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Patent number: 6291347Abstract: A system for constructing semiconductor devices is disclosed. The system comprises a wafer (102) having semiconductor devices (104), a bevel (108), an edge (110), a frontside (111), and a backside (112). The system also has a chamber (107), and a heater (106) coupled to the interior of the chamber (107) and operable to hold and heat the wafer (102). A showerhead (114) is also coupled to the interior of the chamber (107) and is operable to introduce a precursor gas (116) containing copper over the wafer (102). A shield (118) is coupled to the interior of the chamber (107) and is operable to partially shield the bevel (108), the edge (110), and the backside (112) of the wafer (102) from the precursor gas (116). There is an opening (122) in the chamber (107) through which a reactive backside gas (124) may be introduced under the wafer (102). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (102) on a heater (106) in a chamber (107).Type: GrantFiled: September 26, 2000Date of Patent: September 18, 2001Assignee: Texas Instruments IncorporatedInventors: Noel M. Russell, Anthony J. Konecni
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Patent number: 6284646Abstract: A method for forming a metal layer for an integrated circuit device includes forming a first conductive layer on an integrated circuit substrate. While forming the first conductive layer, a reflection index of the first conductive layer is monitored, and the formation of the first conductive layer is terminated when the reflection index of the first conductive layer reaches a predetermined value. More particularly, the first conductive layer can be an aluminum layer having a thickness in the range of approximately 500 Angstroms to 1500 Angstroms.Type: GrantFiled: August 19, 1998Date of Patent: September 4, 2001Assignee: Samsung Electronics Co., LtdInventor: Hyeun-Seog Leem
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Publication number: 20010017409Abstract: There is provided a means for selectively coating a coating liquid on a desired coating position when the coating liquid for forming an EL layer is coated. When the coating liquid is coated, a mask is provided between a coating liquid chamber and a substrate, and a voltage is applied to the mask, so that the coating liquid can be selectively coated on the desired coating position.Type: ApplicationFiled: February 21, 2001Publication date: August 30, 2001Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaaki Hiroki, Shunpei Yamazaki
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Patent number: 6274492Abstract: The invention relates to a process and a device for metallization of semiconductor structures, with which areas of the surface can be connected to be electrically conductive using strip conductors in one or a plurality of planes, and contacts between the strip conductors of different planes. The process for producing metallic coatings on semiconductor structures by depositing from a vapor phase under vacuum, in trenches produced for the strip conductors and holes for strip conductor connection in the substrate material such as SiO2 or other inorganic and organic materials is characterized in that a known per se pulsed vacuum-arc evaporator is used, a barrier layer being deposited on the surface of the trenches and holes of the substrates using the plasma of the evaporator and/or the trenches and holes being filled with low-impedance strip conductor material from a further plasma of said type of evaporator.Type: GrantFiled: January 3, 1999Date of Patent: August 14, 2001Assignees: Technische Universitaet Dresden, Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschnung E.V.Inventors: Wolfgang Klimes, Christian Wenzel, Norbert Urbansky, Peter Siemroth, Thomas Shuelke, Bernd Schultrich
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Patent number: 6210754Abstract: A method is proposed for use in a chamber used in IC fabrication to adjust for parallel alignment between a shower head and a heater platform in the chamber, so that later the deposition process performed in the chamber can result in an evenly deposited layer on the wafer. This method is characterized by the provision of a plurality of displacement gauges between the shower head and the heater platform, with the heater platform being adjusted in such a manner as to allow all the distance readings from the displacement gauges to be substantially equal to a predetermined fixed value. This not only allows the shower head and the heater platform to be aligned and parallel to each other, but also allows them to be separated by a predetermined, fixed distance.Type: GrantFiled: February 8, 1999Date of Patent: April 3, 2001Assignee: United Microelectronics Corp.Inventors: Tsung-Lin Lu, Ping-Chung Chung, Tso-Lung Lai
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Patent number: 6197684Abstract: A method for forming a metal/metal nitride layer. A dielectric layer is formed on a substrate comprising a conductive region. The dielectric layer comprises an opening exposing a portion of the conductive region. A conformal metal layer is formed on the dielectric layer by physical vapor deposition using a collimator to cover the exposed conductive region. A metal nitride layer is formed on the metal layer. A part of the metal layer may be exposed due to poor step coverage. An implanting process is performed on the metal nitride layer and on the exposed metal layer using a nitric gas.Type: GrantFiled: March 19, 1999Date of Patent: March 6, 2001Assignee: United Microelectronics Corp.Inventor: Chein-Cheng Wang
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Patent number: 6140235Abstract: The present invention provides a method and apparatus for filling submicron features on a substrate with a polycrystalline metal such as copper or a copper alloy comprising at least 90% by weight of copper. The method comprises deposition of a polycrystalline metal layer which bridges the submicron features and has a grain size smaller than the submicron features, and exposing the polycrystalline metal layer to a high pressure processing gas at a temperature less than one half of the absolute melting temperature to extrude the metal layer into the submicron features.Type: GrantFiled: December 5, 1997Date of Patent: October 31, 2000Assignee: Applied Materials, Inc.Inventors: Tse-Yong Yao, Barry Chin
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Patent number: 6139698Abstract: A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.Type: GrantFiled: February 3, 1997Date of Patent: October 31, 2000Assignee: Applied Materials, Inc.Inventors: Hougong Wang, Gongda Yao
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Patent number: 6136706Abstract: A process for producing titanium that includes forming gaseous titanium and then transforming the gaseous titanium into solid titanium through condensation. The titanium gas is formed by vaporizing titania with an electron beam in the presence of carbon. The gas-containing vapor is cooled to form a titanium liquid or solid.Type: GrantFiled: July 27, 1999Date of Patent: October 24, 2000Assignee: Idaho Research FoundationInventors: Vadim J. Jabotinski, Francis H. Froes