Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the steps of providing a semiconductor wafer including a dielectric layer formed on the wafer, the dielectric layer having vias formed therein and placing the wafer in a deposition chamber. The method further includes depositing a metal on the wafer to fill the vias wherein the metal depositing is initiated when the wafer is at a first temperature and the depositing is continued while heating the wafer to a target temperature which is greater than the first temperature.

Abstract: A method and apparatus are provided for forming cobalt on a silicon substrate containing native silicon oxide on the surface thereof wherein a modified vapor sputtering device is used. The vapor sputtering device is modified by providing an electrical circuit to ground whereby the wafer disposed in the device is electrically connected to the ground circuit. The ground circuit preferably contains a resistor therein to control wafer voltage and current flow from the wafer to ground. It has been found that providing a current flow from the wafer to ground and particularly in a ground circuit containing a resistor, provides an in-situ simultaneous cleaning of native oxide on the silicon surface and deposition of cobalt on cleaned silicon. The deposited cobalt containing substrate may then be readily annealed to form cobalt silicide evenly and uniformly across the desired regions of the wafer surface.

Abstract: Process for making a semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a metal halide as a precursor (e.g., BaF.sub.2 or SrF.sub.2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of a temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.

Abstract: A method of forming metallization layers and vias as part of an interconnect structure within an integrated circuit ("IC") is disclosed. The metallization layers and vias are formed of an alloy consisting of tungsten and one or more other materials such as aluminum, gold, copper, cobalt, titanium, molybdenum or platinum. In the alternative, the alloy may include aluminum and exclude tungsten. The alloy that forms the metallization layers and vias is deposited onto the IC substrate using ionized cluster beam ("ICB") apparatus. The IC substrate is an "in-process" IC in that various active devices (e.g., bipolar and/or MOS transistors), resistors and capacitors are formed in the substrate using conventional techniques prior to the ICB deposition of the alloy layers. Intermediate IC substrate processing steps (e.g., patterning and etching to form the vias) may take place in-between ICB deposition steps.

Abstract: A method for producing a noble metal-containing structure on a substrate, and a semiconductor component having such a noble metal-containing structure, include introducing a noble metal into a preliminary structure by converting a gaseous compound of the noble metal with a non-noble metal in a preliminary structure into elementary noble metal and a gaseous compound of the non-noble metal. The process continues until a desired amount of the non-noble metal in the preliminary structure is replaced by the noble metal.

Abstract: A soft metal conductor for use in a semiconductor device that has an upper-most layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent chemical mechanical polishing step.

Abstract: A method of creating a rerouting pattern on a semiconductor die or cube by providing a semiconductor die having an active surface with bond pads thereon and sides. A layer of electrically insulating material is sputtered over the active surface and the sides while exposing the bond pads. Electrically conductive material is formed over the electrically insulating material on the active surface and the sides. A selected portion of the electrically conductive material is removed with an excimer laser. The step of sputtering a layer of electrically insulating material over the active surface and said sides can include the steps of sputtering a layer of electrically insulating material over the active surface including the bond pads and the sides, masking the electrically insulating material to expose the region of the electrically insulating material over the bond pads and ablating the electrically insulating material with an excimer laser at the exposed region down to said bond pads.

Abstract: Ultra fine powder of metal dispersed in organic solvent is applied onto a surface of a semiconductor substrate, and heated to evaporate solvent and to sinter the ultra fine powder of metal. Deep contact holes or via holes, and grooves or trenches in the substrate can be filled up with metal, and the surface of the substrate can be covered with thin metal film.

Abstract: With a view to reducing the gate voltage in Field Emission Devices, three different methods for reducing the diameter of the gate opening in such devices are described. In the first method, metal is deposited on the gate electrode (which is made of polysilicon or amorphous silicon) at an oblique angle of incidence so that the vertical wall of the opening is coated, but not its lower surface. In the second method, all exposed surfaces are coated with metal. For both methods, metal is then removed from all non-polysilicon surfaces through a silicidation step followed by selective etching. In the third method, the gate electrode is selectively coated with a layer of tungsten. In all cases, a uniform reduction of the gate opening is achieved.

Abstract: An improved process for forming titanium silicide layers on semiconductor device silicon regions which have native oxide thereon utilizes a reactively sputter deposited layer of TiH.sub.x.ltoreq.2 followed by a rapid thermal anneal in a nitrogen bearing gas. This process results in lowered silicidation activation energy and lower anneal temperature requirements. Production throughput is improved with respect to prior art methods of removing the native oxide or minimizing its negative effect on silicide formation. The same process produces a titanium nitride/titanium silicide bilayer on silicon, and a titanium nitride/titanium bilayer on silicon dioxide. The thickness of the titanium nitride layer over silicon dioxide is enhanced by the use of TiH.sub.x.ltoreq.2 in place of Ti layers used in prior art, thus improving the utility of the titanium nitride as a diffusion barrier layer.

Abstract: A process of Pb/Sn evaporation eliminates haloes in the manufacture of solder bump interconnects. This robust process of forms solder bump interconnects and reduces critical molebdnum mask sensitivity. Vacuum evaporation through which Pb/Sn C4 pads are deposited is performed by maintaining parallel temperature gradients between the molybdenum mask and silicon wafer, thus resulting in elimination of connecting haloes and yield losses.