Utilizing Chemical Vapor Deposition (i.e., Cvd) Patents (Class 438/680)
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Patent number: 8492196Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.Type: GrantFiled: January 13, 2012Date of Patent: July 23, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Yaojian Lin
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Patent number: 8486193Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.Type: GrantFiled: January 25, 2012Date of Patent: July 16, 2013Assignee: SoitecInventor: Christiaan J. Werkhoven
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Patent number: 8486835Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.Type: GrantFiled: September 18, 2009Date of Patent: July 16, 2013Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
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Patent number: 8481381Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.Type: GrantFiled: September 14, 2011Date of Patent: July 9, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
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Patent number: 8476161Abstract: Provided is a Cu electrical interconnection film forming method, wherein an adhesive layer (base film) having improved adhesiveness with a Cu electrical interconnection film is used, in a semiconductor device manufacturing process. After forming a barrier film on a substrate whereupon a hole or the like is formed, a PVD-Co film or a CVD-Co film or an ALD-Co film is formed on the barrier film. Then, after filling up or burying the hole or the like, which has the Co film formed on the surface, with a CVD-Cu film or a PVD-Cu film, heat treatment is performed at a temperature of 350° C. or below, and the Cu electrical interconnection film is formed.Type: GrantFiled: July 14, 2009Date of Patent: July 2, 2013Assignee: Ulvac, Inc.Inventors: Shoichiro Kumamoto, Masamichi Harada, Harunori Ushikawa
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Publication number: 20130164936Abstract: A film deposition method includes a film depositing step of depositing titanium nitride on a substrate mounted on a substrate mounting portion of a turntable, which is rotatably provided in a vacuum chamber, by alternately exposing the substrate to a titanium containing gas and a nitrogen containing gas which is capable of reacting with the titanium containing gas while rotating the turntable; and an exposing step of exposing the substrate on which the titanium nitride is deposited to the nitrogen containing gas, the film depositing step and the exposing step being continuously repeated to deposit the titanium nitride of a desired thickness.Type: ApplicationFiled: December 26, 2012Publication date: June 27, 2013Applicant: Tokyo Electron LimitedInventor: Tokyo Electron Limited
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Patent number: 8471353Abstract: A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D1 of a portion covering the side wall of the mesa is equal to or greater than 850 nm.Type: GrantFiled: June 8, 2010Date of Patent: June 25, 2013Assignee: Renesas Electronics CorporationInventors: Tomoaki Koi, Isao Watanabe, Takashi Matsumoto
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Patent number: 8466069Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can form a plurality of grooves extending in a first direction on a semiconductor substrate. The method can form an insulating layer on the inner face of the groove and on the top face of the semiconductor substrate. The method can deposit a first conductive layer on the insulating layer so as to fill in the groove. The method can deposit a second conductive layer on the first conductive layer. The method can form a hard mask in a region including part of a region immediately above the groove on the second conductive layer. The method can form a columnar body including the hard mask and the second conductive layer by etching the second conductive layer using the hard mask as a mask.Type: GrantFiled: September 14, 2011Date of Patent: June 18, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Toshiyuki Sasaki
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Patent number: 8455360Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.Type: GrantFiled: March 28, 2011Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
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Patent number: 8455365Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.Type: GrantFiled: May 19, 2011Date of Patent: June 4, 2013Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8455352Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.Type: GrantFiled: May 24, 2012Date of Patent: June 4, 2013Assignee: Applied Materials, Inc.Inventors: Bo Zheng, Arvind Sundarrajan, Xinyu Fu
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Patent number: 8455314Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.Type: GrantFiled: May 27, 2011Date of Patent: June 4, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
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Patent number: 8450819Abstract: In a plasma torch unit, a conductor rod having a spiral shape is disposed inside a quartz pipe having a surface coated with boron glass, and a brass block is disposed on the periphery thereof. While a gas is being supplied into a cylindrical chamber, a high-frequency power is supplied to the conductor rod and a plasma is generated in the cylindrical chamber, so that a base material is irradiated with the plasma.Type: GrantFiled: November 8, 2011Date of Patent: May 28, 2013Assignee: Panasonic CorporationInventors: Tomohiro Okumura, Mitsuo Saitoh, Ichiro Nakayama, Taro Kitaoka
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Patent number: 8450191Abstract: Methods of forming polysilicon layers are described. The methods include forming a high-density plasma from a silicon precursor in a substrate processing region containing the deposition substrate. The described methods produce polycrystalline films at reduced substrate temperature (e.g. <500° C.) relative to prior art techniques. The availability of a bias plasma power adjustment further enables adjustment of conformality of the formed polysilicon layer. When dopants are included in the high density plasma, they may be incorporated into the polysilicon layer in such a way that they do not require a separate activation step.Type: GrantFiled: April 19, 2011Date of Patent: May 28, 2013Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Xiaolin Chen, Young S. Lee
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Patent number: 8445381Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.Type: GrantFiled: December 20, 2007Date of Patent: May 21, 2013Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sundar Narayanan
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Patent number: 8440566Abstract: The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film.Type: GrantFiled: July 22, 2011Date of Patent: May 14, 2013Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Koji Kato, Shoji Kano, Waichi Yamamura
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Patent number: 8440556Abstract: Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products.Type: GrantFiled: December 22, 2010Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Scott Bruce Clendenning, Niloy Mukherjee
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Publication number: 20130115768Abstract: In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. Nickel thin films can be used directly in silicidation and germanidation processes.Type: ApplicationFiled: August 22, 2012Publication date: May 9, 2013Inventors: Viljami J. Pore, Suvi P. Haukka, Tom E. Blomberg, Eva E. Tois
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Patent number: 8435905Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.Type: GrantFiled: June 13, 2006Date of Patent: May 7, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Sadayoshi Horii, Hideharu Itatani, Kazuhiro Harada
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Patent number: 8420466Abstract: A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface and a floating gate on the P? polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer.Type: GrantFiled: October 27, 2008Date of Patent: April 16, 2013Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fumitake Mieno
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Patent number: 8420534Abstract: Methods of forming a PrCaMnO (PCMO) material by atomic layer deposition. The methods include separately exposing a surface of a substrate to a manganese-containing precursor, an oxygen-containing precursor, a praseodymium-containing precursor and a calcium-containing precursor. The resulting PCMO material is crystalline. A semiconductor device structure including the PCMO material, and related methods, are also disclosed.Type: GrantFiled: October 12, 2010Date of Patent: April 16, 2013Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Publication number: 20130084700Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.Type: ApplicationFiled: October 3, 2012Publication date: April 4, 2013Applicant: IMECInventor: IMEC
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Patent number: 8409988Abstract: Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus capable of improving defects of conventional CVD and ALD methods, satisfying requirements of film-thinning, and realizing high film-forming rate. The method includes forming a first layer including a first element being able to become solid state by itself on a substrate by supplying a gas containing the first element into a process vessel in which the substrate is accommodated under a condition that a CVD reaction occurs, and forming a second layer including the first element and a second element being unable to become solid state by itself by supplying a gas containing the second element into the process vessel to modify the first layer, wherein a cycle including the forming of the first layer and the forming of the second layer is performed at least once to form a thin film including the first and second elements and having a predetermined thickness.Type: GrantFiled: May 25, 2011Date of Patent: April 2, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Yushin Takasawa, Hajime Karasawa, Yoshiro Hirose
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Patent number: 8410002Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.Type: GrantFiled: November 12, 2010Date of Patent: April 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Patent number: 8409985Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.Type: GrantFiled: April 27, 2011Date of Patent: April 2, 2013Assignee: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
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Patent number: 8399329Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.Type: GrantFiled: March 12, 2010Date of Patent: March 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8389408Abstract: Provided are methods of forming a semiconductor device. The methods include providing a first precursor and a substitute gas into a reaction chamber having a substrate therein, the first precursor having a first substituent and further providing a second precursor into the reaction chamber. Either the first precursor or the second precursor includes a metal element and the other includes a silicon element, at least one of the first substituents of the first precursor are substituted with the substitute gas, the first precursor substituted with the substitute gas is adsorbed onto the substrate, and the second precursor is reacted with the adsorbed first precursor.Type: GrantFiled: June 23, 2010Date of Patent: March 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Lim Park, Jinil Lee, Changsu Kim, Sugwoo Jung
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Patent number: 8389399Abstract: A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.Type: GrantFiled: November 2, 2009Date of Patent: March 5, 2013Assignee: SanDisk 3D LLCInventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
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Patent number: 8377803Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.Type: GrantFiled: February 16, 2012Date of Patent: February 19, 2013Assignee: Intermolecular, Inc.Inventors: Philip A. Kraus, Thai Cheng Chua, Sandeep Nijhawan
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Patent number: 8361902Abstract: A cleaning control apparatus capable of performing a cleaning process efficiently regardless of qualities and thicknesses of films formed in a process tube and a gas supply nozzle. The cleaning control apparatus employs cleaning request signal output units configured to output cleaning request signals requesting cleaning processes of a silicon-containing gas supply system and nitriding source gas supply system when accumulated amounts of the molecules of the silicon-containing gas and the nitriding source gas exceeds preset values.Type: GrantFiled: July 5, 2012Date of Patent: January 29, 2013Assignee: Hitachi Kokusai Electric Inc.Inventor: Tomohide Kato
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Patent number: 8357614Abstract: Disclosed are ruthenium-containing precursors and methods of using the same in CVD and ALD.Type: GrantFiled: December 30, 2010Date of Patent: January 22, 2013Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventor: Satoko Gatineau
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Publication number: 20130012022Abstract: A method for larger-area fabrication of uniform silicon nanowire arrays is disclosed. The method includes forming a metal layer with a predetermined thickness on a substrate whose surface has a silicon material by a coating process, the metal layer selected from the group consisting of Ag, Au and Pt; and performing a metal-induced chemical etching for the silicon material by using an etching solution. Accordingly, a drawback that Ag nanoparticles are utilized to perform the metal-induced chemical etching in prior art is solved.Type: ApplicationFiled: January 4, 2012Publication date: January 10, 2013Applicant: National Taiwan University of Science and TechnologyInventors: Yung-Jr Hung, San-liang Lee, Kai-Chung Wu
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Patent number: 8349709Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: GrantFiled: May 18, 2010Date of Patent: January 8, 2013Assignee: Elpida Memory, Inc.Inventors: Michio Inoue, Yorio Takada
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Patent number: 8349726Abstract: There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapor deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.Type: GrantFiled: September 15, 2006Date of Patent: January 8, 2013Assignee: NXP B.V.Inventor: Wim Besling
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Publication number: 20130005146Abstract: The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicants: Applied Materials, Inc., International Business Machines CorporationInventors: Mihaela Balseanu, Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, JR., Son Nguyen, Li-Qun Xia
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Patent number: 8344300Abstract: A substrate heating apparatus configured to be coupled to a processing system and radiatively heat a substrate is described. The substrate heating apparatus includes a radiative heat source coupled to a processing system and configured to produce electromagnetic (EM) radiation, a translucent object positioned between the radiative heat source and the substrate along a the EM radiation path, and an opaque object also positioned between the radiative heat source and the substrate along the EM radiation path. The translucent object includes at least one textured surface to cause random refraction of the EM radiation passing through the translucent object, or an optical waveguide configured to encapsulate the opaque object and direct the EM radiation around the opaque object, or both, to prevent creation of a shadow of the opaque object on the substrate.Type: GrantFiled: June 14, 2010Date of Patent: January 1, 2013Assignee: Tokyo Electron LimitedInventor: Ronald Nasman
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Patent number: 8338298Abstract: The present inventors have found that a wafer process of VLSI (Very Large Scale Integration) has the following problem, that is, generation of foreign matters due to moisture from a wafer as a result of degassing when a barrier metal film or a first-level metal interconnect layer is formed by sputtering as a preliminary step for the formation of a tungsten plug in a pre-metal step. To overcome the problem, the present invention provides a manufacturing method of a semiconductor integrated circuit device including, in a plasma process, in-situ monitoring of moisture in a processing chamber by receiving an electromagnetic wave generated from plasma.Type: GrantFiled: September 9, 2009Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Kazuyuki Fujii, Toshihiko Minami, Hideaki Kanazawa
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Patent number: 8333840Abstract: A metal organic chemical vapor deposition apparatus includes reaction chambers in which nitride layers is deposited on a substrate using a group III-V material, a buffer chamber connected to the reaction chambers and in which a transfer robot is disposed to transfer the substrate into the reaction chambers, a gas supply device configured to selectively supply one or more of hydrogen, nitrogen, and ammonia gases into the buffer chamber so that when the buffer chamber communicates with one of the reaction chambers, the buffer chamber has the same atmosphere as an atmosphere of the reaction chamber, and a heater disposed in the buffer chamber. Nitride layers are deposited on a substrate in the reaction chambers, and the temperature and gas atmosphere of the buffer chamber are adjusted such that when the substrate is transferred, epitaxial layers formed on the substrate can be stably maintained.Type: GrantFiled: September 29, 2010Date of Patent: December 18, 2012Assignee: Ligadp Co., Ltd.Inventor: Jin Joo
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Patent number: 8329559Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.Type: GrantFiled: April 19, 2007Date of Patent: December 11, 2012Assignee: The Regents of the University of CaliforniaInventors: Hideki Takeuchi, Emmanuel P. Quevy, Tsu-Jae King, Roger T. Howe
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Patent number: 8318590Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.Type: GrantFiled: February 17, 2012Date of Patent: November 27, 2012Assignee: Intermolecular, Inc.Inventors: Philip A. Kraus, Thai Cheng Chua, Sandeep Nijhawan
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Patent number: 8283205Abstract: A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.Type: GrantFiled: January 13, 2012Date of Patent: October 9, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
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Patent number: 8278216Abstract: The present invention provides methods of selectively depositing refractory metal and metal nitride cap layers onto copper lines inlaid in a dielectric layer. The methods result in formation of a cap layer on the copper lines without significant formation on the surrounding dielectric material. The methods typically involve exposing the copper lines to a nitrogen-containing organo-metallic precursor and a reducing agent under conditions that the metal or metal nitride layer is selectively deposited. In a particular embodiment, an amino-containing tungsten precursor is used to deposit a tungsten nitride layer. Deposition methods such as CVD or ALD may be used.Type: GrantFiled: August 18, 2006Date of Patent: October 2, 2012Assignee: Novellus Systems, Inc.Inventors: Glenn Alers, Nerissa Draeger, Michael Carolus, Julie Carolus, legal representative
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Publication number: 20120244703Abstract: A tray for film formation by a CVD method includes a tray main body (2) and a supporting member (3) mounted on the tray main body (2) for supporting a silicon wafer (5). The supporting member (3) has a holding portion (3c), on which the silicon wafer (5) is directly placed. The holding portion (3c) has its lower surface (3d) apart from a surface (2a) of the tray main body that is opposed to and apart from the supported silicon wafer (5), whereby the thickness distribution of an oxide film formed on the silicon wafer can be made uniform. The tray has a structure for reducing a contact area between the supporting member (3) and the tray main body (2), with the holding portion (3c) having a tilted surface with its inner circumferential side closer to the tray main body surface (2a) that is opposed to the silicon wafer.Type: ApplicationFiled: November 29, 2010Publication date: September 27, 2012Applicant: SUMCO CORPORATIONInventors: Takashi Nakayama, Tomoyuki Kabasawa, Takayuki Kihara
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Patent number: 8271121Abstract: An arrangement for implementing an automatic in-situ process control scheme during execution of a recipe is provided. The arrangement includes control-loop sensors configured at least for collecting a first set of sensor data to facilitate monitoring set points during the recipe execution, wherein the control-loop sensors being part of a process control loop. The arrangement also includes independent sensors configured at least for collecting a second set of sensor data, which is not part of the process control loop. The arrangement yet also includes a hub configured for at least receiving at least one of the first set of sensor data and the second set of sensor data. The arrangement yet further includes an analysis computer communicably coupled with the hub and configured for performing analysis of at least one of the first set of sensor data and the second set of sensor data.Type: GrantFiled: June 29, 2010Date of Patent: September 18, 2012Assignee: Lam Research CorporationInventors: Vijayakumar C. Venugopal, Neil Martin Paul Benjamin
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Publication number: 20120231164Abstract: Methods and precursors are provided for deposition of elemental manganese films on surfaces using metal coordination complexes comprising an eta-3-bound monoanionic four-electron donor ligands selected from amidinate, mixed ene-amido and allyl, or eta-2 bound amidinate ligand. The ligands are selected from amidinate, ene-amido, and allyl.Type: ApplicationFiled: March 8, 2012Publication date: September 13, 2012Applicant: Applied Materials, Inc.Inventors: David Thompson, Jeffrey W. Anthis
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Patent number: 8263421Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.Type: GrantFiled: November 12, 2010Date of Patent: September 11, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
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Patent number: 8258060Abstract: The sheet structure includes a plurality of linear structure bundles including a plurality of linear structures of carbon atoms arranged at a first gap, and arranged at a second gap larger than the first gap, a graphite layer formed in a region between the plurality of linear structure bundles and connected to the plurality of linear structure bundles, and a filling layer filled in the first gap and the second gap and retaining the plurality of linear structure bundles and the graphite layer.Type: GrantFiled: August 13, 2010Date of Patent: September 4, 2012Assignee: Fujitsu LimitedInventors: Daiyu Kondo, Taisuke Iwai, Yoshitaka Yamaguchi, Ikuo Soga
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Patent number: 8242498Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.Type: GrantFiled: November 24, 2010Date of Patent: August 14, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Fumitake Nakanishi
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Publication number: 20120199887Abstract: Methods, apparatus, and systems for depositing tungsten having tailored stress levels are provided. According to various embodiments, the methods involve depositing high stress or low stress tungsten films. In certain embodiments depositing high stress tungsten involves a multi-stage chemical vapor deposition (CVD) process including a low temperature deposition followed by a high temperature deposition. In certain embodiments depositing low stress tungsten involves a CVD process using a relatively low tungsten precursor flow. Also provided are new classes of high and low stress tungsten films, which may also have low resistivity and/or high reflectivity. Also provided are integration methods involving depositing high or low stress tungsten, for example as contacts and/or metal gates, and semiconductor devices incorporating the tungsten films.Type: ApplicationFiled: February 3, 2011Publication date: August 9, 2012Inventors: Lana Chan, Feng Chen, Roey Shaviv
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Patent number: 8236692Abstract: Efficient cleaning is possible although the film qualities and thicknesses of a reaction tube and a gas supply nozzle are different. There is provided a method of manufacturing a semiconductor device. The method includes forming a film on a substrate, performing a first cleaning process to remove a first deposition substance attached to an inner wall of a gas introducing part, and performing a second cleaning process to remove a second deposition substance attached to an inside of a process chamber and having a chemical composition different from that of the first deposition substance. In the first cleaning process, cleaning conditions are set according to the accumulated supply time of a first source gas supplied to the inside of the process chamber through the gas introducing part, and in the second cleaning process, cleaning conditions are set according to the accumulated thickness of a film formed on the substrate.Type: GrantFiled: December 22, 2009Date of Patent: August 7, 2012Assignee: Hitachi Kokusai Electric Inc.Inventor: Tomohide Kato