Aluminum Or Aluminum Alloy Conductor Patents (Class 438/688)
  • Publication number: 20090191698
    Abstract: Disclosed is display part such as a TFT array panel comprising an aluminum layer, and a molybdenum layer formed on the aluminum layer. The thickness of the molybdenum layer may be about 10% to about 40% the thickness of the aluminum layer. As a result, a top surface of the aluminum layer may have a width about equal to a bottom surface of the molybdenum layer. Accordingly, it is an aspect of the present invention to provide a TFT array panel comprising an aluminum wiring on which aluminum protrusion is reduced or eliminated.
    Type: Application
    Filed: April 2, 2009
    Publication date: July 30, 2009
    Inventors: Je-hun Lee, Chang-ob Jeong, Jin-kwan Kim, Yang-bo Bae, Beom-seok Cho, Jun-hyung Souk
  • Patent number: 7566647
    Abstract: A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed on the substrate. Then, the aluminum pad material layer is patterned to form the aluminum pad layer which includes a plurality of aluminum pads and a plurality of dummy patterns, wherein the dummy patterns are distributed in the spaces between the aluminum pads. Besides, routings can be further disposed in the aluminum pad layer and the dummy patterns are distributed in the spaces between the aluminum pads, between the aluminum pads and the routings, or between the routings.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: July 28, 2009
    Assignee: United Microelectronics Corp.
    Inventor: Hsin-Ming Hou
  • Patent number: 7563704
    Abstract: An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: July 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Kaushik Chanda, Lawrence A. Clevenger, Yun-Yu Wang, Daewon Yang
  • Patent number: 7538001
    Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer
  • Patent number: 7521352
    Abstract: A method for manufacturing a semiconductor device includes forming a copper anti-diffusion film on a copper trench wiring layer, and forming an opening portion in the copper anti-diffusion film by laser ablation, the opening portion being formed in a region corresponding to an alignment region used for lithography process for forming an aluminum wiring on the copper trench wiring layer.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: April 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Shinomiya, Jun Hirota, Mie Matsuo, Hisashi Kaneko
  • Patent number: 7517793
    Abstract: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: April 14, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Hee Hong, Cheol Mo Jeong, Jung Geun Kim, Eun Soo Kim
  • Publication number: 20090061613
    Abstract: Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer.
    Type: Application
    Filed: May 22, 2008
    Publication date: March 5, 2009
    Inventors: Sang-moo Choi, Kwang-soo Seol, Woong-chul Shin, Sang-jin Park, Eun-ha Lee, Jung-hun Sung
  • Patent number: 7488681
    Abstract: Disclosed is a method for fabricating an Al metal line. The method includes forming an insulating layer on a semiconductor substrate; forming a Ti layer, a bottom TiN layer, an Al layer and a top TiN layer in successive order on the insulating layer; plasma-treating the top TiN layer; forming a photoresist pattern on the plasma-treated top TiN layer; and etching the plasma-treated top TiN layer, the Al layer, the bottom TiN layer, and the Ti layer using the photoresist pattern as an etching mask, thereby forming the Al metal line.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: February 10, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheon Man Shim
  • Patent number: 7488684
    Abstract: An organic aluminum precursor includes aluminum as a central metal, and borohydride and trimethylamine as ligands. In a method of forming an aluminum layer or wire, the organic aluminum presursor is introduced onto a substrate, and then thermally decomposed. The aluminum decomposed from the organic aluminum precursor is deposited on the substrate.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: February 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Sik Choi, Jung-Ho Lee, Jun-Hyun Cho, Youn-Joung Cho, Tae-Sung Kim, Mi-Ae Kim, Kyoo-Chul Cho, Dong-Jun Lee
  • Patent number: 7473644
    Abstract: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: January 6, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Richard H. Lane, Fred Fishburn
  • Patent number: 7468321
    Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: December 23, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Chia-Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Wen-Hsiang Tseng
  • Patent number: 7468319
    Abstract: The present invention relates to a method for preventing a metal corrosion in a semiconductor device. The present method includes the steps of etching of a metal layer in a chamber, the metal layer having a photoresist pattern thereon or thereover; oxidizing a surface of the metal layer using a plasma comprising N2O in the same chamber; and removing the photoresist. Therefore, metal corrosion as well as bridges between metal wirings can be suppressed or prevented, thereby improving the profile of metal layer and the reliability and yield of the semiconductor device.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: December 23, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Publication number: 20080305634
    Abstract: The object of this invention is to prevent unwanted separation of a deposited metal film from a member, such as an anti-adhesion plate, in the chamber of a metal film forming device. In a sputtering device, metal particles sputtered from the surface of a target 12 in a chamber 10 are not only dispersed or scattered toward a semiconductor wafer 22 on the front of the target, but also adhere to shield member 30 to form a deposited metal film 40. Shield member 30 is made of stainless steel, for example, a plasma spray film made of aluminum or an aluminum alloy is formed on its anti-adhesion surface (inner wall surface), and the surface of the plasma spray film is suitably roughened.
    Type: Application
    Filed: May 19, 2008
    Publication date: December 11, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Toshifumi Igarashi
  • Patent number: 7462942
    Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: December 9, 2008
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Kim Hwee Tan, Ch'ng Han Shen, Rosemarie Tagapulot, Yin Yen Bong, Ma L. Nang Htoi, Lim Tiong Soon, Shikui Lui, Balasubramanian Sivagnanam
  • Publication number: 20080296771
    Abstract: A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventors: Mrinal Kanti Das, Qingchun Zhang, John M. Clayton, JR., Matthew Donofrio
  • Patent number: 7459387
    Abstract: A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad may include a lower layer of aluminum, copper, or alloys thereof, and an upper layer including at least one film of a metal and/or metallic alloy including nickel, palladium, or alloys thereof, and being deposited by an electroless chemical process.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 2, 2008
    Assignee: STMicroelectronics S.r.L.
    Inventors: Roberto Tiziani, Carlo Passagrilli
  • Patent number: 7452805
    Abstract: A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 ?m2 and a PVD aluminum base conductor filled in the opening.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: November 18, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsiung Wang, Chien-Chao Huang, Chenming Hu, Horng-Huei Tseng
  • Patent number: 7446037
    Abstract: In semiconductor integrated circuit and device fabrication interconnect metallization is accomplished by a clad Ag deposited on a SiO2 level on a Si surface. The clad Ag has a layer of an alloy of Ag and Al (5 atomic %) contacting the SiO2, a layer of substantially pure Ag and an outer layer of the Ag and Al alloy. The alloy improves adhesion to the SiO2, avoids agglomeration of the Ag, reduces or eliminates diffusion at the SiO2 surface, reduces electromigration and presents a passive exterior surface.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: November 4, 2008
    Inventors: Terry L. Alford, Ekta Misra
  • Patent number: 7432203
    Abstract: Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: October 7, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Publication number: 20080239629
    Abstract: A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Barry J. Liles, Colin S. Whelan
  • Publication number: 20080233742
    Abstract: A contact hole is formed in an interlayer insulating layer disposed on a semiconductor substrate. The semiconductor substrate is loaded into a reaction chamber. A reaction gas including an aluminum precursor is injected into the reaction chamber. Reaction energy is supplied to the reaction chamber so as to allow thermal decomposition of the aluminum precursor. The injecting of the reaction gas and the supplying of the reaction energy are periodically repeated to deposit a first aluminum layer on the semiconductor substrate. A second aluminum layer is deposited to fill the contact hole.
    Type: Application
    Filed: December 5, 2007
    Publication date: September 25, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Choon Hwan KIM, II Cheol Rho
  • Patent number: 7425765
    Abstract: A high melting point solder alloy superior in oxidation resistance, in particular a solder alloy provided with both a high oxidation resistance and high melting point suitable for filling fine through holes of tens of microns in diameter and high aspect ratios and forming through hole filling materials, comprising a zinc-aluminum solder alloy containing 0.001 wt % to 1 wt % of aluminum and the balance of zinc and unavoidable impurities.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: September 16, 2008
    Assignee: Fujitsu Limited
    Inventors: Masayuki Kitajima, Tadaaki Shono, Ryoji Matsuyama
  • Patent number: 7416932
    Abstract: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: August 26, 2008
    Assignee: DENSO CORPORATION
    Inventor: Hiroyasu Itou
  • Patent number: 7402519
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
  • Publication number: 20080157284
    Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
  • Patent number: 7381645
    Abstract: The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride, further metalization strata are produced (114). The result is an integrated circuit arrangement having connections which have a low electrical resistance. The circuit arrangement is particularly suitable for the purpose of switching high powers.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: June 3, 2008
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Göllner, Herbert Obermeier
  • Patent number: 7378002
    Abstract: An aluminum sputtering process including RF biasing the wafer and a two-step aluminum fill process and apparatus used therefor to fill aluminum into a narrow via hole by sputtering under two distinctly different conditions, preferably in two different plasma sputter reactors. The first step includes sputtering a high fraction of ionized aluminum atoms onto a relatively cold wafer, e.g., held at less than 150° C., and relatively highly biased to attract aluminum atoms into the narrow holes and etch overhangs. The second step includes more neutral sputtering onto a relatively warm wafer, e.g. held at greater than 250° C., and substantially unbiased to provide a more isotropic and uniform aluminum flux. The magnetron scanned about the back of the aluminum target may be relatively small and unbalanced in the first step and relatively large and balanced in the second.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: May 27, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Wei Ti Lee, Ted Guo, Sang-Ho Yu
  • Patent number: 7358195
    Abstract: In etching a metal line formed as a dual layer of aluminum alloy and molybdenum, the metal line consisting of the dual layer of aluminum alloy and molybdenum is etched through one-time wet etching by applying the etchant including HNO3, HClO4, a Ferric compound (Fe3+), and a Flouro compound (F?), the process can be reduced and a metal line having a good profile can be formed.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: April 15, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Soon-Ho Choi, Hyuk-Cheol Son, Kum-Chul Oh, Seung-Hwan Chon, Young-Chul Park
  • Patent number: 7344986
    Abstract: The present invention relates to a plating solution useful for forming embedded interconnects by embedding a conductive material in fine recesses for interconnects provided in the surface of a substrate, such as a semiconductor substrate, or for forming a protective layer for protecting the surface of embedded interconnects, a semiconductor device manufactured by using the plating solution and a method for manufacturing the semiconductor device. The plating solution contains copper ions, metal ions of a metal, and the metal is capable of forming with copper a copper alloy in which the metal does not form a solid solution with copper, a complexing agent, and a reducing agent free from alkali metal.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: March 18, 2008
    Assignee: Ebara Corporation
    Inventors: Hiroaki Inoue, Xinming Wang, Moriji Matsumoto, Makoto Kanayama
  • Publication number: 20080064204
    Abstract: A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.
    Type: Application
    Filed: December 27, 2006
    Publication date: March 13, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Eun Soo Kim, Cheol Mo Jeong, Seung Hee Hong
  • Patent number: 7341942
    Abstract: A method for forming a metal line of a semiconductor device forms an aluminum line having an excellent orientation. A specific resistance of a metal line is reduced, thereby enabling sufficient supply of a desired electric current. The method includes steps of forming a lower reflection preventing layer on a silicon wafer, forming a first aluminum layer on the lower reflection preventing layer, forming a second aluminum layer on the first aluminum layer, lowering a surface roughness of the second aluminum layer, forming an upper reflection preventing layer on the second aluminum layer, and forming an aluminum line.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 11, 2008
    Assignee: Dongbu Electronics Co., Ltd
    Inventor: Jae Suk Lee
  • Patent number: 7329365
    Abstract: An etchant for removing an indium oxide layer includes sulfuric acid as a main oxidizer, an auxiliary oxidizer such as H3PO4, HNO3, CH3COOH, HClO4, H2O2, and a Compound A that is obtained by mixing potassium peroxymonosulfate (2KHSO5), potassium bisulfate (KHSO4), and potassium sulfate (K2SO4) together in the ratio of 5:3:2, an etching inhibitor comprising an ammonium-based material, and water. The etchant may remove desired portions of the indium oxide layer without damage to a photoresist pattern or layers underlying the indium oxide layer.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: February 12, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Je Cho, Seung-Yong Lee, Joon-Woo Lee, Jae-Yeon Lee, Seung-Hwan Chon, Yong-Suk Choi, Young-Chul Park, Jin-Su Kim, Kyu-Sang Kim, Dong-Uk Choi, Kwan-Tack Lim
  • Publication number: 20080003816
    Abstract: An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the lower wiring layer is formed by etching the interlayer insulation film. A wetting layer is formed on an inner wall of the contact hole. An anti-deposition layer is formed around an entrance of the contact hole to prevent an aluminum layer from being deposited around the entrance of the contact hole. The contact hole is filled with the aluminum layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Hyun Phill Kim
  • Patent number: 7312152
    Abstract: The corrosion of aluminum-based metal films may be minimized by applying a lactate-containing solution to the aluminum-based metal films before the aluminum-based metal films are etched. The lactate-containing solution is applied to the aluminum-based metal film before the film is etched with a corrosive etchant. Minimizing the corrosion of the aluminum-based film may increase the yield and performance of the highly reflective pixel arrays that are formed from the aluminum-based metal for use in liquid crystal on silicon (LCOS) microprocessors for digital televisions.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Adam R. Stephenson, Hue D. Chiang
  • Patent number: 7297640
    Abstract: A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High E/D ratio maintains the gap openings without necking. In the second step, a lower argon concentration and lower E/D ratio are used. Since observed metal defects are caused by argon diffusion in the top 200-300 nm of the HDP-CVD film, by controlling argon concentration in the top part of the film (i.e. second step deposition) to a low value, a reduced number of metal defects are achieved.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: November 20, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jun Xie, Hoon Lian Yap, Chuin Boon Yeap, Weoi San Lok
  • Publication number: 20070257370
    Abstract: A multilayer electrode structure has a conductive layer including aluminum, an oxide layer formed on the conductive layer, and an oxygen diffusion barrier layer. The oxide layer includes zirconium oxide and/or titanium oxide. The oxygen diffusion barrier layer is formed at an interface between the conductive layer and the oxide layer by re-oxidizing the oxide layer. The oxygen diffusion barrier layer includes aluminum oxide.
    Type: Application
    Filed: April 11, 2007
    Publication date: November 8, 2007
    Inventors: Jong-Cheol Lee, Kyoung-Ryul Yoon, Ki-Vin Im, Jae-Hyun Yeo, Eun-Ae Chung, Jin-Il Lee
  • Patent number: 7288442
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
  • Publication number: 20070243703
    Abstract: A method of making a semiconductor device includes providing a laminate substrate made by bonding a II-VI or III-V semiconductor laminate film to a support substrate, and preparing the laminate film to enable growth of a II-VI or III-V semiconductor device layer on the laminate substrate.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 18, 2007
    Inventors: Thomas Pinnington, Sean Olson, James M. Zahler, Charles Tsai
  • Patent number: 7276434
    Abstract: A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film in a region having a predetermined area including the inner surface of the contact hole on the surface of the semiconductor substrate, an step of forming an aluminum-containing thin film on the surface of the semiconductor substrate on which the silicon-containing thin film is formed, and a step of heating the semiconductor substrate on which the aluminum-containing thin film is formed to such a temperature as to cause silicon to diffuse with respect to aluminum.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: October 2, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 7262135
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventor: John Smythe
  • Patent number: 7259096
    Abstract: A method for forming an Al interconnect is disclosed. A disclosed method comprises: depositing a Ti layer on a substrate having predetermined devices; depositing a TiN layer on the entire surface of the Ti layer by performing a CVD process; performing a plasma treatment for the TiN layer; depositing an Al layer on the TiN layer; and forming an ARC on the entire surface of the Al layer.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: August 21, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jung Joo Kim
  • Patent number: 7241692
    Abstract: A method for chemical mechanical polishing of mirror structures. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a first dielectric layer overlying the semiconductor substrate and forming an aluminum layer overlying the first dielectric layer, the aluminum layer having an upper surface with a predetermined roughness of greater than 20 Angstroms RMS. The method also includes processing regions overlying the upper surface of the aluminum layer using a touch polishing process to reduce a surface roughness of the upper surface of aluminum layer to less than 5 Angstroms to form a mirror surface on the aluminum layer. Preferably, a protective layer is formed overlying the mirror surface on the aluminum layer.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: July 10, 2007
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Chris C. Yu, Chun Xiao Yang
  • Patent number: 7241685
    Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: July 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hideo Miura, Shinji Nishihara, Masashi Sahara
  • Patent number: 7235310
    Abstract: A hillock-free conductive layer comprising at least two aluminum (Al) layers formed on a substrate, wherein said at least two Al layers comprise a barrier Al layer formed on the substrate, and a pure Al layer formed on the barrier Al layer. The barrier Al layer could be an aluminum nitride (AlNx) layer, an aluminum oxide (AlOx) layer, an aluminum oxide-nitride (AlOxNy) layer, or an Al—Nd alloy layer. Also, the pure Al layer is physically thicker than the barrier Al layer, for effectively inhibiting the occurrence of hillocks and the like.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: June 26, 2007
    Assignee: CHI MEI Optoelectronics Corp.
    Inventors: Kung-Hao Chang, Shyi-Ming Yeh, Jui-Tang Yin
  • Patent number: 7226854
    Abstract: Methods of forming metal lines in semiconductor devices are disclosed. One example method may include forming lower metal lines and forming an insulation layer on the lower metal lines; etching said insulation layer to a depth; and depositing a material for upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines. The example method may also include exposing the lower metal lines by etching said upper metal lines and the insulation layer and depositing a material for contact plugs on the entire surfaces of said upper metal lines and said insulation layer and planarizing the material for said contact plugs to form the contact plugs.
    Type: Grant
    Filed: December 26, 2003
    Date of Patent: June 5, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheolsoo Park
  • Patent number: 7226858
    Abstract: A submicron contact opening fill using a chemical vapor deposition (CVD) TiN liner/barrier and a high temperature, e.g., greater than about 385° C., physical vapor deposition (PVD) aluminum alloy layer that substantially fills the submicron contact.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: June 5, 2007
    Assignee: Microchip Technology Incorporated
    Inventors: Jacob Lee Williams, Harold E. Kline
  • Patent number: 7217661
    Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: May 15, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Wing-Cheong Gilbert Lai, Gurtej Singh Sandhu
  • Patent number: 7214602
    Abstract: A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further includes annealing the layer of iridium, forming a dielectric layer on the layer of iridium, and forming a conductive layer on the dielectric layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 7196008
    Abstract: For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al2O3 for example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: March 27, 2007
    Assignee: Spansion LLC
    Inventors: Hidehiko Shiraiwa, Satoshi Torii, Jaeyong Park, Joong Jeon
  • Patent number: 7176081
    Abstract: A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fu Chang, Yen-Hsiu Chen, Hung-Jen Lin, Ming-Chu King, Ching-Hwanq Su, Chih-Mu Huang, Yun Chang