Aluminum Or Aluminum Alloy Conductor Patents (Class 438/688)
  • Patent number: 7163884
    Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: January 16, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Gyung-Su Cho
  • Patent number: 7141500
    Abstract: A method of forming an aluminum containing film on a substrate includes providing a precursor having the chemical structure: Al(NR1R2)(NR3R4)(NR5R6); where each of R1, R2, R3, R4, R5 and R6 is independently selected from the group consisting of hydrogen and an alkyl group including at least two carbon atoms. The precursor is utilized to form a film on the substrate including at least one of aluminum oxide, aluminum nitride and aluminum oxy-nitride. Each of the R1–R6 groups can be the same or different and can by straight or branched chain alkyls. An exemplary precursor that has is useful in forming aluminum containing films is tris diethylamino aluminum.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: November 28, 2006
    Assignee: American Air Liquide, Inc.
    Inventors: Gregory M. Jursich, Ronald S. Inman
  • Patent number: 7135399
    Abstract: An Al3Ti film having a large amount of dissolved Si is deposited on a semiconductor substrate to form a laminate with an Al wiring film, and heat treatment is performed at a temperature of at least 400° C., to thereby absorb excessive Si into the Al3Ti film and so prevent the occurrence of Si nodules. By depositing Al film at a temperature of at least 400° C. at the time of depositing the Al wiring film on the Al3Ti film, excessive Si is caused to be absorbed in the Al3Ti film. Further, at the time of depositing a Ti film on the semiconductor substrate and depositing the Al wiring film, the Al film is deposited at a temperature of a least 400° C., there is reaction between the Ti film within the laminate, causing an Al3Ti film to be produced, and excessive Si is absorbed in the Al3 Ti film produced.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: November 14, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tetsuo Usami, Yoshikazu Arakawa
  • Patent number: 7122458
    Abstract: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Jen Cheng, Hui-Mei Yu, Li-Hsin Tseng, Tzu-Han Lin, Ching-Chiang Wu, Chun-Yen Lo, Li-Chuan Huang, Boe Su
  • Patent number: 7119034
    Abstract: This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed to form a first species monolayer onto the substrate within the deposition chamber from a gaseous first precursor. The chemisorbed first species is contacted with a gaseous second precursor effective to react with the first species to form an oxide of a component of the first species monolayer. The contacting at least in part results from flowing O3 to the deposition chamber, with the O3 being at a temperature of at least 170° C. at a location where it is emitted into the deposition chamber. The chemisorbing and the contacting are successively repeated to form an oxide comprising layer on the substrate. Additional aspects and implementations are contemplated.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Demetrius Sarigiannis, Shuang Meng
  • Patent number: 7115503
    Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are pemitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: October 3, 2006
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 7112528
    Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: September 26, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Ted Guo, Roderick Craig Mosley, Fusen Chen
  • Patent number: 7101779
    Abstract: Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 5, 2006
    Assignee: Micron, Technology, Inc.
    Inventors: Brian A. Vaartstra, Donald L. Westmoreland
  • Patent number: 7094692
    Abstract: A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) forming a catalyst layer on the growth mode control layer, and (c) causing the carbon nanotubes to grow by heating the catalyst layer by thermal CVD so that the carbon nanotubes serve as the interconnection part. The growth mode control layer is formed by sputtering or vacuum deposition in an atmospheric gas, using a metal selected from a group of Ti, Mo, V, Nb, and W. The growth mode is controlled in accordance with a predetermined concentration of oxygen gas of the atmospheric gas.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: August 22, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiro Horibe, Akio Kawabata, Mizuhisa Nihei
  • Patent number: 7094680
    Abstract: A method of forming a tantalum nitride layer for integrated circuit fabrication is disclosed. In one embodiment, the method includes forming a tantalum nitride layer by chemisorbing a tantalum precursor and a nitrogen precursor on a substrate disposed in a process chamber. A nitrogen concentration of the tantalum nitride layer is reduced by exposing the substrate to a plasma annealing process. A metal-containing layer is then deposited on the tantalum nitride layer by a deposition process.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: August 22, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Patent number: 7087520
    Abstract: A semiconductor device includes a semiconductor substrate and metal wiring formed by alternately depositing aluminum layers and copper layers on the semiconductor substrate so that a top layer of the metal wiring is an aluminum layer. The metal wiring is fabricated by alternately depositing an aluminum layer and a copper layer on a semiconductor substrate a predetermined number of times to form a metal wiring layer having an aluminum top layer. A photoresist film pattern is formed on the metal wiring layer and metal wiring is formed by performing an etching process on the metal wiring layer using the photoresist film pattern as a mask.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: August 8, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae-Suk Lee
  • Patent number: 7078339
    Abstract: The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conductive layers, and then the other conductive layers are etched. According to the present invention, since it is possible to prevent attacks against the side walls, which may occur due to sputtering and bending of plasma ions, it is possible to enhance yield and reliability of a semiconductor device.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: July 18, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joon Hyeon Lee
  • Patent number: 7067416
    Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: June 27, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 7052993
    Abstract: A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper alloy line has a thickness t. the concentration y of magnesium in copper alloy line is related to the thickness is as follows: y ? 94 t .
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: May 30, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Jae Gab Lee, Heung Lyul Cho
  • Patent number: 7045460
    Abstract: A packaging substrate is fabricated using two plating steps for respectively plating the gold-plating areas defined on two opposite sides of the substrate. Before plating, the gold-plating areas are defined by a layer of solder mask. By doing this, the plated gold layer will not overlap with the solder mask, thereby preventing peeling or reliability problems.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: May 16, 2006
    Assignee: Nan Ya Printed Circuit Board Corporation
    Inventors: Yi-Tang Weng, Wei-Hsin Lin, Shing-Fun Ho
  • Patent number: 7037766
    Abstract: An active matrix substrate comprises a matrix array of TFTs. A double-layered film includes an under-layer of aluminum-neodymium (Al—Nd) alloy and an over-layer of high melting point metal. The double-layered film forms first interconnection lines for connection to the TFTs. A triple-layered film includes an under-layer of said high melting point metal, a middle-layer of said Al—Nd alloy and an over-layer of the high melting point metal. The triple-layered film forms second interconnection lines for connection to the TFTs.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: May 2, 2006
    Assignee: NEC LCD Technologies, Inc.
    Inventors: Akitoshi Maeda, Hiroaki Tanaka, Shigeru Kimura, Satoshi Kimura
  • Patent number: 7037830
    Abstract: A physical vapor deposition sputtering process for enhancing the <0002> preferred orientation of a titanium layer uses hydrogen before or during the deposition process. Using the oriented titanium layer as a base layer for a titanium, titanium nitride, aluminum interconnect stack results in formation of an aluminum layer with predominant <111> crystallographic orientation which provides enhanced resistance to electromigration. In one process, a mixture of an inert gas, usually argon, and hydrogen is used as the sputtering gas for PVD deposition of titanium in place of pure argon. Alternatively, titanium is deposited in a two-step process in which an initial burst of hydrogen is introduced into the reaction chamber in a separate, first step. Pure argon is used as the sputtering gas for the titanium deposition in a second step. The method is broadly applicable to the deposition of metallization layers.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: May 2, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Michael Rumer, Jack Griswold, Tom Dorsh, Michael Kwok Leung Ng, David E. Reedy, Paul D. Healey, Michal Danek, Reed W. Rosenberg
  • Patent number: 7015152
    Abstract: A method of fabricating aluminum oxide films utilizing aluminum alkoxide precursors is described. The aluminum oxide film is formed by (a) providing an aluminum alkoxide precursor that is dissolved, emulsified or suspended in a liquid; (b) providing a vapor generated from the aluminum alkoxide precursor; and (c) depositing an aluminum oxide film on the substrate at a temperature greater than 500° C.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Alessandro C. Callegari, Deborah Ann Neumayer
  • Patent number: 7008869
    Abstract: A bridge phenomenon between metal wirings is prevented by removing metal by-products created during a metal wiring etching process. A semiconductor substrate is formed with an insulation layer having a conductive plug. A metal layer including first Ti/TiN layer, an Al layer, and a second Ti/TiN layer is formed on an entire surface of the semiconductor substrate. A hard mask layer is formed on the metal layer. A photosensitive film pattern is formed the hard mask layer and the hard mask layer is primarily etched by using the photosensitive film pattern as a mask. The metal layer is etched by using the photosensitive film pattern and the etched hard mask layer as an etching mask.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: March 7, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hee Han
  • Patent number: 6989330
    Abstract: In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film (14) containing fluorine formed on a substrate (11), a titanium aluminum alloy film (17a) formed on the insulating film (14) containing fluorine, and a metallic film (17b) comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film (17a).
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: January 24, 2006
    Assignee: Sony Corporation
    Inventors: Yoshiyuki Enomoto, Ryuichi Kanamura
  • Patent number: 6982217
    Abstract: A structure having projections is provided. The structure having projections comprises a first projection formed on a first layer containing a first material, and a plurality of second projections formed around the first projection and containing a material capable of being subjected to anodic oxidation.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: January 3, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aya Imada, Tohru Den
  • Patent number: 6982218
    Abstract: A method of electrically contacting a semiconductor layer (13) coated with at least one dielectic layer (12) which is coated with a metal layer the metal layer (11) is applied on the dielectric layer (12) and the metal layer (11) is temporarily locally heated in a line, linear or dotted pattern by means of a source of radiation (9) in a controlled manner in such a way that a local molten mixture, is formed consisting exclusively of the metal layer (11), the dielectric layer (12) and the semiconductor layer (13) are located directly underneath the metal layer (11) and upon solidification, leads to an electrical contact between the semiconductor layer (13) and the metal layer (11).
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: January 3, 2006
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Ralf Preu, Eric Schneiderlöchner, Stefan Glunz, Ralf Lüdeman
  • Patent number: 6977217
    Abstract: In one embodiment, a via structure includes a liner, a barrier layer over the liner, and an aluminum layer over the barrier layer. The barrier layer helps minimize reaction between the aluminum layer and the liner, thus helping minimize void formation in the via. The liner and the barrier layer may be deposited in-situ by ionized metal plasma (IMP) physical vapor deposition (PVD). In one embodiment, the liner comprises titanium, while the barrier layer comprises titanium nitride.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: December 20, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mira Ben-Tzur, Gorley L. Lau, Ivan P. Ivanov, Feng Dai, Chan-Lon Yang
  • Patent number: 6969448
    Abstract: A method for fabricating a metallization structure is presented. The method preferably includes ion metal plasma depositing a wetting layer within a cavity defined in a dielectric layer. The wetting layer preferably includes titanium. The method preferably further includes sputter depositing a bulk metal layer within the cavity and upon the wetting layer. Sputter depositing of the bulk metal layer is preferably performed in a single deposition chamber at least until the cavity is substantially filled.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: November 29, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventor: Gorley L. Lau
  • Patent number: 6964922
    Abstract: Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: November 15, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-myeong Lee, Hyeon-deok Lee, In-sun Park, Ju-bum Lee
  • Patent number: 6960526
    Abstract: A method of producing a field emission device includes laying a group III-nitride semiconductor layer over a substrate, placing a photoresist mask over the group III-nitride semiconductor layer, patterning a generally circular grid in the photoresist mask and the group III-nitride semiconductor layer, and forming the group III-nitride semiconductor layer into generally pointed tips using an inductively coupled plasma dry etching process, wherein the group III-nitride semiconductor layer comprises a group III-nitride semiconductor material having a low positive electron affinity or a even a negative electron affinity, wherein the inductively coupled plasma dry etching process selectively creates an anisotropic deep etch in the group III-nitride semiconductor layer, and wherein the inductively coupled plasma dry etching process creates an isotropic etch in the group III-nitride semiconductor layer. Preferably, the photoresist layer is approximately 1.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: November 1, 2005
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6955978
    Abstract: A semiconductor device can comprise a contact material in substantially continuous contact with a contact region. In an embodiment the contact region may comprise an alloy comprising a wide band-gap material and a low melting point contact material. A wide band-gap material may comprise silicon carbide and a low melting point contact material may comprise aluminum. In another embodiment a substantially uniform ohmic contact may be formed between a contact material and a semiconductor material by annealing the contact at a temperature less than the melting point of the contact material. In an embodiment, the contact may be annealed for more than five hours.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: October 18, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Richard L. Woodin, William F. Seng
  • Patent number: 6951804
    Abstract: A method of forming a tantalum-nitride layer (204) for integrated circuit fabrication is disclosed. Alternating or co-reacting pulses of a tantalum containing precursor and a nitrogen containing precursor are provided to a chamber (100) to form layers (305, 307) of tantalum and nitrogen. The nitrogen precursor may be a plasma gas source. The resultant tantalum-nitride layer (204) may be used, for example, as a barrier layer. As barrier layers may be used with metal interconnect structures (206), at least one plasma anneal on the tantalum-nitride layer may be performed to reduce its resistivity and to improve film property.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: October 4, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Patent number: 6951814
    Abstract: Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal layer is removed from the top surface of the insulating pattern adjacent the recess region and from an upper portion of the recess region. An aluminum film is formed on the metal layer at a process temperature less than a reflow temperature of the metal layer to substantially fill the upper portion of the recess region after removing the metal layer. A metal film is formed on the aluminum film at a process temperature less than the reflow temperature of the etched metal layer.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: October 4, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-hee Kim, Gil-heyun Choi, Ju-young Yun, Jung-hun Seo
  • Patent number: 6949475
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: September 27, 2005
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Jae Suk Lee
  • Patent number: 6949464
    Abstract: An improved semiconductor device fabrication method comprises insertion of a semiconductor wafer into a high-pressure heated chamber and deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: September 27, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Trung T. Doan
  • Patent number: 6949417
    Abstract: In manufacturing an active panel of a liquid crystal display, when a pad portion to which outer driving signals are applied is formed, oxide or nitride layer is generated on the surface of the pads. Since these oxide and nitride layers have a high intrinsic resistance, they cause a reliability of the signal transmission in the pad portion to be decreased. The present invention provides a method for enhancing the reliability of the signal transmission in the pad portion by removing contaminants such as oxide layer and nitride layer and reducing the contact resistance of the pad portion. The present inversion also provides a method for maintaining a good adhesion by forming a surface of the pad portion in an uneven shape and by increasing the contact area. The pad is formed from dual metal layer made by depositing sequentially a first metal layer and a second metal layer.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: September 27, 2005
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Byung Chol Ahn
  • Patent number: 6946387
    Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Atsuko Sakata, Tomio Katata, Takamasa Usui, Masahiko Hasunuma, Hideki Shibata, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura
  • Patent number: 6936535
    Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: August 30, 2005
    Assignee: ASM International NV
    Inventors: Ki-Bum Kim, Pekka J. Soininen, Ivo Raaijmakers
  • Patent number: 6933988
    Abstract: An active matrix substrate includes: a plurality of scan lines and signal lines on a transparent insulative substrate which cross each other; a plurality of switching elements formed at predetermined intersections of the scan lines and signal lines, the switching elements being electrically connected to the scan lines and signal lines; a connection electrode electrically connected to a corresponding one of the switching elements; an interlayer insulating film formed over the scan lines, the signal lines, the connection electrode, and the switching elements; a contact hole formed in the interlayer insulating film over the connection electrode; and a pixel electrode at each intersection, the pixel electrode being electrically connected to the connection electrode through the contact hole, wherein each of the scan lines and signal lines includes an opaque electrode layer; and the contact hole is formed such that a portion of the contact hole exists outside the connection electrode.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: August 23, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Ohgami, Shinya Yamakawa
  • Patent number: 6924172
    Abstract: A top-most layer (64) is formed over a bond pad layer (62) and under a passivation layer (68) and a polyimide layer (72). Openings (70 and 74) are formed within the passivation layer (68) and the polyimide layer (72) to expose the top-most layer (64), which protects the bond pad layer (62) during the formation of the openings (70 and 74). In one embodiment, the exposed top-most layer (64) is selectively etched using hydrogen peroxide and an amine, such as ammonium hydroxide. Because the chemistry does not attack the bond pad layer (62), the bond pad layer's thickness is not decreased and thus, reliability of the bond pad is maintained.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: August 2, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas S. Roche, Paule C. Aschieri
  • Patent number: 6908859
    Abstract: A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: June 21, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Taylor R. Efland, William Nehrer
  • Patent number: 6908857
    Abstract: A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm2 or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: June 21, 2005
    Assignee: Denso Corporation
    Inventors: Kazuo Akamatsu, Yoshihiko Isobe, Hiroyuki Yamane
  • Patent number: 6905962
    Abstract: This invention relates to a method of depositing a layer on an exposed surface of an insulating layer of material. The method includes treating the exposed surface with hydrogen or a gaseous source of hydrogen in the presence of a plasma, prior to or during deposition of a metallic layer.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: June 14, 2005
    Assignee: Trikon Technologies Limited
    Inventors: Knut Beekman, Paul Rich, Claire Louise Wiggins
  • Patent number: 6905960
    Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: June 14, 2005
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hong-Mi Park, Jong-Sik Chun, Hyeon-Deok Lee, In-Sun Park, Jong-Myeong Lee, Ju-Cheol Shin
  • Patent number: 6903017
    Abstract: An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in the silicon layer of the IC. The titanium layer of the structure is at least partially alloyed with the aluminum layer, thereby restricting the ability of the titanium to getter the mobile impurities within the various layers of the IC. Despite the alloying of the titanium and aluminum, the metallization structure exhibits the superior contact resistance and electromigration properties associated with titanium.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: June 7, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Ricky D. Snyder, Robert G Long, David W Hula, Mark D. Crook
  • Patent number: 6900131
    Abstract: The present invention provides a method of manufacturing a semiconductor device, which is capable of reducing variations in the rate of occurrence of failures at individual connecting portions in the semiconductor device. According to the semiconductor device manufacturing method, a Cu-containing TiN layer, which serves as a cap layer (130 (310)), is formed using a Cu-containing Ti target. Cu contained in the Cu-containing TiN layer is diffused into an Al—Cu wiring (120 (320)) located in a portion electrically connected to an interlayer wiring (200) by heat treatment.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 31, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 6893957
    Abstract: A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: May 17, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Jigish D. Trivedi, Mike P. Violette
  • Patent number: 6893960
    Abstract: A method for manufacturing a semiconductor device capable of forming a fine interconnection structure without making the resistance at the through hole high is provided. More specifically, a semiconductor device having a first interconnection formed on the surface of a first layer insulating film is provided, and a second interconnection is also provided on the upper part of the first interconnection and is electrically connected to the first interconnection, and wherein the first interconnection is formed so that the width of the lower part is narrower than that of the upper part.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: May 17, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 6888258
    Abstract: A contact and a copper interconnect line as an uppermost interconnect layer are buried in an interlayer insulating film. A pad area including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line. A gold wire is bonded to the pad area.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Takeru Matsuoka, Noriaki Fujiki, Hiroki Takewaka
  • Patent number: 6878465
    Abstract: The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium. The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Peter K. Moon, Zhiyong Ma, Madhav Datta
  • Patent number: 6872653
    Abstract: After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, an initial conductor film made of aluminium is further deposited. Subsequently, the conductor film is made to reflow and run into the grooves. Thereafter, while heating, further conductor films are respectively deposited, thereby causing these conductor films to run into the grooves. The provision of the initial conductor film suppresses or prevents aluminium in the further conductor films and silicon in the semiconductor substrate from reacting with each other during reflowing of the conductor films.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: March 29, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Yuji Fujii
  • Patent number: 6852628
    Abstract: The process is used to electrically insulate adjacent metallic interconnects made from an aluminum-containing alloy, in particular for interconnects which are arranged on a DRAM cell array. A dielectric material is applied to the interconnects and the polymerizable material polymerizes under the action of heat. In a heat-treatment step the dielectric material is polymerized. A step of applying the dielectric material is carried out without a step of applying an interlayer between interconnects and dielectric material. On account of the self-passivation effect of aluminum, a thin Al2O3 film, which protects the interconnect from corrosion, is formed on the interconnects.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventor: Detlef Weber
  • Patent number: 6849541
    Abstract: A method of forming at least one wire on a substrate. The substrate includes at least one conductive region. An insulating layer is disposed on the substrate. At least one recess in the insulating layer exposes the conductive region. A barrier layer is formed on a surface of the insulating layer and the recess first. A continuous and uniform conductive layer is then formed on a surface of the barrier layer. A seed layer is thereafter formed on a surface of the conductive layer. Finally, a metal layer filling up the recess is formed on a surface of the seed layer.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 1, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Chung Hu, Yu-Ru Yang, Chien-Chung Huang, Tzung-Yu Hung
  • Patent number: 6835644
    Abstract: A method for making interconnect structures, particularly in a semiconductor integrated circuit, is described. The method comprises the steps of: forming a conductive layer; forming of an insulating layer above said conductive layer; creating a plurality of holes in said insulating layer and filling the holes with tungsten thereby forming tungsten plugs, such that said tungsten plugs are in electrical contact with the conductive layer. A patterned metallisation layer that overlies said insulating layer (is formed by means of following steps: forming a continuous metallisation layer, forming an organic mask, etching in plasma said continuous metallisation layer, removing the organic mask in a dry way, and immersing the obtained wafer including the layers (3, 4, 5) and the tungsten plugs in a cleaning solution to remove the post-etching residues. Before immersing into said cleaning solution, the wafer is submitted to a plasma treatment containing F, H or a mixture of F and H.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: December 28, 2004
    Assignee: AMI Semiconductor Belgium
    Inventors: Pierre Stefaan Bruneel, Eddy De Backer, Malik Mastgutovich Fatkhoutdinov