Substrate Dicing Patents (Class 438/68)
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Patent number: 8198705Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.Type: GrantFiled: September 16, 2008Date of Patent: June 12, 2012Assignee: Freescale Semiconductor, Inc.Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
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Publication number: 20120142139Abstract: According to an embodiment, a method of manufacturing a solar cell includes depositing a sequence of layers of semiconductor material forming at least one solar cell on a first substrate; temporarily bonding a flexible film to a support second substrate; permanently bonding the sequence of layers of semiconductor material to the flexible film so that the flexible film is interposed between the first and second substrates; thinning the first substrate while bonded to the support substrate to expose the sequence of layers of semiconductor material; and subsequently removing the support substrate from the flexible film.Type: ApplicationFiled: February 13, 2012Publication date: June 7, 2012Applicant: Emcore Solar Power, Inc.Inventor: Tansen Varghese
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Patent number: 8193013Abstract: A method of producing a semiconductor optical sensor element includes the steps of: forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film; patterning the gate electrode layer to form a gate electrode; and processing thermally the gate electrode layer or the gate electrode under an oxidation environment. Further, the gate electrode layer or the gate electrode is thermally processed under the oxidation environment at a temperature between 750° C. and 900° C.Type: GrantFiled: December 8, 2009Date of Patent: June 5, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Yukihiro Kita
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Publication number: 20120132817Abstract: An embodiment of a photomultiplier device is formed by a base substrate of insulating organic material forming a plurality of conductive paths and carrying a plurality of chips of semiconductor material. Each chip integrates a plurality of photon detecting elements, such as Geiger-mode avalanche diodes, and is bonded on a first side of the base substrate. Couplings for photon-counting and image-reconstruction units are formed on a second side of the base substrate. The first side of the base substrate is covered with a transparent encapsulating layer of silicone resin, which, together with the base substrate, bestows stiffness on the photomultiplier device, preventing warpage, and covers and protects the chips.Type: ApplicationFiled: November 23, 2011Publication date: May 31, 2012Applicant: STMicroelectronics S.r.I.Inventors: Mark Andrew SHAW, Federico Giovanni ZIGLIOLI
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Patent number: 8187960Abstract: A method of joining a flexible layer and a support includes forming a first metal layer on one surface of the flexible layer, forming a second metal layer on one surface of the support, cleaning the first metal layer and the second metal layer, and joining the first metal layer to the second metal layer, such that the first metal layer is between the flexible layer and the second metal layer.Type: GrantFiled: September 7, 2011Date of Patent: May 29, 2012Assignee: Samsung Mobile Display Co., Ltd.Inventors: Jae-Seob Lee, Kyu-Sung Lee, Hyo-Jin Kim, Jae-Kyeong Jeong, Jin-Ho Kwack
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Publication number: 20120126355Abstract: An oxide film capable of suppressing reflection of a lens is formed under a low temperature. A method of manufacturing a semiconductor device includes: (a) forming a lower layer oxide film on a lens formed on a substrate using a first processing source containing a first element, a second processing source containing a second element, an oxidizing source and a catalyst, the lower layer oxide film having a refractive index greater than that of air and less than that of the lens; and (b) forming an upper layer oxide film on the lower layer oxide film using the first processing source, the oxidizing source and the catalyst, the upper layer oxide film having a refractive index greater than that of the air and less than that of the lower layer oxide film.Type: ApplicationFiled: November 10, 2011Publication date: May 24, 2012Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Norikazu Mizuno, Tomohide Kato, Takaaki Noda
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Patent number: 8178423Abstract: A laser beam machining method wherein machining areas in which to form machined grooves and machining start point areas in which to form shallow grooves shallower than the machined grooves are alternately set in each of streets formed on a wafer, and the machined grooves and the shallow grooves are continuously formed by scanning an irradiation point of a laser beam along each of the streets.Type: GrantFiled: September 1, 2009Date of Patent: May 15, 2012Assignee: Disco CorporationInventor: Tomohiro Endo
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Patent number: 8168458Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.Type: GrantFiled: December 8, 2008Date of Patent: May 1, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Reza A. Pagaila, Linda Pei Ee Chua
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Publication number: 20120097234Abstract: Techniques for fabricating thin film solar cells, such as CuZnSn(S,Se) (CZTSSe) solar cells are provided. In one aspect, a method of fabricating a solar cell is provided that includes the following steps. A substrate is provided. The substrate is coated with a molybdenum (Mo) layer. A stress-relief layer is deposited on the Mo layer. The stress-relief layer is coated with a diffusion barrier. Absorber layer constituent components are deposited on the diffusion barrier, wherein the constituent components comprise one or more of sulfur (S) and selenium (Se). The constituent components are annealed to form an absorber layer, wherein the stress-relief layer relieves thermal stress imposed on the absorber layer, and wherein the diffusion barrier blocks diffusion of the one or more of S and Se into the Mo layer. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer.Type: ApplicationFiled: October 26, 2010Publication date: April 26, 2012Applicant: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Supratik Guha, Byungha Shin, Kejia Wang
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Publication number: 20120094422Abstract: Provided herein are methods and systems for scribing solar cell structures to create isolated solar cells. According to various embodiments, the methods involve scanning an excimer laser beam along a scribe line of a solar cell structure to ablate electrically active layers of the structure. A photomask having variable transmittance is disposed between the beam source and the solar cell structure. The transmittance is calibrated to produce variable fluence levels such that a stepped scribed profile is obtained. In certain embodiments, a front contact/absorber/back contact stack is removed along a portion of the scribe line, while a front contact/absorber stack is simultaneously removed along a parallel portion, with the back contact layer unremoved. In this manner, the scribe electrically isolates solar cells on either side of the scribe line, while providing a contact point to the back contact layer of one of the solar cells for subsequent cell-cell interconnection.Type: ApplicationFiled: October 14, 2010Publication date: April 19, 2012Applicant: MIASOLEInventor: Osman Ghandour
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Patent number: 8153464Abstract: A method of singulating a semiconductor die from a wafer is provided. The method includes etching or cutting several trenches into the wafer from a front surface of the wafer, such that each trench extends along an entire side of the die; depositing a passivation layer into the trenches to form a passivation plug on at least a bottom of the trenches to protect the dies and immobilize them during singulation; and forming a rigid carrier layer or plate at the first side of the wafer to secure the dies. The wafer is then ground from the back side to expose the bottom of each trench, a metal layer is formed on the back surface of the wafer; dicing tape is added, the carrier layer is removed, and the die is separated from the wafer by laser cutting or by flexing the tape.Type: GrantFiled: October 18, 2006Date of Patent: April 10, 2012Assignee: International Rectifier CorporationInventor: Robert Montgomery
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Patent number: 8148189Abstract: A method is described to create a thin semiconductor lamina adhered to a ceramic body. The method includes defining a cleave plane in a semiconductor donor body, applying a ceramic mixture to a first face of the semiconductor body, the ceramic mixture including ceramic powder and a binder, curing the ceramic mixture to form a ceramic body, and cleaving a lamina from the semiconductor donor body at the cleave plane, the lamina remaining adhered to the ceramic body. Forming the ceramic body this way allows outgassing of volatiles during the curing step. Devices can be formed in the lamina, including photovoltaic devices. The ceramic body and lamina can withstand high processing temperatures. In some embodiments, the ceramic body may be conductive.Type: GrantFiled: June 30, 2010Date of Patent: April 3, 2012Assignee: Twin Creeks Technologies, Inc.Inventors: Aditya Agarwal, Kathy J Jackson
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Patent number: 8143081Abstract: A method for dicing an optoelectronic semiconductor wafer has steps of preparing an optoelectronic semiconductor wafer, laser scribing, diamond saw dicing and forming optoelectronic semiconductor dies. A product for dicing an optoelectronic semiconductor wafer has a substrate and an epitaxial layer. The substrate has a first surface, a second surface and two rough surfaces. The rough surfaces are formed by laser scribing the wafer to define multiple guide grooves on the wafer and diamond saw grooving the wafer along the guide grooves. The epitaxial layer is formed epitaxially on the first surface of the substrate.Type: GrantFiled: February 13, 2007Date of Patent: March 27, 2012Assignee: HUGA Optotech Inc.Inventors: Chih-Ching Cheng, Chiung-Chi Tsai
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Publication number: 20120058591Abstract: A method of fabricating epitaxial structures including applying an etch stop to one side of a substrate and then growing at least one epitaxial layer on a first side of said substrate, flipping the substrate, growing a second etch stop and at least one epitaxial layer on a second side of the substrate, applying a carrier medium to the ultimate epitaxial layer on each side, dividing the substrate into two parts generally along an epitaxial plane to create separate epitaxial structures, removing any residual substrate and removing the etch stop.Type: ApplicationFiled: September 4, 2010Publication date: March 8, 2012Inventor: Brad M. Siskavich
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Patent number: 8129273Abstract: In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in which electrodes of the semiconductor element are electrically connected to the wiring pattern, and in which the face of the substrate which has the semiconductor element is coated with a resin, the through hole has a through hole land with a width of 0.02 mm or more, which is conductive to the wiring portion, in a substrate face, and the wiring portion and the through hole land are exposed.Type: GrantFiled: September 14, 2010Date of Patent: March 6, 2012Assignee: Canon Kabushiki KaishaInventors: Tetsuo Yoshizawa, Shin-ichi Urakawa, Takashi Miyake
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Publication number: 20120050590Abstract: A method of manufacturing an optical sensor includes providing a semiconductor wafer including a plurality of pixel areas, providing a light transmissive substrate including a light transmissive wafer with a plurality of light transmissive members attached thereto, the plurality of light transmissive members being arranged on a first main surface of the light transmissive wafer and each of plurality of light transmissive members emitting ? rays, an amount of the ? rays being smaller than or equal to 0.05 c/cm2·h, fixing the light transmissive substrate onto the semiconductor wafer together by a fixing member, and dividing the semiconductor wafer and the light transmissive substrate that are fixed together into individual pieces.Type: ApplicationFiled: August 16, 2011Publication date: March 1, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Takanori Suzuki, Tadashi Kosaka, Koji Tsuduki, Yasuhiro Matsuki, Shin Hasegawa, Akiya Nakayama
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Publication number: 20120045866Abstract: A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.Type: ApplicationFiled: November 2, 2011Publication date: February 23, 2012Applicant: AstroWatt, Inc.Inventors: Leo Mathew, Dharmesh Jawarani
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Patent number: 8119502Abstract: The invention relates to a method for the manufacture of packaged components. The invention is based here on the problem of facilitating the application of covers with lateral dimensions that are smaller than the lateral dimensions of the functional substrate. For this purpose, a plate-like cover substrate is mounted on a carrier substrate. Then, on the uncovered side of the plate-like cover substrate, trenches are inserted, so that a composite part is obtained with the carrier substrate and individual covering parts that are separated from each other by the trenches, but interconnected by the carrier substrate. The covering parts of the composite part are connected with a functional substrate with a plurality of components. Then, the connection of the covering parts is dissolved with the carrier substrate, and the carrier substrate is removed, so that a composite is obtained with the functional substrate and a plurality of covering parts that cover functional areas.Type: GrantFiled: May 24, 2007Date of Patent: February 21, 2012Assignee: Schott AGInventors: Dietrich Mund, Volker Seidemann, Edgar Pawlowski, Ralf Biertuempfel, Bernd Woelfing, Frank Fleissner, Petra Auchter-Krummel, Ulf Brauneck, Joseph S. Hayden, Ulrich Fotheringham
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Patent number: 8114701Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.Type: GrantFiled: November 20, 2008Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Seong Kwon, Tae-Je Cho, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Hyung-Sun Jang
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Publication number: 20120034728Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.Type: ApplicationFiled: September 6, 2011Publication date: February 9, 2012Applicant: Furukawa Electric Co, Ltd.Inventors: Toshihiro NAKAMURA, Nobuaki ORITA, Hisashi KOAIZAWA, Kenkichi SUZUKI, Hiroshi KURASEKO, Michio KONDO
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Patent number: 8105856Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.Type: GrantFiled: June 28, 2004Date of Patent: January 31, 2012Assignee: Semiconductor Components Industries, LLCInventors: Takashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru Okigawa
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Publication number: 20120012963Abstract: In one embodiment, a method for making an optical micro device package includes: providing a substrate wafer having a plurality of solid state light sensors integrate therein; providing a transparent cover wafer coated with a material that alters the transparency characteristics of the cover wafer; forming a layer of light sensitive, photo definable adhesive material on the substrate wafer; selectively removing part of the layer of adhesive material in a pattern for a plurality of adhesive spacers between the substrate wafer and the cover wafer with each spacer surrounding a corresponding one of the light sensors; bonding the substrate wafer and the cover wafer together at the spacers to form a wafer assembly in which each spacer surrounds and seals a corresponding one of the light sensors within a cavity bounded by a spacer and the two wafers; and singulating individual device packages from the wafer assembly.Type: ApplicationFiled: February 27, 2009Publication date: January 19, 2012Inventors: Zhuqing Zhang, Steve P. Hanson, Chien-Hua Chen
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Patent number: 8097493Abstract: A method of manufacturing semiconductor light emitting elements with improved yield and emission power uses laser lift-off and comprises the steps of forming a semiconductor grown layer formed of a first semiconductor layer, an active layer, and a second semiconductor layer on a first principal surface of a growth substrate; forming a plurality of junction electrodes apart on the second semiconductor layer and forming guide grooves arranged in a lattice to surround each of the junction electrodes in the second semiconductor layer; joining together a support and the semiconductor grown layer via the junction electrodes; projecting a laser to separate the growth substrate; dividing the semiconductor grown layer into respective element regions for the semiconductor light emitting elements; and cutting the support, thereby separating into the semiconductor light emitting elements.Type: GrantFiled: November 2, 2010Date of Patent: January 17, 2012Assignee: Stanley Electric Co., Ltd.Inventors: Noriko Nihei, Tatsuma Saito, Yusuke Yokobayashi
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Publication number: 20120009717Abstract: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Inventors: Kyle K. Kirby, Salman Akram, William M. Hiatt
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Publication number: 20120009718Abstract: An image sensor module may include an image sensor, a variable thickness member and a lens member. The image sensor may include a light receiver configured to receive a light. Further, a driving voltage may be applied to the image sensor. The variable thickness member may be arranged on the image sensor adjacent to the light receiver. Further, the variable thickness member may have a variable thickness along an optical axis of the light in accordance with the driving voltage through the image sensor.Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Applicant: Samsung Electronics Co., Ltd.Inventor: Yung-Cheol KONG
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Publication number: 20120001291Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.Type: ApplicationFiled: June 17, 2011Publication date: January 5, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Kazuo Kokumai
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Publication number: 20120003777Abstract: Provided herein are methods, apparatuses and systems for fabricating photovoltaic cells and modules. In certain embodiments, the methods, apparatuses and systems involve coating ferromagnetic substrates with thin film solar cell materials and using magnetic force to constrain, move or otherwise manipulate partially fabricated cells or modules. According to various embodiments, the methods, apparatuses and systems provide magnetically actuated handling throughout a photovoltaic cell or module fabrication process, from forming photovoltaic cell layers on a substrate to packaging the module for transport and installation. The magnetically manipulated processing provides advantages over conventional photovoltaic module processing operations, including fewer mechanical components, greater control over placement and tolerances, and ease of handling. As a result, the methods, apparatuses and systems provide highly efficient, low maintenance photovoltaic module fabrication processes.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: MIASOLEInventors: Bruce Krein, Darin Birtwhistle, Jeff Thompson, William Sanders, Paul Alexander
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Publication number: 20120003776Abstract: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Applicant: INTELLECTUAL VENTURES II LLCInventor: Sang Hyuk Park
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Publication number: 20120003775Abstract: A method is described to create a thin semiconductor lamina adhered to a ceramic body. The method includes defining a cleave plane in a semiconductor donor body, applying a ceramic mixture to a first face of the semiconductor body, the ceramic mixture including ceramic powder and a binder, curing the ceramic mixture to form a ceramic body, and cleaving a lamina from the semiconductor donor body at the cleave plane, the lamina remaining adhered to the ceramic body. Forming the ceramic body this way allows outgassing of volatiles during the curing step. Devices can be formed in the lamina, including photovoltaic devices. The ceramic body and lamina can withstand high processing temperatures. In some embodiments, the ceramic body may be conductive.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Aditya Agarwal, Kathy J. Jackson
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Publication number: 20110318863Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chiang Tu, Chun-Lang Chen
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Patent number: 8084288Abstract: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.Type: GrantFiled: August 11, 2009Date of Patent: December 27, 2011Assignee: Raytheon CompanyInventors: Robert P. Ginn, Kenneth A. Gerber
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Publication number: 20110303273Abstract: There is disclosed a photovoltaic cell, such as a solar cell, incorporating one or more epitaxially grown layers of SiGe or another germanium material, substantially lattice matched to GaAs. A GaAs substrate used for growing the layers may be removed by a method which includes using a boundary between said GaAs and the germanium material as an etch stop.Type: ApplicationFiled: February 17, 2010Publication date: December 15, 2011Inventor: Robert Cameron Harper
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Publication number: 20110306162Abstract: A photovoltaic device uses a single crystal or polycrystalline semiconductor layer which is separated from a single crystal or polycrystalline semiconductor substrate as a photoelectric conversion layer and has a SOI structure in which the semiconductor layer is bonded to a substrate having an insulating surface or an insulating substrate. A single crystal semiconductor layer which is a separated surface layer part of a single crystal semiconductor substrate and is transferred is used as a photoelectric conversion layer and includes an impurity semiconductor layer to which hydrogen or halogen is added on a light incidence surface or on an opposite surface. The semiconductor layer is fixed to a substrate having an insulating surface or an insulating substrate.Type: ApplicationFiled: August 19, 2011Publication date: December 15, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yasuyuki ARAI
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Publication number: 20110300661Abstract: An improved method for interconnecting thin film solar cells to form solar cell modules is provided, the method comprising using a flat metallic mesh formed from a thin metallic strip to provide a current collection grid over a thin film solar cell. The method is particularly useful for forming interconnections between thin film solar cells deposited on flexible substrates. The rectangular cross sectional shape of the mesh elements provides an increased area of electrical contact to the solar cell compared to the small tangential area provided by elements of circular cross section. Mesh elements can be made higher rather than wider to improve conductivity without proportionally increasing shading loss. Various coatings can be applied to the mesh to improve its performance, provide corrosion resistance, and improve its cosmetic appearance.Type: ApplicationFiled: June 3, 2010Publication date: December 8, 2011Applicant: NuvoSun, Inc.Inventors: David B. Pearce, Bruce D. Hachtmann, Liguang Gong, Thomas M. Valeri, Dennis R. Hollars
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Patent number: 8071428Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.Type: GrantFiled: February 18, 2009Date of Patent: December 6, 2011Assignee: Infineon Technologies AGInventors: Jens Pohl, Markus Brunnbauer, Irmgard Escher-Poeppel, Thorsten Meyer
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Patent number: 8067819Abstract: The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer insulation film. The semiconductor wafer includes a process-monitor electrode pad formed on a dicing area of the scribe line. The process-monitor electrode pad has a width greater than the width of the dicing area. The process-monitor electrode pad includes a contact hole formed in the poly-metal insulation film for connecting the first metal wiring layer to the polysilicon layer.Type: GrantFiled: November 22, 2006Date of Patent: November 29, 2011Assignee: Ricoh Company, Ltd.Inventors: Masaaki Yoshida, Satoshi Kouno
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Patent number: 8067295Abstract: A double-side light receiving solar cell in a planer regular hexagon shape and having first electrodes on both surfaces are divided into four pieces by a line A-A? connecting two opposing apexes and by a line B-B? perpendicular to the line A-A? and connecting center points on two opposing sides. By matching oblique lines of two divided pieces without misalignment and with respective surfaces in an inversed state, the first electrodes on the same side of the two divided pieces align along the same single straight line. Then, the first electrodes that are on the same side are connected with a first inter connecter, thereby constructing a unit having a rectangular outline. Units thus constructed are arranged so that relevant sides match without misalignment. By handling on a unit basis as described above, it is possible to facilitate an arrangement of the cells and an electricity connection work.Type: GrantFiled: September 27, 2006Date of Patent: November 29, 2011Assignee: SANYO Electric Co., LtdInventors: Toshio Yagiura, Shingo Okamoto, Atsushi Nakauchi
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Patent number: 8067258Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS, or biotechnology devices. The method includes application of a protective thin film which typically has a thickness ranging from about 3 ? to about 1,000 ?, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.Type: GrantFiled: June 5, 2006Date of Patent: November 29, 2011Assignee: Applied Microstructures, Inc.Inventors: Jeffrey D. Chinn, Boris Kobrin, Romuald Nowak
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Patent number: 8067256Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel; mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel; and singulating the combination to yield a plurality of microelectronic packages, each of the packages including: an IHS component of the IHS panel, one of the plurality IC dies bonded and thermally coupled to said IHS component and one of the plurality of package substrates, said IHS component and said one of the plurality of IC dies being mounted to said one of the plurality of package substrates to form said each of the packages.Type: GrantFiled: September 28, 2007Date of Patent: November 29, 2011Assignee: Intel CorporationInventors: Sabina J. Houle, James P. Mellody
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Patent number: 8062960Abstract: The present invention provides a method of manufacturing a compound semiconductor device capable of improving yield when a wafer is divided into device regions. The method of manufacturing a compound semiconductor device includes a division step. The division step includes: a first division step of dividing a wafer 30 in a first direction ? to obtain first strip wafers each having at least two rows of device portions 10 arranged in the first direction ?; a second division step of dividing the first strip wafer in a second direction ? to obtain second strip wafers each having a row of the device portions 10 arranged in the second direction ?; and a third division step of dividing the second strip wafer into the device portions 10, thereby forming compound semiconductor devices including the device portions 10.Type: GrantFiled: February 13, 2008Date of Patent: November 22, 2011Assignee: Showa Denko K.K.Inventor: Kazuhiro Kato
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Publication number: 20110273600Abstract: The present invention provides optical imaging apparatus comprising solid state sensing elements and optical components operable to be manufactured and assembled at the wafer level.Type: ApplicationFiled: February 3, 2010Publication date: November 10, 2011Inventors: Moshe Kriman, William Hudson Welch, Giles Humpston, Osher Avsian, Felix Hazanovich, Ekaterina Axelrod
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Patent number: 8048780Abstract: A method of dividing an optical device wafer includes: a laser beam processing step of performing laser beam processing on the face side of an optical device wafer so as to form breakage starting points along streets; a protective plate bonding step of bonding the face side of the optical device wafer to a surface of a highly rigid protective plate with a bonding agent permitting peeling; a back side grinding step of grinding the back side of the optical device wafer so as to form the optical device wafer to a finished thickness of optical devices; a dicing tape adhering step of adhering the back-side surface of the optical device wafer to a dicing tape; a cut groove forming step of cutting the protective plate bonded to the optical device wafer along the streets so as to form cut grooves; and a wafer dividing step of exerting an external force on the optical device wafer through the protective plate, so as to break up the optical device wafer along the breakage starting points formed along the streets, thereType: GrantFiled: July 6, 2009Date of Patent: November 1, 2011Assignee: Disco CorporationInventors: Hitoshi Hoshino, Takashi Yamaguchi
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Patent number: 8048768Abstract: A method of fabricating a joined wafer has an exposure process which comprises a device formed-area exposure process of exposing by a stepper such that parts of the photosensitive adhesive layer formed over a surface of the transparent wafer or the device formed wafer are removed, the parts corresponding to the device formed areas when the transparent wafer and the device formed wafer are stuck together; and a wafer periphery exposure process of exposing such that a portion of the photosensitive adhesive layer over the periphery of the transparent wafer is left.Type: GrantFiled: July 1, 2009Date of Patent: November 1, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Shigeru Yamada
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Publication number: 20110247672Abstract: A method for manufacturing solar cell chips having an active surface area configured to directly convert solar energy into electrical energy. The method including cutting the solar cell chips out of a wafer using a laser such that the solar cell chips include a non-rectangular geometry. The non-rectangular geometry facilitate continuous cutting by the laser and maximizing a number of solar cell chips cut from the wafer.Type: ApplicationFiled: July 16, 2009Publication date: October 13, 2011Applicant: Concentrix Solar GMBHInventors: Sascha Van Riesen, Andreas Gombert
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Patent number: 8034653Abstract: A method and apparatus for breaking a semiconductor substrate along a predetermined area over which a split groove is formed. The breaking apparatus includes a table for placing a portion of the semiconductor substrate inside the predetermined area and a breaking blade being operable to move downward from a position above the semiconductor substrate placed on the table to thereby compress a portion of the semiconductor substrate outside the predetermined area so that the semiconductor substrate is broken along the split groove. The predetermined area of the semiconductor substrate has at least a neighboring pair of sides intersecting at an angle of less than 180 degrees, and the breaking blade has a projection which, when the semiconductor substrate is broken, compresses a portion of the semiconductor substrate outside the one side so that the one side is compressed ahead of the other side.Type: GrantFiled: December 26, 2007Date of Patent: October 11, 2011Assignee: Sanyo Electric Co., Ltd.Inventor: Hiroyuki Kannou
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Publication number: 20110237015Abstract: The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5 microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier junction with the semiconductor core and the other forms an ohmic contact therewith. In other embodiment, the nanophotovoltaic device includes a semiconductor core comprising a p-n junction that is sandwiched between two metallic layers forming ohmic contacts with the core.Type: ApplicationFiled: June 3, 2011Publication date: September 29, 2011Applicant: SPIRE CORPORATIONInventors: Steven J. Wojtczuk, James G. Moe, Roger G. Little
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Patent number: 8022453Abstract: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.Type: GrantFiled: August 4, 2010Date of Patent: September 20, 2011Assignee: Crosstek Capital, LLCInventor: Sang Hyuk Park
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Patent number: 8003426Abstract: A package structure of optical devices has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has at least an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires.Type: GrantFiled: May 25, 2009Date of Patent: August 23, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Kuo-Chung Yee
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Patent number: 7998763Abstract: A method for manufacturing a semiconductor apparatus which does not hamper the miniaturization of products and can simplify the manufacturing process without the optical performance deteriorating is described. Furthermore, a mold assembly for use in molding a semiconductor apparatus can be provided. A substrate can be set within a lower mold, wherein a plurality of optical semiconductor elements are mounted on the substrate at predetermined intervals. Primary transfer molding using the lower mold and a primary upper mold can be carried out to form a plurality of frame bodies so as to surround the respective optical semiconductor elements. While the substrate is set on the lower mold, secondary transfer molding using the lower mold and the secondary upper mold can be carried out to form the light-transmitting portions so as to cover the optical semiconductor elements and the frame bodies on the substrate.Type: GrantFiled: November 17, 2009Date of Patent: August 16, 2011Assignee: Stanley Electric Co., Ltd.Inventors: Kazuyuki Iwasaki, Ryuichi Goto, Shogo Sakuma
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Patent number: 7998781Abstract: A method of manufacturing a semiconductor device includes: forming a first resin layer on a wafer having a light receiving portion; patterning the first resin layer into a predetermined shape and forming a first resin film on the light receiving portion; dividing the wafer into light receiving elements; mounting the light receiving elements on an upper surface of a lead frame; a sealing step of forming a sealing resin layer around the first resin film; and removing the first resin film such that a portion of the light receiving element is exposed to the outside, and in the sealing step, the upper surface of the first resin film is flush with the upper surface of the sealing resin layer, or the upper surface of the first resin film is higher than the upper surface of the sealing resin layer.Type: GrantFiled: August 13, 2009Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Kenji Uchida, Koki Hirasawa