Substrate Dicing Patents (Class 438/68)
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Patent number: 7993977Abstract: A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a substantially rectangular sheet of transparent material and, after forming the standoff structures, singulating the substantially rectangular sheet of transparent material into a plurality of individual transparent members, each of which comprise at least one of the plurality of standoff structures.Type: GrantFiled: July 2, 2007Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventors: Frank Hall, James Voelz
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Patent number: 7993975Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.Type: GrantFiled: December 18, 2008Date of Patent: August 9, 2011Assignee: Elpida Memory, Inc.Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
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Publication number: 20110169118Abstract: The present invention is has an object of providing an optical device miniaturized while maintaining bonding strength between a semiconductor substrate and a light-transmissive plate, reducing possibility of warpage, and maintaining yields and design flexibility, a method of manufacturing the optical device, and an electronic apparatus. The optical device according to the present invention includes a semiconductor substrate having one surface in which a light-receiving element is formed; and a light-transmissive plate provided above the semiconductor substrate so as to cover the light-receiving element. The semiconductor substrate and the light-transmissive plate are partially bonded above a light-receiving unit of the semiconductor substrate. The light-receiving element is formed in the light-receiving unit.Type: ApplicationFiled: January 11, 2011Publication date: July 14, 2011Applicant: PANASONIC CORPORATIONInventor: Hikari SANO
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Publication number: 20110168237Abstract: An integrated thin-film solar battery, comprising: a plurality of strings having a plurality of thin-film photoelectric conversion elements formed on a transparent insulating substrate, the thin-film photoelectric conversion elements being electrically connected in series to each other, wherein the thin-film photoelectric conversion elements have a first transparent electrode layer laminated on the transparent insulating substrate, a photoelectric conversion layer laminated on the first electrode layer and a second electrode layer laminated on the photoelectric conversion layer, the plurality of strings are arranged in parallel on the same transparent insulating substrate in a direction perpendicular to the series-connecting direction across one or more string separating grooves extending to the series-connecting direction, the string separating groove includes a first groove formed by removing the first electrode layer, and a second groove formed by removing the photoelectric conversion layer and the secoType: ApplicationFiled: September 14, 2009Publication date: July 14, 2011Inventors: Tohru Takeda, Yoshiyuki Nasuno
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METHOD FOR MANUFACTURING THIN FILM TYPE SOLAR CELL, AND THIN FILM TYPE SOLAR CELL MADE BY THE METHOD
Publication number: 20110162684Abstract: A method for manufacturing a thin film type solar cell and a thin film type solar cell manufactured by the method is disclosed. The method is comprised of a first process for forming a plurality of unit front electrode patterns at predetermined intervals on a substrate; a second process for forming a semiconductor layer pattern on the substrate, wherein the semiconductor layer pattern is comprised of a separating part to divide the solar cell into unit cells, and a contact part to connect the electrode patterns electrically; and a third process for forming a plurality of unit rear electrode patterns which are respectively connected with the unit front electrode patterns through the contact part, and are separated from one another by the separating part.Type: ApplicationFiled: August 6, 2008Publication date: July 7, 2011Applicant: JUSUNG ENGINEERING CO., LTD.Inventors: Jae Ho Kim, Jin Hong, Chang-Sil Yang -
Publication number: 20110162688Abstract: A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventor: Christopher J. Petti
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Patent number: 7968432Abstract: A laser processing apparatus has one laser light source that simultaneously radiates laser beams with two wavelengths. Depth positions of focusing points for laser beams are gradually changed in a wafer. Three sets of modifying region groups, i.e., six layers of modifying region groups, are successively formed. One set of modifying region groups constitutes two layers and is formed at a time. The modifying region groups are separated, adjoined, or overlapped with each other along an estimated cut line of the wafer in a depth direction from a surface thereof.Type: GrantFiled: November 14, 2006Date of Patent: June 28, 2011Assignee: DENSO CORPORATIONInventors: Muneo Tamura, Tetsuo Fujii
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Patent number: 7964431Abstract: A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls.Type: GrantFiled: March 19, 2009Date of Patent: June 21, 2011Assignee: Twin Creeks Technologies, Inc.Inventors: Christopher J Petti, Mohamed M Hilali
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Patent number: 7964432Abstract: A method for manufacturing a micro-module for capturing images having an imager and at least one lens, includes manufacturing at least one imager on a first plate of a semiconductor material, producing at least one optical zone to form a lens in at least one second plate of a transparent material, and of assembling the first and second plates so that the imager can receive light through the optical zone.Type: GrantFiled: June 18, 2007Date of Patent: June 21, 2011Assignee: STMicroelectronics Rousset SASInventors: Brendan Dunne, Olivier Gagliano, Robert Ronchi, Roberto Mionetto
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Patent number: 7955955Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: May 10, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville
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Publication number: 20110127631Abstract: A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate.Type: ApplicationFiled: November 17, 2010Publication date: June 2, 2011Applicant: SONY CORPORATIONInventor: Hiroyuki Kawashima
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Patent number: 7951648Abstract: A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern, which is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. A curable underfill coating is applied to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The scanned and stored alignment pattern is delivered to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure.Type: GrantFiled: July 1, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Claudius Feger, Nancy LaBianca
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Publication number: 20110124147Abstract: In a method for separating silicon solar cells, a groove is introduced into a silicon wafer containing the silicon solar cells along a separating line in a front side of the silicon wafer adjacent to a p-n junction in the silicon wafer using a first laser beam. The groove has a depth reaching at least to the p-n junction and extends to a lateral edge of the silicon wafer. In a second work step, the silicon wafer is cut along the separating line starting at the lateral edge using a second laser beam directed into the groove. Wherein the melt arising during the cutting is driven out of the cutting kerf arising during the cutting using a cutting gas flowing at least approximately in the direction of the second laser beam.Type: ApplicationFiled: February 4, 2011Publication date: May 26, 2011Applicant: ROFIN-BAASEL LASERTECH GMBH & CO. KGInventor: ROLAND MAYERHOFER
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Patent number: 7947574Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality modified region 71 is formed at a position where the distance between the front face 3 of the substrate 4 and the end part of the quality modified region 71 on the front face side is 5 ?m to 15 ?m. When the quality modified region 71 is formed at such a position, a laminate part 16 (constituted by interlayer insulating films 17a, 17b here) formed on the front face 3 of the substrate 4 is also cut along a line to cut with a high precision together with the substrate 4.Type: GrantFiled: March 26, 2010Date of Patent: May 24, 2011Assignee: Hamamatsu Photonics K.K.Inventors: Takeshi Sakamoto, Kenshi Fukumitsu
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Publication number: 20110114150Abstract: The present invention provides a process for making solar panels. The process of the present invention avoids the use of laser scribing so it is particularly useful in making flexible solar panels. In addition, the present invention provides an alternative scheme for connecting the first electrodes and second electrodes in a solar panel.Type: ApplicationFiled: November 12, 2010Publication date: May 19, 2011Applicant: DU PONT APOLLO LTD.Inventors: Chiou Fu WANG, Huo-Hsien CHIANG
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Patent number: 7943425Abstract: Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with at least a portion of the exposed wafer surface positioned below the center of gravity of the wafer such that prevailing force of gravity may be used to assist in the removal of contaminants from the wafer.Type: GrantFiled: March 11, 2009Date of Patent: May 17, 2011Assignee: Texas Instruments IncorporatedInventors: Patricio Vergara Ancheta, Heintje Sardonas Vilaga, Ella Chan Sarmiento
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Publication number: 20110111548Abstract: A method of manufacturing a solar cell wherein a pre-cleaning step is completed prior to a saw damage removal step and prior to texturization, thereby resulting in the subsequently formed textured surface to have a more homogeneous textural morphology.Type: ApplicationFiled: October 5, 2010Publication date: May 12, 2011Inventors: Ismail Kashkoush, Gim-Syang Chen
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Patent number: 7932121Abstract: A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the edge surface of the transparent member and the sealing member and easing a stress which the transparent member receives from the sealing member or the semiconductor element.Type: GrantFiled: March 29, 2010Date of Patent: April 26, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoyuki Watanabe
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Patent number: 7923297Abstract: Size of a chipping is made small, suppressing blinding of a blade, when performing dicing of a wafer. When cutting a wafer, cutting is performed so that the portion of a V character-shaped shoulder may enter below the front surface of a wafer (depth Z2 from a substrate front surface) using the metal-bond blade which includes the abrasive particle whose fineness number is more than #3000, and whose point is V character form. By processing it in this way, cutting resistance goes up and blinding of a blade can be prevented. Hereby, the size of a chipping can be suppressed small, preventing blinding of a blade.Type: GrantFiled: August 26, 2009Date of Patent: April 12, 2011Assignee: Renesas Electronics CorporationInventor: Naoki Izumi
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Publication number: 20110079801Abstract: A laminate leadless carrier package comprising an optoelectronic chip, a substrate supporting the chip, the substrate comprising a plurality of conductive and dielectric layers; a wire bond coupled to the optoelectronic chip and a wire bond pad positioned on the top surface of the substrate; an encapsulation covering the optoelectronic chip, the wire bond, and at least a portion of the top surface of the substrate, wherein the encapsulation is a molding compound; and wherein the package is arranged to be mounted as a side-looker. A process for manufacturing laminate leadless carrier packages, comprising preparing a substrate; applying epoxy adhesive to a die attach pad; mounting an optoelectronic chip on the die attach pad; wire-bonding the optoelectronic chip; molding a molding compound to form an encapsulation covering the optoelectronic chip, a wire bond, and the top surface of the substrate; and dicing the substrate into individual packages.Type: ApplicationFiled: October 1, 2009Publication date: April 7, 2011Inventors: Xianzhu ZHANG, Arthur BARLOW, Jerry DELEON, Juergen SCHILZ
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Publication number: 20110073983Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.Type: ApplicationFiled: September 16, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
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Publication number: 20110073974Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.Type: ApplicationFiled: September 13, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Eiji Takano, Hideo Numata, Kazumasa Tanida
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Patent number: 7915746Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has another interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.Type: GrantFiled: May 26, 2006Date of Patent: March 29, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Ohsumi
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Publication number: 20110065226Abstract: The present disclosure relates generally to a method to break and assemble solar cells to make solar panel. The present disclosure provides a method to produce solar pieces from solar cell, as well as assemble them together. The present disclosure device is unique when compared with other known devices and solutions because the present disclosure provides a high speed method to break scribed cells into pieces. A method of forming a string of solar cells includes providing a scribe line on a solar cell and placing a first ribbon on the solar cell. The method then includes placing the solar cell on a supporter and then breaking the solar cell into a plurality of solar cell pieces. The method then has the step of placing a second ribbon on the solar cell pieces and soldering the first and second ribbons and the solar cell pieces and then assembling the solar cell pieces into a string of solar cells.Type: ApplicationFiled: September 8, 2010Publication date: March 17, 2011Inventors: Yuhao Luo, Zhi-min Ling
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Publication number: 20110065227Abstract: Embodiments of the present invention generally relate to an automated production line using a common laser scribe module for providing consistent scribe lines in multiple layers during the formation of thin film photovoltaic modules. The common laser scribe module includes a plurality of identical, programmable laser tools configured to emit radiation at a common wavelength. Substrates flowing through the production line are tracked by a system controller, which identifies available laser tools within the common laser scribe module and routes substrates to available tools for scribing features in one or more layers disposed on the substrates. The system controller also sets and controls laser parameters, such as power, pulse frequency, pulse width, and laser pattern, in order to accurately and consistently produce scribed lines in the appropriate material layer of the substrate.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Tzay-Fa Su, David Morishige, David Tanner, Chris Eberspacher
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Patent number: 7901973Abstract: To a transparent substrate (20) on which a plurality of spacers (5) are formed, an infrared cut filter (IRCF) substrate (27) is attached. The IRCF substrate (27) has a coefficient of thermal expansion smaller than the transparent substrate (20) and approximately equal to a wafer (31). Next, the transparent substrate (20) is diced into plural pieces to form a plurality of cover glasses (6). Then heat cure adhesive (32) is coated on each spacer (5) and the spacers (5) are attached on the wafer (31) on which a plurality of light receiving section (3) and pads (10) are previously formed. Finally, the heat cure adhesive (32) is heated to be cured.Type: GrantFiled: December 11, 2006Date of Patent: March 8, 2011Assignee: Fujifilm CorporationInventor: Kiyofumi Yamamoto
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Patent number: 7901967Abstract: A method for dicing a semiconductor substrate includes: forming a reforming layer in the substrate by irradiating a laser beam on the substrate; forming a groove on the substrate along with a cutting line; and applying a force to the substrate in order to cutting the substrate at the reforming layer as a starting point of cutting. The groove has a predetermined depth so that the groove is disposed near the reforming layer, and the force provides a stress at the groove.Type: GrantFiled: November 16, 2006Date of Patent: March 8, 2011Assignee: DENSO CORPORATIONInventors: Atsushi Komura, Muneo Tamura, Kazuhiko Sugiura, Hirotsugu Funato, Yumi Maruyama, Tetsuo Fujii, Kenji Kohno
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Publication number: 20110053308Abstract: On an epitaxy substrate (1), a layer structure (5, 6, 7) provided for light-emitting diodes or other optoelectronic components using thin-film technology is produced and provided with a first connecting layer (2), which comprises one or a plurality of solder materials. A second connecting layer (3) is applied over the whole area on a carrier (10) and permanently connected to the first connecting layer (2) by means of a soldering process.Type: ApplicationFiled: November 21, 2008Publication date: March 3, 2011Applicant: OSRAM Opolo Semiconductoros GmbHInventors: Vincent Grolier, Andreas Ploessl
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Publication number: 20110049588Abstract: An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion element with excellent characteristics. An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion device with excellent characteristic through a simple process. A semiconductor device is provided, which includes a light-transmitting substrate; an insulating layer over the light-transmitting substrate; and a photoelectric conversion element over the insulating layer.Type: ApplicationFiled: August 17, 2010Publication date: March 3, 2011Inventors: Atsuo Isobe, Noriko Harima, Noriko Matsumoto, Akihisa Shimomura, Kosei Noda, Kazuko Yamawaki, Yoshiyuki Kurokawa, Takayuki Ikeda, Takashi Hamada
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Publication number: 20110045625Abstract: A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers.Type: ApplicationFiled: October 29, 2010Publication date: February 24, 2011Applicant: STMICROELECTRONICS ROUSSET SASInventor: Caroline Hernandez
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Publication number: 20110030758Abstract: To manufacture a photovoltaic device through a first step of sequentially stacking a transparent electrode, a photovoltaic layer, and a rear surface electrode to thereby form a structure in which photovoltaic cells are serially connected, a second step of measuring characteristics of the photovoltaic cell; and a third step of removing, according to a result of measurement, the transparent electrode, the photovoltaic layer, and the rear surface electrode along the serial connection direction, to thereby divide the serially connected photovoltaic cells into a plurality of regions.Type: ApplicationFiled: August 5, 2010Publication date: February 10, 2011Applicant: SANYO ELECTRIC CO., LTD.Inventor: Tatsuya KIRIYAMA
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Publication number: 20110023958Abstract: A solar cell and a method of fabricating solar cells. The method includes a step of separating neighbor solar cells formed on a semiconductor wafer by scribing the wafer to form scribe lines on the wafer and applying a force at, or adjacent to, the scribed lines to separate the solar cells. The scribing is effected on a cap layer covering a window layer of solar cells, thereby minimizing damage to the window layer and mitigating propagation of defects into p-n junctions formed in the solar cells.Type: ApplicationFiled: July 21, 2010Publication date: February 3, 2011Applicant: CYRIUM TECHNOLOGIES INCORPORATEDInventors: Denis Paul MASSON, Simon FAFARD, Eric DESFONDS
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Publication number: 20110017263Abstract: A method and device of fabricating a photovoltaic strip. The method includes providing a photovoltaic cell having a front surface and a back surface and forming a first grid pattern on the front surface and second grid pattern on the back surface. The first grid pattern includes a first plurality of strip columns in parallel in a first direction and a plurality of grid lines in parallel in a second direction perpendicularly crossing the first plurality of strip columns. The second grid pattern includes a plurality of blocks separated by a plurality of streets parallel in the second direction and a second plurality of strip columns parallel in the first direction. The method further includes dicing the photovoltaic cell along the plurality of streets into a plurality of photovoltaic strips. Each of the plurality of photovoltaic strips includes at least one of the plurality of grid lines.Type: ApplicationFiled: September 5, 2008Publication date: January 27, 2011Applicant: Solaria CorporationInventors: KEVIN R. GIBSON, NEELSEN CO, ZHI-MIN LING, CHRIS MIHAI, ALELIE FUNCELL, RAMON ROSAL REGLOS
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Patent number: 7875794Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.Type: GrantFiled: November 29, 2001Date of Patent: January 25, 2011Assignee: Transform Solar Pty LtdInventors: Klaus Johannes Weber, Andrew William Blakers
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Patent number: 7871901Abstract: A method of manufacturing semiconductor chips including forming dividing-groove portions in accordance with dividing regions on the second surface of a semiconductor wafer where an insulating film is placed in the dividing regions of the first surface and performing etching of the entire second surface and the surfaces of the dividing-groove portions by performing plasma etching from the second surface. Thereby corner portions on the second surface side are removed, while the insulating film is exposed from the etching bottom portion by removing the dividing-groove portions in the dividing regions. Also, by continuously performing the plasma etching in a state in which the exposed insulating film is surface charged with electric charge due to ions in plasma, corner portions on in contact with the insulating film on the first surface side are removed, and semiconductor chips that have a high transverse rupture strength are provided.Type: GrantFiled: April 17, 2006Date of Patent: January 18, 2011Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Akira Nakagawa
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Publication number: 20110005566Abstract: A photovoltaic cell module and a method of making the same are provided. The photovoltaic cell module includes a first cell including a first transparent conductive substrate, a first photovoltaic conversion layer, and a first electrode layer, at least a second cell electrically connected to the first cell in series; and a second electrode layer electrically connected to the second cell. In the first cell, the first photovoltaic conversion layer is disposed on the first transparent conductive substrate. The first electrode layer is disposed on the first photovoltaic conversion layer and electrically connected to the first transparent conductive substrate. In addition, the present invention also provides the method of making the photovoltaic cell module.Type: ApplicationFiled: July 7, 2009Publication date: January 13, 2011Applicant: CHI-MEI ENERGY CORP.Inventors: Chih-Jeng HUANG, Yu-Hua WU, Liang-Tang WANG, Wei-Teng CHANG
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Patent number: 7867825Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.Type: GrantFiled: August 29, 2007Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-joon Kim, Hyeoung-won Seo
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Publication number: 20100320554Abstract: Disclosed herein is a method of manufacturing a solid state imaging device, including the steps of: forming a light receiving portion in a light receiving area of a semiconductor substrate; forming a pad portion in a pad area of the semiconductor substrate; forming a microlens material layer over the light receiving portion and the pad portion; providing the microlens material layer with a microlens corresponding to the light receiving portion; forming a low-reflection material layer on the microlens material layer; etching the microlens material layer and the low-reflection material layer over the pad portion to form an opening; and imparting hydrophilicity to a surface of the low-reflection material layer and an inside portion of the opening by a normal temperature oxygen radical treatment.Type: ApplicationFiled: June 2, 2010Publication date: December 23, 2010Applicant: SONY CORPORATIONInventors: Yoshinori Toumiya, Ina Hori, Tadayuki Dofuku, Hitomi Kamiya, Atsushi Yamamoto, Taichi Natori
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Patent number: 7851241Abstract: There are provided a scribing step of performing scribing in a state in which a protective material is applied on at least one surface of a brittle material substrate, and a first scribing device that performs this scribing step. Accordingly, it is possible to form a vertical crack that reaches deep inside of the substrate, while effectively removing cullets produced at the time of severing the substrate, thus performing precise severing along a scribe line.Type: GrantFiled: April 1, 2003Date of Patent: December 14, 2010Assignee: Mitsuboshi Diamond Industrial Co., Ltd.Inventors: Kazuya Maekawa, Hiroshi Soyama
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Publication number: 20100304519Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.Type: ApplicationFiled: August 3, 2010Publication date: December 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hans-Juergen Eickelmann, Michael Haag, Harold J. Hovel, Rainer Klaus Krause, Markus Schmidt, Xiaoyan Shao, Steven Erik Steen
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Publication number: 20100297803Abstract: The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier junction with the semiconductor core and the other forms an ohmic contact therewith. In other embodiment, the nanophotovoltaic device includes a semiconductor core comprising a p-n junction that is sandwiched between two metallic layers forming ohmic contacts with the core.Type: ApplicationFiled: August 6, 2010Publication date: November 25, 2010Applicant: SPIRE CORPORATIONInventors: Steven J. Wojtczuk, James G. Moe, Roger G. Little
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Patent number: 7838325Abstract: Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.Type: GrantFiled: February 13, 2009Date of Patent: November 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Hsuan Hsu, Alex Hsu, Ching-Chun Wang
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Patent number: 7838333Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.Type: GrantFiled: November 3, 2009Date of Patent: November 23, 2010Assignee: Industrial Technology Research InstituteInventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin
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Patent number: 7829360Abstract: A method of nanomachining is provided. The method includes plunging a nanometer-scaled tip into a surface of a substrate at a first location in a first direction that is substantially perpendicular to the surface, thereby displacing a first portion of the substrate with the tip. The method also includes withdrawing the tip from the substrate in a second direction that is substantially opposite to the first direction. The method further includes moving at least one of the tip and the substrate laterally relative to each other. In addition, the method also includes plunging the tip into the substrate at a second location in a third direction that is substantially parallel to the first direction, thereby displacing a second portion of the substrate with the tip and withdrawing the tip from the substrate in a fourth direction that is substantially opposite to the third direction.Type: GrantFiled: September 17, 2007Date of Patent: November 9, 2010Assignee: Rave, LLCInventors: Bernabe J. Arruza, Ronald Bozak, Kenneth Gilbert Roessler, Andrew Dinsdale, Tod Evan Robinson, David Brinkley
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Patent number: 7829440Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, a seed metal layer may be used to grow hard metal layers above it for handling. Metal may be plated above these metal layers everywhere except where a block of stop electroplating (EP) material exists. The stop EP material may be obliterated, and a barrier layer may be formed above the entire remaining structure. The substrate may be removed, and the individual dies may have any desired bonding pads and/or patterned circuitry added to the semiconductor surface. The remerged hard metal after laser cutting and heating should be strong enough for handling. Tape may be added to the wafer, and a breaker may be used to break the dies apart. The resulting structure may be flipped over, and the tape may be expanded to separate the individual dies.Type: GrantFiled: August 7, 2007Date of Patent: November 9, 2010Assignee: SemiLEDS Optoelectronics Co. Ltd.Inventors: Jiunn-Yi Chu, Chao-Chen Cheng, Chen-Fu Chu, Trung Tri Doan
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Publication number: 20100275990Abstract: To provide a novel photoelectric conversion device and a manufacturing method thereof. Over a base substrate having a light-transmitting property, a light-transmitting insulating layer and a single crystal semiconductor layer over the insulating layer are formed. A plurality of first impurity semiconductor layers each having one conductivity type is provided in a band shape in a surface layer of the single crystal semiconductor layer or on a surface of the single crystal semiconductor layer, and a plurality of second impurity semiconductor layers each having a conductivity type which is opposite to the one conductivity type is provided in a band shape in such a manner that the first impurity semiconductor layers and the second impurity semiconductor layers are alternately provided and do not overlap with each other.Type: ApplicationFiled: April 27, 2010Publication date: November 4, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Fumito ISAKA, Sho KATO
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Publication number: 20100269899Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.Type: ApplicationFiled: June 23, 2010Publication date: October 28, 2010Applicant: TRANSFORM SOLAR PTY LTD.Inventors: Klaus Johannes Weber, Andrew William Blakers
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Patent number: 7816165Abstract: A method of forming a MEMS device provides a wafer having a base with a conductive portion. The wafer also has an intermediate conductive layer. After it provides the wafer, the method adds a diaphragm layer to the wafer. The method removes at least a portion of the intermediate conductive layer to form a cavity between the diaphragm layer and the base. At least a portion of the diaphragm layer is movable relative to the base. After it forms the cavity, the method seals the cavity.Type: GrantFiled: January 9, 2009Date of Patent: October 19, 2010Assignee: Analog Devices, Inc.Inventors: Timothy J. Brosnihan, Robert E. Sulouff, Jr., John M. Sledziewski
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Publication number: 20100259672Abstract: An image capturing system includes an optical component, a sensor below and connected to the optical component for capturing radiation, and a chip below the sensor for processing and/or storing and/or transmitting information captured by the sensor. The sensor and the Chip are directly connected to each other. The disclosure further relates to a production method for an image capturing system.Type: ApplicationFiled: November 12, 2008Publication date: October 14, 2010Applicant: CONTINENTAL AUTOMOTIVE GMBHInventor: Thorsten Koehler
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Publication number: 20100258159Abstract: A thin film type solar cell and a method for manufacturing the same is disclosed, the thin film type solar cell comprising a substrate; front electrodes arranged at fixed intervals on the substrate by separating parts for dividing the solar cell into a plurality of unit cells, wherein each separating part is interposed between the front electrodes; semiconductor layer patterns arranged at fixed intervals on the front electrodes by the interposed separating parts; rear electrodes arranged at fixed intervals on the semiconductor layer patterns by the interposed separating parts; and auxiliary electrodes to electrically connect the front electrodes with the rear electrodes, in which the front electrode is electrically connected with the rear electrode through the use of auxiliary electrode, so that it is possible to minimize the laser-scribing procedure for dividing the solar cell into the plurality of unit cells, thereby preventing the particles from being generated.Type: ApplicationFiled: October 30, 2008Publication date: October 14, 2010Applicant: JUSUNG ENGINEERING CO., LTD.Inventors: Jin Hong, Jae Ho Kim, Joung Sik Kim