Abstract: The invention relates to a method for marking wafers, in particular wafers for solar cell production: The method comprises the steps of manufacturing a position line (21a, 21b, 21c) on a peripheral surface of a silicon ingot or column, the ingot or column extending in an axial direction and having a longitudinal axis in the axial direction, wherein the position line extends in the axial direction along substantially the whole ingot or column and is inclined with respect to the longitudinal axis. By this position line it is possible to determine the position of a wafer cut from the ingot or column within the ingot or column, respectively. Further, an individual identification pattern (20a, 20b, 20c) of lines on the peripheral surface of the silicon ingot or column is manufactured, the individual identification pattern of lines extending in axial direction over substantially the whole ingot or column and providing an individual coding which allows to identify the silicon ingot or column.

Abstract: A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls.

Abstract: Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method can further involve placing a plurality of singulated dice back side down on the plurality of pieces of die attach film.

Abstract: A photovoltaic assembly comprises a thin semiconductor lamina and a receiver element, where the receiver element serves as a superstrate in the completed device. The photovoltaic assembly includes a photovoltaic cell. The photovoltaic cell is a back-contact cell; photocurrent passes into and out of the back surface of the cell, but does not pass through the light-facing surface. The lamina is typically substantially crystalline and has a thickness less than about 100 microns, in some embodiments 10 microns or less.

Abstract: According to an embodiment, a method of manufacturing a solar cell includes depositing a sequence of layers of semiconductor material forming at least one solar cell on a first substrate; temporarily bonding a flexible film to a support second substrate; permanently bonding the sequence of layers of semiconductor material to the flexible film so that the flexible film is interposed between the first and second substrates; thinning the first substrate while bonded to the support substrate to expose the sequence of layers of semiconductor material; and subsequently removing the support substrate from the flexible film.

Abstract: An imaging optical module is designed to be placed in front of an optical image sensor of a semiconductor component. The module includes at least one element which has a refractive index that varies between its optical axis and its periphery, over at least an annular part and/or over its central part. The element may be a tablet in front of the semiconductor sensor or a lens in front of the semiconductor sensor. The direction of variation in refractive index may be oppositely oriented with respect to the table and lens.

Abstract: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With these methods, an ingot can be grown that is low in carbon and whose crystal growth is controlled to increase the cross-sectional area of seeded material during casting.

Abstract: An interconnect layer is formed on a lower face of a silicon wafer, a support substrate is adhered over a lower face of the interconnect layer, and a thickness reduction of the silicon wafer is performed from an upper face side. Next, a photodiode is formed in an upper face of the silicon wafer, and a microlens is formed at a position corresponding to the photodiode. An adhesive layer is formed on the silicon wafer in a region not covering the microlens, a low refractive index layer having a lower refractive index than the microlens is formed in a region covering the microlens, and a glass substrate is adhered to the silicon wafer by the adhesive layer. The support substrate is removed from the interconnect layer, and a solder ball is bonded to a lower face of the interconnect layer. Thereafter, a CMOS image sensor is manufactured by dicing the silicon wafer.

Abstract: A semiconductor image sensor includes: a semiconductor imaging element including an imaging area, a peripheral circuit area, and an electrode area; cylindrical electrodes provided on electrode terminals so as to be electrically connected with an external device; and a transparent resin layer provided on the upper surface of the semiconductor imaging element. The upper surface of each cylindrical electrode and the upper surface of the transparent resin layer are substantially of the same height.

Abstract: Provided is an imaging device manufacturing method, which has the step of forming a plurality of imaging elements on one surface of a silicon wafer, the step of sealing a light receiving pixel portion for each imaging element by an imaging optical system, the step of cutting the silicon wafer into the individual imaging elements, the step of placing the cut imaging elements on a substrate, the step of connecting the substrate and the imaging elements electrically, the step of molding the substrate, the imaging optical system and the imaging elements integrally by a mold having identification marks with respect to each imaging element, and the step of cutting and separating the molded substrate into each every imaging element.

Abstract: A laser processing method including a first step of forming a first groove and a second step of forming a second groove on the workpiece. In the first step, the laser beam is intermittently applied to the first street except the intersections between the first street and the second street, thereby forming a discontinuous groove as the first groove in such a manner that each intersection is not grooved. In the second step, the laser beam is continuously applied to the second street, thereby forming a continuous groove as the second groove intersecting the first groove in such a manner that each intersection is grooved by the second groove. In the second step, heat generated at a portion immediately before each intersection is passed through the intersection to be dissipated forward, thereby suppressing overheating at this portion.

Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

Abstract: A method for forming a photovoltaic cell is disclosed which comprises the steps of providing a semiconductor donor body having a first surface and a second surface opposite the first surface, cleaving a first portion from the first surface of the semiconductor donor body to form a first lamina of semiconductor material, wherein the first lamina of semiconductor material has a first lamina thickness, and cleaving a second portion from the second surface of the semiconductor donor body to form a second lamina of semiconductor material, wherein the second lamina of semiconductor material has a second lamina thickness.

Abstract: A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area.

Abstract: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.

Abstract: Methods of forming camera modules include forming a chip structure including a molding pattern surrounding a chip and sidewalls of the chip. A lens module is formed, and the lens module is coupled to an upper part of the chip structure.

Abstract: A pixilated scintillator, scintillator array and methods of fabricating the same are provided. The scintillator array comprises a grid having walls, a scintillator crystal packed between the walls, and a reflective coating provided between the walls and the scintillator crystal.

Abstract: A process applied to grinding, dicing, and/or stacking semiconductors is disclosed. One of its features is that after transparent material is stuck on its active surface, a semiconductor is ground from another surface thereof to become thinner, then take advantage of transparency of the transparent material to cut the transparent material and the semiconductor, to obtain at least one smaller semiconductor unit such as die or chip. Another feature is that the transparent material remains sticking to the active surface of the die by an adhesion layer until the die is attached to a carrier or another die, and then the transparent material and the adhesion layer are removed by taking advantage of a function of the adhesion layer: receiving a ray to lose adhesion between it and the active surface. Preferably the ray reaches the adhesion layer via the transparent material stuck on the active surface of the die.

Abstract: A method includes forming a plurality of mirror periods, stacking the mirror periods, and bonding the mirror periods together to form a high reflectance mirror. At least one of the mirror periods is formed by bonding a first semiconductor layer to a first side of a film layer (where the film layer is formed on a second semiconductor layer), forming an opening through the second semiconductor layer to expose the film layer, and cutting through the first semiconductor layer, the film layer, and the second semiconductor layer. The first semiconductor layer could include a high resistivity silicon wafer, the film layer could include an oxide film, and the second semiconductor layer could include a silicon wafer. The high resistivity silicon wafer could be approximately 110 ?m thick, and the silicon wafer could be approximately 125 ?m thick. The opening through the second semiconductor layer could be 1.25 cm to 1.75 cm in width.

Abstract: An optical waveguide includes a layer A and a plurality of cores enclosed in a cladding. During production of the optical waveguide, a layered film including alternate layers of a core layer and a cladding layer is cut so as to form a groove that penetrates through the layered film in a thickness direction and so as to form a plurality of core portions, and the layer A is provided so as to partially fill the groove depthwise and so as to maintain spacing between the plurality of core portions before the core portions is enclosed by the cladding.

Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

Abstract: A semiconductor device manufacturing method can produce semiconductor light emitting/detecting devices that have high connective strength and high luminous energy by increasing contact areas of electrodes thereof and decreasing enclosed areas of electrodes thereof. A wafer is provided with a semiconductor substrate and a semiconductor epitaxial layer. A plurality of substrate concave portions and epitaxial layer concave portions are formed on the semiconductor substrate and the semiconductor epitaxial layer, respectively. Substrate electrodes and epitaxial layer electrodes are formed in the substrate concave portions and the epitaxial layer concave portions. A substrate surface electrode and an epitaxial layer surface electrode can be formed on the semiconductor substrate and the substrate electrodes and the semiconductor epitaxial layer and the epitaxial layer electrodes, respectively.

Abstract: A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.

Abstract: The present invention relates to measuring devices used in measuring physical quantities, such as acceleration, angular acceleration, or angular velocity, and, more precisely, to micromechanical motion sensors. The area, in the wafer plane, of a motion sensor component according to the present invention is smaller than the area of the motion sensor component having been dice cut and turned by 90°. Correspondingly, the height of the motion sensor component according to the present invention, the component having been turned by 90°, is smaller, in the direction of the joint, than the thickness of the wafer stack formed by the joined wafers. The object of the invention is to provide an improved method of manufacturing a micromechanical motion sensor, and to provide a micromechanical motion sensor suitable, in particular, for use in small micromechanical motion sensor solutions.

Abstract: A wafer processing method for dividing a wafer having function elements in area sectioned by dividing lines formed on the front surface in a lattice pattern into individual chips along the dividing lines, comprising a deteriorated layer forming step for forming a deteriorated layer on the side of the back surface of a position at a distance corresponding to the final thickness of the chip from the front surface of the wafer by applying a laser beam capable of passing through the wafer along the dividing lines from the back surface of the wafer; a dividing step for dividing the wafer into individual chips along the dividing lines by applying external force to the wafer in which the deteriorated layer has been formed along the dividing lines; and a back surface grinding step for grinding the back surface of the wafer divided into individual chips to the final thickness of the chip.

Abstract: A method for fabricating an image sensor die includes providing a wafer having a plurality of die, each die having a raised portion adjacent to an image area onto which a glass cover will be adhered; and thereafter dicing the wafer so that the plurality of die are separated into individual die.

Abstract: A method for manufacture of application specific solar cells includes providing and processing custom design information to determine at least a cell size and a cell shape. The method includes providing a transparent substrate having a back surface region, a front surface region, and one or more grid-line regions overlying the front side surface region. The one or more grid regions provide one or more unit cells having the cell size and the cell shape. The method further includes forming a layered structure including photovoltaic materials overlying the front surface region.

Abstract: Disclosed are a method for manufacturing a thin-film type solar cell and a thin-film type solar cell obtained thereby that uses a direct printing method and reduces the frequency of a cutting process.

Abstract: A method of manufacturing a substrate structure includes the steps of: (1) providing a metal substrate having a metal portion; (2) chemically etching a plurality of trenches in the metal substrate; (3) applying a polymer composite material into the trenches to form a substrate having a polymer composite portion abutted to the metal portion; (4) polishing a surface of the substrate to make a height of the polymer composite portion equal to that of the metal portion; (5) forming a covering material on the surface of the substrate; and (6) cutting the substrate via the polymer composite portion for decreasing cutting bur produced on the metal portion. Furthermore, the method is provided for combining the metal substrate and the polymer composite material, thereby to increase cutting precision and strength of the substrate structure.

Abstract: Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected.

Abstract: A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: A transfer film, on which an adhesive is applied, is glued to plural spacers formed on a glass substrate. The glass substrate is laid on a working table, and one end of the transfer film is fixed to a winding roller. A peeling guide is set at a position over the transfer film. The winding roller is driven to wind the transfer film while the working table moves horizontally. While winding the transfer film, the angle between the glass substrate and the transfer film is kept constant. After the transfer film is peeled off, the adhesive is uniformly transferred to each of the spacers.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A method for producing many semiconductor chips, each having a semiconductor circuit disposed on the face thereof and a die bonding film stuck to the back thereof, from a semiconductor wafer in which many rectangular regions are defined on its face by streets arranged in a lattice pattern, and the semiconductor circuit is disposed in each of the rectangular regions.

Abstract: The invention relates to the formation of thin-film crystalline silicon using a zone-melting recrystallization process in which the substrate is a ceramic material. Integrated circuits and solar cells are fabricated in the recrystallized silicon thin film and lifted off the substrate. Following lift-off, these circuits and devices are self-sustained, lightweight and flexible and the released ceramic substrate can be reused making the device fabrication process cost effective.

Abstract: A method of fabricating a joined wafer has an exposure process which comprises a device formed-area exposure process of exposing by a stepper such that parts of the photosensitive adhesive layer formed over a surface of the transparent wafer or the device formed wafer are removed, the parts corresponding to the device formed areas when the transparent wafer and the device formed wafer are stuck together; and a wafer periphery exposure process of exposing such that a portion of the photosensitive adhesive layer over the periphery of the transparent wafer is left.

Abstract: An element is formed on the major surface of a semiconductor wafer, and a groove is formed in the back surface of the semiconductor wafer along a dicing line or chip dividing line by a mechanical or chemical method. A modified layer is formed by irradiating the groove with a laser, and the semiconductor wafer is divided by using the modified layer as a starting point. The back surface of the semiconductor wafer is removed to at least the depth of the groove.

Abstract: A through hole P of this infrared sensor is formed in a position opposed to an adhesive layer AD. The through hole P, the bottom part thereof and an insulating film Pi formed therein is restrained from being deteriorated and damaged, in order to improve the characteristics of the infrared sensor, since the through hole P and the bottom part thereof are supported by the adhesive layer AD even when a pressure difference is generated between the inside and the outside in the space partitioned by the adhesive layer AD.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, the microelectronic imaging devices include an interposer substrate and a plurality of imager units coupled to the interposer substrate. The interposer substrate includes a plurality of openings and a plurality of contact arrays proximate to corresponding openings. The individual imager units include a microelectronic die with an image sensor and a plurality of bond-pads electrically coupled to the image sensor. The image sensors are aligned with corresponding openings on the interposer substrate, and the bond-pads are electrically coupled to corresponding contacts on the interposer substrate.

Abstract: A method for manufacturing a solid-state pickup device module of the present invention includes: a step of processing a transparent substrate so that each of transparent substrates for a chip is held opposite to each of solid-state image pickup devices when the transparent substrate and a substrate having a plurality of solid-state image pickup devices are opposed to each other (step of processing a transparent substrate; S1 to S17); and a modularizing step in which the transparent substrate thus processed and the substrate having a plurality of solid-state image pickup devices are opposed to each other so as to place each of the transparent substrates for a chip opposite to each of the solid-state image pickup devices (modularizing step; S21 to S28). Thus, the present invention can improve manufacturing efficiency by bonding the transparent substrate and the substrate having a plurality of solid-state image pickup devices at a time.

Abstract: A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut structure in the semiconductor substrate. The at least one undercut structure may include at least one substantially vertical shelf, at least one substantially horizontal shelf, and at least one faceted surface. The at least one doped region may be formed by implanting an impurity in the semiconductor substrate, which is, optionally, annealed. The at least one doped region may be removed selective to the undoped portion of the semiconductor substrate by at least one of wet etching or dry etching. An intermediate semiconductor structure that comprises a single crystalline silicon substrate and at least one undercut structure formed in the single crystalline silicon substrate is also disclosed.

Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.

Abstract: Disclosed is a method of manufacturing a photoelectric conversion element including a substrate and a stacked body configured of a plurality of compound semiconductor layers of different compositions sequentially stacked on the substrate, and having at least one pn junction in the stacked body. This method includes the steps of forming the stacked body configured of the plurality of compound semiconductor layers of different compositions sequentially stacked on the substrate; forming a protective film on the stacked body; forming a groove by removing at least a portion of the stacked body by at least one method selected from the group consisting of a mechanical removing method, dry etching and laser scribing; etching a side wall of the groove using an etching solution after forming the protective film and the groove; and cutting a portion corresponding to the groove for separation into a plurality of photoelectric conversion elements.

Abstract: A thin-film solar cell (1) includes a transparent insulation substrate (2), a transparent electrode layer (3), a semiconductor photoelectric conversion layer (4) and a back electrode layer (5) sequentially formed on the transparent insulation substrate (2), and a separation trench (8) separating at least the back electrode layer (5). The transparent electrode layer (3) protrudes in a longitudinal direction of the separation trench (8), extending beyond the semiconductor photoelectric conversion layer (4) and back electrode layer (5). A method of fabricating the thin-film solar cell (1) is provided.

Abstract: A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.