Abstract: A method of generating a library of reference spectra includes storing an optical model for a layer stack having at a plurality of layers, receiving user input identifying a set of one or more refractive index functions and a set of one or more extinction coefficient functions a first layer from the plurality of layers, wherein the set of one or more refractive index functions includes a plurality of different refractive index functions or the set of one or more extinction coefficient functions includes a plurality of different extinction coefficient functions, and for each combination of a refractive index function from the set of refractive index functions and an extinction coefficient function from the set of extinction coefficient functions, calculating a reference spectrum using the optical model based on the refractive index function, the extinction coefficient function and a first thickness of the first layer.

Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).

Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.

Abstract: The present invention relates to a method for forming a trench that can remove residual particles in a trench using a metal mask, a method for forming a metal wire, and a method for manufacturing a thin film transistor array panel. The method for forming a trench includes: forming a first insulating layer on a substrate; forming a first metal layer on the first insulating layer; forming an opening by patterning the first metal layer; forming a trench by dry-etching the first insulating layer using the patterned first metal layer as a mask; and wet-etching the substrate. The dry-etching is performed using a main etching gas and a first auxiliary etching gas, and the first auxiliary etching gas includes argon.

Abstract: A polishing composition for a silicon wafer includes a macromolecular compound, an abrasive, and an aqueous medium. The macromolecular compound includes a constitutional unit (a1) represented by the following general formula (1), a constitutional unit (a2) represented by the following general formula (2), and a constitutional unit (a3) represented by the following general formula (3). The total of the constitutional unit (a3) is 0.001 to 1.5 mol % of all the constitutional units of the macromolecular compound.

Abstract: The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers.

Abstract: A polishing method and a polishing apparatus finish a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that the surface can be flattened with high surface accuracy within a practical processing time. In the presence of water, such as weak acid water, water with air dissolved therein, or electrolytic ion water, the surface of the substrate made of a compound semiconductor containing either one of Ga, Al, and In and a surface of a polishing pad having an electrically conductive member in an area of the surface which is held in contact with the substrate) are relatively moved while being held in contact with each other, thereby polishing the surface of the substrate.

Abstract: Provided are a polishing slurry for metal films and a polishing method which restrain the generation of erosion and seams, and makes the flatness of a surface polished therewith or thereby high. The slurry and the method are a polishing slurry, for metal films, comprising abrasive grains, a methacrylic acid based polymer and water, and a polishing method using the slurry, respectively.

Abstract: The CMP polishing liquid of the present invention contains 1,2,4-triazole, a phosphoric acid, an oxidant, and abrasive particles. The polishing method of the present invention is a substrate polishing method for polishing a substrate with a polishing cloth while supplying a CMP polishing liquid between the substrate and the polishing cloth, in which the substrate is a substrate having a palladium layer, and the CMP polishing liquid is a CMP polishing liquid containing 1,2,4-triazole, a phosphoric acid, an oxidant, and abrasive particles.

Abstract: A slurry composition has an amount of 100% and includes abrasives, an acid-base pH adjustor, an oxidant and water. A content of the abrasives is 10 wt % to 40 wt %, and a polydisperse index of the abrasives sizes is greater than 1.8. A content of the acid-base pH adjustor is 0.01 wt % to 10 wt %. A content of the oxidant is 0.01 wt % to 10 wt %. A remaining portion of the slurry composition is water.

Abstract: A method of forming fin-shaped structures includes the following steps. A plurality of spacers is formed on a substrate. The substrate is etched by using the spacers as hard masks to form a plurality of fin-shaped structures in the substrate. A cutting process is then performed to remove parts of the fin-shaped structures and the spacers formed on the removed parts.

Abstract: An approach for polishing-based hard mask removal during FinFET device formation is provided. In a typical embodiment, an initial device will be provided with a set of fins (e.g., silicon (Si)), a set of fin caps (e.g., silicon nitride (SiN)), and an oxide layer. A post-oxide planarizing and thinning polishing will first be performed (e.g., using a Silica-based slurry) to thin/reduce the oxide layer. A stop-on-nitride polishing will then be performed (e.g., using a Ceria-based slurry) to reduce the oxide layer to a top surface of the fin caps. Still yet, a stop-on-silicon polishing will be performed (e.g., using a Ceria-based slurry) to remove the set of fin caps and to reduce the oxide layer to a top surface to the set of fins.

Abstract: A method for polishing Through-Silicon Via (TSV) wafers is provided. The method comprises a step of subjecting the surface of a TSV wafer to a polishing treatment with a polishing composition containing an organic alkaline compound, an oxidizing agent selected from sodium chlorite and/or potassium bromate, silicon oxide abrasive particles, and a solvent to simultaneously remove Si and conductive materials at their respective removal rates. By using the method of this invention, Si and conductive materials can be simultaneously polished at higher removal rates to significantly save the necessary working-hour costs for polishing TSV wafers. A polishing composition used in the above method is also provided.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.

Abstract: A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.

Abstract: A donor wafer, for example of silicon, has an irregular surface following cleaving of a lamina from the surface, for example by exfoliation following implant of hydrogen and/or helium ions to define a cleave plane. Pinholes in the lamina leave column asperities at the exfoliated surface of the donor wafer, and the beveled edge may leave an edge asperity which fails to exfoliate. To prepare the surface of the donor wafer for reuse, mechanical grinding removes the column and edge asperities, and minimal additional thickness. Following cleaning, growth and removal of an oxide layer at the surface rounds remaining peaks. The smoothed surface is well adapted to bonding to a receiver element and exfoliation of a new lamina. A variety of devices may be fabricated from the lamina, for example a photovoltaic cell.

Abstract: The present invention relates to an etching method of capable of etching a silicon carbide substrate with a higher accuracy. A first etching step in which a silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C, SF6 gas is supplied into a processing chamber and plasma is generated from the SF6 gas, and a bias potential is applied to a platen, thereby isotropically etching the silicon carbide substrate K, and a second etching step in which the silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C., SF6 gas and O2 gas are supplied into the processing chamber and plasma is generated from the SF6 gas and the O2 gas, and a bias potential is applied to the platen on which the silicon carbide substrate K is placed, thereby etching the silicon carbide substrate K while forming a silicon oxide film as passivation film on the silicon carbide substrate K are alternately repeated.

Abstract: Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact.

Abstract: A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

Abstract: Afforded are a polishing agent, and a compound semiconductor manufacturing method and semiconductor device manufacturing method utilizing the agent, whereby the surface quality of compound semiconductor substrates can be favorably maintained, and high polishing rates can be sustained as well. The polishing agent is a polishing agent for Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductors, and includes an alkali metal carbonate, an alkali metal organic salt, a chlorine-based oxidizer, and an alkali metal phosphate, wherein the sum of the concentrations of the alkali metal carbonate and the alkali metal organic salt is between 0.01 mol/L and 0.02 mol/L, inclusive. The compound semiconductor manufacturing method comprises a step of preparing a Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductor, and a step of polishing the face of the compound semiconductor utilizing an aforedescribed polishing agent.

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.

Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low within a wafer non-uniformity values and low residue levels remaining after polishing.

Abstract: There is provided a nitride semiconductor light-emitting element including a transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the transparent conductor. There is also provided a nitride semiconductor light-emitting element including a first transparent conductor, a metal layer, a second transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the metal layer, the second transparent conductor, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the first transparent conductor.

Abstract: A plasma processing method and a plasma processing apparatus in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.

Abstract: A photoelectric conversion apparatus includes: an active matrix-type TFT array substrate on which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, wherein the photoelectric conversion element connects with a drain electrode via a contact hole opened through a first interlayer insulation film provided above the thin film transistor, wherein a data line and a bias line are connected with the source electrode and the photoelectric conversion element via respective contact holes opened through the second interlayer insulation, and wherein at least a part of the photoelectric conversion element is fixed to have a shape different from a normal pixel between pixels adjacent to each other in an extending direction of the gate line, and an electrical connection between the photoelectric conversion element and the data line is cut off in the transistor of the pixel having the different shape.

Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.

Abstract: A method of chemically-mechanically polishing a substrate having a Group III-nitride surface includes providing a chemical-mechanical polishing slurry composition. The slurry composition includes a slurry solution including a liquid carrier and an oxidizer including a transition metal or a per-based compound. The slurry solution includes at least one component that reacts with the Group III-nitride surface to form a softened Group III-nitride surface. The Group III-nitride comprising surface is contacted with the slurry composition by a pad to form the softened Group III-nitride surface. The pad is moved relative to the softened Group III-nitride surface, wherein at least a portion of the softened Group III-nitride surface is removed.

Abstract: The liquid treatment apparatus according to the present invention includes a substrate holder configured to horizontally hold a substrate, and a top plate configured to be rotatable and to cover the substrate held by the substrate holder from above so as to define a treatment space. In the treatment space, a chemical liquid is supplied by a chemical liquid nozzle onto the substrate, and an atmosphere replacement gas is supplied by a replacement nozzle into the treatment space. The replacement nozzle is supported by a replacement nozzle support arm configured to be horizontally moved between an advanced position at which the replacement nozzle support arm is advanced into the treatment space and a retracted position at which the replacement nozzle support arm is retracted outside from the treatment space. The replacement nozzle is configured to discharge, above the substrate, the atmosphere replacement gas upward.

Abstract: A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value <N> of the measured torques N and a fluctuation range Y of the measured torques N.

Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.

Abstract: The present invention relates to a CMP slurry composition comprising an abrasive particle; a dispersant; an ionic polymer additive; and a non-ionic polymer additive including a polyolefin-polyethylene glycol copolymer including at least two polyethylene glycol repeat unit as a backbone and at least a polyethylene glycol repeating unit as a side chain, and a polishing method with using the slurry composition. The CMP slurry composition shows a low polishing rate to a single-crystalline silicon layer or a polysilicon layer and a high polishing rate to a silicon oxide layer, resulting in having an excellent polishing selectivity.

Abstract: A computer implemented method of monitoring a polishing process includes, for each sweep of a plurality of sweeps of an optical sensor across a substrate undergoing polishing, obtaining a plurality of current spectra, each current spectrum of the plurality of current spectra being a spectrum resulting from reflection of white light from the substrate, for each sweep of the plurality of sweeps, determining a difference between each current spectrum and each reference spectrum of a plurality of reference spectra to generate a plurality of differences, for each sweep of the plurality of sweeps, determining a smallest difference of the plurality of differences, thus generating a sequence of smallest difference, and determining a polishing endpoint based on the sequence of smallest differences.

Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.

Abstract: A method for providing waveguide structures for an energy assisted magnetic recording (EAMR) transducer is described. The waveguide structures have a plurality of widths. At least one waveguide layer is provided. Mask structure(s) corresponding to the waveguide structures and having a pattern are provided on the waveguide layer(s). The mask structure(s) include a planarization stop layer, a planarization assist layer on the planarization stop layer, and a hard mask layer on the planarization assist layer. The planarization assist layer has a low density. The pattern of the mask structure(s) is transferred to the waveguide layer(s). Optical material(s) that cover the waveguide layer(s) and a remaining portion of the mask structure(s) are provided. The optical material(s) have a density that is at least twice the low density of the planarization assist layer. The method also includes performing a planarization configured to remove at least a portion of the optical material(s).

Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.

Abstract: The present invention provides chemical-mechanical polishing (CMP) compositions suitable for polishing a substrate comprising a germanium-antimony-tellurium (GST) alloy. The CMP compositions of the present invention are aqueous slurries comprising a particulate abrasive, a water-soluble surface active agent, a complexing agent, and a corrosion inhibitor. The ionic character of the surface active material (e.g., cationic, anionic, or nonionic) is selected based on the zeta potential of the particulate abrasive. A CMP method for polishing a GST alloy-containing substrate utilizing the composition is also disclosed.

Abstract: Disclosed is a CMP slurry for silicon film polishing, comprising abrasive grains, an oxidizing agent, a cationic surfactant, and water. This CMP slurry is suitable for the CMP step of a silicon film of semiconductor devices, since it enables to obtain excellent planarity and excellent performance of controlling the remaining film thickness, while improving the yield and reliability of the semiconductor devices. This CMP slurry also enables to reduce the production cost.

Abstract: Compositions useful for the selective removal of silicon nitride materials relative to poly-silicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon. The removal compositions include fluorosilicic acid, silicic acid, and at least one organic solvent. Typical process temperatures are less than about 100° C. and typical selectivity for nitride versus oxide etch is about 200:1 to about 2000:1. Under typical process conditions, nickel-based silicides as well as titanium and tantalum nitrides are largely unaffected, and polysilicon etch rates are less than about 1 ? min?1.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.

Abstract: An aqueous CMP agent, comprising (A) solid polymer particles interacting and forming strong complexes with the metal of the surfaces to be polished; (B) a dissolved organic non-polymeric compound interacting and forming strong, water-soluble complexes with the metal and causing an increase of the material removal rate MRR and the static etch rate SER with increasing concentration of the compound (B); and (C) a dissolved organic non-polymeric compound interacting and forming slightly soluble or insoluble complexes with the metal, which complexes are capable of being adsorbed by the metal surfaces, and causing a lower increase of the MRR than the compound (B) and a lower increase of the SER than the compound (B) or no increase of the SER with increasing concentration of the compound (C); a CMP process comprising selecting the components (A) to (C) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: A method for separating a layer from a substrate. The method includes providing a plurality of trenches extending from a first main surface of the substrate into the substrate. A heat treatment of the substrate is performed such that edges of the trenches grow together at the first main surface to form a closed layer at the first main surface, wherein lower portions of the trenches form one or more cavities within the substrate. After that the closed layer is separated from the substrate along the one or more cavities.

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.

Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.

Abstract: The invention provides a polishing liquid for polishing a barrier layer of a semiconductor integrated circuit, the polishing liquid comprising: a diquaternary ammonium cation; a corrosion inhibiting agent; and a colloidal silica, wherein the pH of the polishing liquid is in the range of 2.5 to 5.0. According to the invention, a polishing liquid capable of achieving a superior barrier layer polishing rate, as well as suppressing the occurrence of scratching due to the agglomeration of solid abrasive grains can be provided.

Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.

Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.