Abstract: The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.

Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.

Abstract: Semiconductor wafer provided with a strain-relaxed layer of Si1-xGex, are polished in a first step of mechanical machining of the Si1-xGex layer of the semiconductor wafer in a polishing machine using a polishing pad containing fixedly bonded abrasive materials having a particle size of 0.55 ?m or less, and also a second step of a chemomechanical machining of the previously mechanically machined Si1-xGex layer of the semiconductor wafer using a polishing pad and with supply of a polishing agent slurry containing abrasive materials.

Abstract: Exemplary embodiments provide methods for planarizing a semiconductor surface. In embodiments, the disclosed planarizing methods can include a chemical mechanical planarization (CMP) process using a slurry-free solution that includes hydrogen peroxide (H2O2) but is free of particles such as oxide particles. A semiconductor surface (e.g., germanium) can then be planarized to provide a desirable surface roughness. In embodiments, high-quality Group III-V materials can be formed on the planarized semiconductor surface.

Abstract: Provided may be a slurry composition for chemical mechanical polishing (CMP) and a CMP method using the same. For example, the slurry composition may include a first polishing inhibitor including at least one of PO43? or HPO42? and a second polishing inhibitor, which may be a C2-C10 hydrocarbon compound having —SO3H or —OSO3H. By using the slurry composition for CMP and a CMP method using the same, increased selectivity to SiN may be obtained.

Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

Abstract: A polishing liquid for a chemical mechanical polishing of a semiconductor device includes (a) a carboxylic acid compound having one or more carboxy groups, (b) colloidal silica particles having a ? potential of ?10 mV to ?35 mV when used in the polishing liquid, (c) a benzotriazole derivative, (d) an anionic surfactant, and (e) an oxidizing agent, and the polishing liquid has a pH of from 5.0 to 8.0.

Abstract: An electrophoretic display device includes: a transparent substrate positioned at a display side and having a transparent front electrode; a wiring substrate disposed to face the transparent substrate and having a field applying unit; a spacer disposed between the transparent substrate and the wiring substrate and having a plurality of accommodating holes with upper and lower portions open; and a plurality of microcapsules respectively positioned in the plurality of accommodating holes and including a dispersion solvent encapsulated with a plurality of charged particles contained therein, wherein the accommodating holes comprise upper holes with a width for receiving the microcapsules and lower holes allowing the microcapsules to be mounted thereon.

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract: Suspensions of cerium oxide particles in which the particles (secondary particles) have an average size not exceeding 200 nm, such secondary particles being comprised of primary particles having an average size not exceeding 100 nm with a standard deviation having a value not exceeding 30% of the value of this average size, are prepared from a solution of a cerium-III salt, including cerium IV or hydrogen peroxide, which is contacted with a base in the presence of nitrate ions and in an inert atmosphere; the medium thus obtained is subjected to a thermal processing in an inert atmosphere, then acidified and scrubbed and the powder is obtained by drying and calcining of the suspension, which suspension and powder are useful for polishing applications.

Abstract: In a slurry composition and a method of polishing a layer using the slurry composition, the slurry composition includes from about 3 to 20 percent by weight of an abrasive, from about 0.1 to 3 percent by weight of an ionic surfactant, from about 0.01 to 0.1 percent by weight of a nonionic surfactant, from about 0.01 to 1 percent by weight of a polish accelerating agent including an amino acid compound, and a remainder of an aqueous solution including a basic pH-controlling agent and water. The slurry composition including the nonionic surfactant and the polish accelerating agent may be used for speedily polishing a stepped upper portion of a silicon oxide layer, and may also enable a lower portion of the silicon oxide layer to function as a polish stop layer.

Abstract: A method for manufacturing a polishing pad containing substantially spherical cells and having high thickness accuracy includes preparing a cell-dispersed urethane composition by a mechanical foaming method; continuously discharging the cell-dispersed urethane composition from a single discharge port to a substantially central portion in the width direction of a face material A, while feeding the face material A; laminating a face material B on the cell-dispersed urethane composition; then uniformly adjusting the thickness of the cell-dispersed urethane composition by thickness adjusting means; curing the cell-dispersed urethane composition with the thickness adjusted in the preceding step without applying any additional load to the composition so that a polishing sheet including a polyurethane foam is formed; and cutting the polishing sheet.

Abstract: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.

Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.

Abstract: A wafer processing method which includes a protective member attaching step of attaching a protective member to the front side of the wafer, a back grinding step of grinding the back side of the silicon (Si) substrate of the wafer so as not to expose electrodes to the back side of the silicon (Si) substrate, and an etching step of etching the back side of the silicon (Si) substrate by using an etching liquid to thereby expose the electrodes to the back side of the silicon (Si) substrate. The etching liquid includes a first etching liquid having a high etching rate to silicon (Si) and a second etching liquid capable of etching silicon (Si) and having a low etching rate to silicon dioxide (SiO2).

Abstract: A polishing mixture and related method of polishing a material wafer surface, such as silicon carbide, are disclosed. The polishing mixture comprises; an abrasive and an oxidizer mixed in an acidic solution. Alumina may be used as the abrasive and the polishing mixture may have a pH less than or equal to seven (7).

Abstract: The Invention relates to a method for producing a solid support coated by a metal Layer to which an SiOx layer provided with a uniform and stable thickness is applied, wherein said solid support makes it possible to determine the pretense of a compound on the surface thereof by means of Surface Plasmon Resonance (?SPR ?).

Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

Abstract: The invention relates to a chemical-mechanical polishing composition comprising silica, one or more organic carboxylic acids or salts thereof, one or more polysaccharides, one or more bases, optionally one or more surfactants and/or polymers, optionally one or more reducing agents, optionally one or more biocides, and water, wherein the polishing composition has an alkaline pH. The polishing composition exhibits a high removal rate and low particle defects and low haze. The invention further relates to a method of chemically-mechanically polishing a substrate using the polishing composition described herein.

Abstract: A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate.

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

Abstract: An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is breached at the recess bottom feature and a bottom interconnect makes a single-interface contact with a subsequent interconnect through the breach.

Abstract: A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.

Abstract: The invention provides chemical-mechanical polishing (CMP) compositions and methods for polishing a silicon-containing substrate. A method of the invention comprises the steps of contacting a silicon-containing substrate with a polishing pad and an aqueous CMP composition, and causing relative motion between the polishing pad and the substrate while maintaining a portion of the CMP composition in contact with the surface of the substrate to abrade at least a portion of the substrate. The CMP composition comprises a ceria abrasive, a polishing additive bearing a functional group with a pKa of about 4 to about 9, a nonionic surfactant with an hydrophilic portion and a lipophilic portion wherein the hydrophilic portion has a number average molecular weight of about 500 g/mol or higher, and an aqueous carrier, wherein the pH of the composition is 7 or less. The method reduces defects on the wafers, particularly local areas of high removal.

Abstract: A method of passivating a CMP composition by dilution and determining the relationship between the extent of dilution and the static etch rate of copper. Such relationship may be used to control the CMP composition during the CMP polish to minimize the occurrence of dishing or other adverse planarization deficiencies in the polished copper, even in the presence of substantial levels of copper ions in the CMP composition and at the copper/CMP composition interface.

Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.

Abstract: The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing.

Abstract: Methods of manufacturing a honeycomb extrusion die comprise the steps of coating at least a portion of a die body with a layer of conductive material and modifying the die body with an electrical discharge machining technique. The method then further includes the step of chemically removing the layer of conductive material, wherein the residual material from the electrical discharge machining technique is released from the die body.

Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 40 wt % abrasive having an average particle size of 5 to 150 nm; 0.001 to 1 wt % of an adamantyl substance according to formula (II); 0 to 1 wt % diquaternary substance according to formula (I); and, 0 to 1 wt % of a quaternary ammonium compound. Also, provided is a method for chemical mechanical polishing using the chemical mechanical polishing composition.

Abstract: A method for fabricating a capacitor includes forming a first storage node (SN) oxide layer over a substrate, forming a second SN oxide layer over the first SN oxide layer, forming a mask pattern over the second SN oxide layer, dry-etching the first and the second SN oxide layers using the mask pattern as an etch barrier to form a capacitor region, and wet-etching a resultant structure including the capacitor region to enlarge a bottom width of the capacitor region, thereby forming a final capacitor region having the enlarged bottom width, wherein the first SN oxide layer comprises one portion of high impurity concentration and the other portion of low impurity concentration, the one portion corresponding to a region where the final capacitor region is to be formed.

Abstract: A system and method are provided for fabricating a low electric resistance ohmic contact, or interface, between a Carbon Nanotube (CNT) and a desired node on a substrate. In one embodiment, the CNT is a Multiwalled, or Multiwall, Carbon Nanotube (MWCNT), and the interface provides a low electric resistance ohmic contact between all conduction shells, or at least a majority of conduction shells, of the MWCNT and the desired node on the substrate. In one embodiment, a Focused Electron Beam Chemical Vapor Deposition (FEB-CVD) process is used to deposit an interface material near an exposed end of the MWCNT in such a manner that surface diffusion of precursor molecules used in the FEB-CVD process induces lateral spread of the deposited interface material into the exposed end of the MWCNT, thereby providing a contact to all conduction shells, or at least a majority of the conduction shells, of the MWCNT.

Abstract: A surface treatment apparatus of a substrate can clean a substrate surface in the air without employing a vacuum apparatus, and can remove a natural oxide film or an organic material, such as BTA, from the substrate surface without resorting to plasma cleaning. The surface treatment apparatus includes: an inert gas supply section for supplying an inert gas to the whole or part of a substrate surface to form an oxygen-blocking zone; a heating section for keeping the substrate surface at a predetermined temperature; and a cleaning gas supply section for supplying a cleaning gas to the oxygen-blocking zone to clean the substrate surface.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: A method of manufacturing an ink-jet head is disclosed. The method in accordance with an embodiment of the present invention includes: forming a dividing groove such that one surface of a piezoelectric element is divided corresponding to the position of the chamber; filling the dividing groove with a filler; bonding one surface of the piezoelectric element to one surface of the ink-jet head in which the chamber is formed; and polishing the other surface of the piezoelectric element such that the filler is exposed.

Abstract: The present disclosure provides a concentrate for use in chemical mechanical polishing slurries, and a method of diluting that concentrate to a point of use slurry. The concentrate comprises abrasive, complexing agent, and corrosion inhibitor, and the concentrate is diluted with water and oxidizer. These components are present in amounts such that the concentrate can be diluted at very high dilution ratios, without affecting the polishing performance.

Abstract: A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane.

Abstract: Methods and apparatus for automatic gain control. A film on a substrate is polished by a chemical mechanical polisher that includes a polishing pad and an in-situ monitoring system. The polishing pad includes a first portion, and the in-situ monitoring system includes a light source and a light detector. The light source emits light, and light emitted from the light source is directed through the first portion and to a surface of the film being polished. Light reflecting from the surface of the film being polished and passing through the first portion is received at the light detector. An electronic signal is generated based on the light received at the light detector. When the electronic signal is evaluated not to satisfy one or more constraints, a gain for the light detector is adjusted so that the electronic signal would satisfy the one or more constraints.

Abstract: A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars.

Abstract: A method for manufacturing a polishing pad, which may be laminated, with a small number of manufacturing steps, high productivity and no peeling between a polishing layer and a cushion layer includes preparing a cell-dispersed urethane composition by a mechanical foaming method; continuously discharging the cell-dispersed urethane composition onto a face material, while feeding the face material; laminating another face material on the cell-dispersed urethane composition; curing the cell-dispersed urethane composition, while controlling its thickness to be uniform, so that a polishing layer including a polyurethane foam is formed; cutting the polishing layer parallel to the face into two pieces so that two long polishing layers each including the polishing layer and the face material are simultaneously formed; and cutting the long polishing layers to produce the polishing pad.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms an adsorption layer on the cationically charged material in order to increase polishing selectivity of the anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed.

Abstract: A method of manufacturing a semiconductor device by thinning a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N? drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N? drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N?-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N? drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.

Abstract: A polishing method includes: a pre-polishing film thickness measurement step of taking a substrate before polishing out of a cassette and measuring a thickness of a polishing film of the substrate with a film thickness measurement device; the pre-polishing substrate withdrawal step of returning the substrate after the pre-polishing film thickness measurement to the cassette; the polishing step of taking the substrate, which has been returned to the cassette, out of the cassette and polishing the substrate; the cleaning/drying step of cleaning and drying the substrate after polishing; the post-polishing substrate withdrawal step of returning the substrate after cleaning/drying to the cassette; and the post-polishing film thickness measurement step of taking the substrate after cleaning/drying, which has been returned to the cassette, out of the cassette and measuring the thickness of the polishing film of the substrate with the film thickness measurement device.

Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.

Abstract: A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.

Abstract: Processing a wafer using a double side grinder having a pair of grinding wheels. Warp data is obtained by a warp measurement device for measuring warp of a wafer as ground by the double side grinder. The warp data is received and a nanotopography of the wafer is predicted based on the received warp data. A grinding parameter is determined based on the predicted nanotopography of the wafer. Operation of the double side grinder is adjusted based on the determined grinding parameter.

Abstract: Compound-semiconductor-substrate polishing methods, compound semiconductor substrates, compound-semiconductor-epitaxial-substrate manufacturing methods, and compound semiconductor epitaxial substrates whereby oxygen superficially present on the substrates reduced. A compound semiconductor-substrate polishing method includes a preparation step (S10), a first polishing step (S20), and a second polishing step (S30). In the preparation step (S10), a compound semiconductor substrate is prepared. In the first polishing step (S20), the compound semiconductor substrate is polished with a chloric polishing agent. In the second polishing step (S30), subsequent to the first polishing step (S20), a polishing operation utilizing an alkaline aqueous solution containing an inorganic builder and having pH of 8.5 to 13.0 inclusive is performed.

Abstract: A method of fabricating a thickness of silicon material includes providing a silicon ingot material having a surface region and introducing a plurality of particles having an energy of about 1-5 MeV through the surface region to a depth to define a cleave region and a thickness of detachable material between the cleave region and the surface region. Additionally, the method includes processing the silicon ingot material to free the thickness of detachable material at a vicinity of the cleave region and causing formation of a free-standing thickness of material characterized by a carrier lifetime about 10 microseconds and a thickness ranging from about 20 microns to about 150 microns with a thickness variation of less than about five percent. Furthermore, the method includes treating the free-standing thickness of material using a thermal treatment process to recover the carrier lifetime to about 200 microseconds and greater.