Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Pillars oriented orthogonally to the substrate each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines (SSLs) are disposed above the conductive layers, and bit lines are disposed above the SSLs. The pillars are arranged on a regular grid having a unit cell which is a non-rectangular parallelogram. The pillars may be arranged so as to define a number of parallel pillar lines, each having an acute angle ?>0° relative to the bit line conductors, each line of pillars having n>1 pillars intersecting a common one of the SSL. The arrangement permits higher bit line density, a higher data rate due to increased parallelism, and a smaller number of SSLs, thereby reducing disturbance, reducing power consumption and reducing unit cell capacitance.

Abstract: A manufacturing method of a semiconductor device including arranging a compound semiconductor above a stage of a chamber, supplying an etching gas into the chamber, and generating a plasma in the chamber is provided. The compound semiconductor includes a group-III element nitride as a main component. A surface of the compound semiconductor is processed by a dry etching. Light is irradiated into the chamber during the generating of the plasma. A dry etching apparatus including a chamber including a stage, on which a compound semiconductor is mounted, and a light source irradiating light into the chamber is provided. The chamber is supplied with an etching gas. A plasma is generated in the chamber. A surface of the compound semiconductor is an object of a dry etching.

Abstract: A metal-insulator-metal (MIM) capacitor and a method for forming the same are provided. The MIM capacitor includes an insulator on a bottom metal plate, a top metal plate on the insulator, a dielectric layer on the top metal plate and on at least sidewalls of the top metal plate and the insulator, and an anti-reflective coating (ARC) layer over the top metal plate and the bottom metal plate. The dielectric layer preferably extends on an exposed portion of the bottom metal plate not covered by the top metal plate and the insulator.

Abstract: Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.

Abstract: There is provided a silicon-containing composition for forming a pattern reversal film that can be reworked by an organic solvent that is normally used for the removal of resist patterns. A composition for forming a pattern reversal film, characterized by comprising: polysiloxane; an additive; and an organic solvent, wherein the polysiloxane has a structural unit of Formula (1) and a structural unit of Formula (2): (where R1 is a C1-8 alkyl group), and (where R2 is an acryloyloxy group or a methacryloyloxy group; and n is an integer of 2 to 4), and the additive is an organic acid having at least two of a carboxy group and/or a hydroxy group; and a pattern reversal film and a method for forming a reversal pattern by use of the composition.

Abstract: [Problem] To provide a method capable of forming an insulating film having homogeneous and high bulk density and less suffering defects. [Means for solving] A substrate surface is coated with a silicon dioxide dispersion containing silicon dioxide fine particles, a polymer, a surfactant and a dispersion medium; and then further coated with a polysilazane composition; and thereafter heated to form an insulating film.

Abstract: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.

Abstract: The present invention provides a method for manufacturing a semiconductor device which can reduce characteristic deterioration due to impurity incorporation. The present invention also provides a semiconductor device and an electric appliance with reduced characteristic deterioration due to the impurity incorporation. The method for manufacturing a semiconductor device has a process for depositing an organic semiconductor. In addition, a process for introducing and exhausting gas having low reactivity while heating a treater so that temperature in the inside of the treater is higher than sublimation temperature of the organic semiconductor after taking a subject deposited with the organic semiconductor from the treater.

Abstract: A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.

Abstract: The present invention provides methods for manufacturing a passivation layer and a thin film transistor (TFT) array substrate. The method for manufacturing the passivation layer comprises the following steps: placing a substrate in a vacuum process chamber; providing an ammonia gas and a nitrogen gas into the vacuum process chamber; forming plasma and evaporating water vapor; and forming the passivation layer on the substrate. The method for manufacturing the passivation layer can be applicable to the method for manufacturing the TFT array substrate. The present invention can enhance the quality of the passivation layer.

Abstract: A method for processing a substrate includes arranging a substrate including masked portions and unmasked portions in a process chamber; creating plasma in a process chamber; supplying a passivation gas mixture that includes nitrogen or carbon to create a plasma passivation gas mixture; exposing a substrate to the plasma passivation gas mixture to create a passivation layer on the unmasked portions of the substrate; supplying a stripping gas mixture that includes oxygen to the plasma to create a plasma stripping gas mixture; exposing the substrate to the plasma stripping gas mixture to strip at least part of the masked portions and at least part of the unmasked portions; and repeating creating the passivation layer and the stripping to remove a predetermined amount of the masked portions.

Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.

Abstract: A cleaning apparatus includes a first substrate-holding portion configured to hold a first area of a back surface of the substrate so that the top surface is kept face up; a second substrate-holding portion configured to hold a second area of the back surface of the substrate, the second area being not overlapped with the first area, and rotate the substrate; a top-surface cleaning nozzle configured to supply a top surface cleaning fluid to a top surface of the substrate; a bevel cleaning nozzle configured to supply a bevel cleaning fluid to a bevel portion of the substrate; a cleaning fluid supplying portion configured to supply a back surface cleaning fluid to the back surface of the substrate held by the first or the second substrate-holding portion; and a cleaning member configured to clean the back surface of the substrate held by the first or the second-substrate holding portion.

Abstract: Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a substrate, the spreading layer having a monolayer. A stressor layer is formed on the spreading layer, and the stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein the closest monolayer remains on the stressor layer.

Abstract: The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.

Abstract: A thin film forming composition for forming resist underlayer film useable in the production of a semiconductor device, and a resist upper layer film absorbs undesirable UV light with a thin film as an upper layer of the EUV resist before undesirable UV light reaches the EUV resist layer in EUV lithography, an underlayer film (hardmask) for an EUV resist, a reverse material, and an underlayer film for a resist for solvent development. The thin film forming composition useable together with a resist in a lithography process, comprising a mixture of titanium compound (A) selected from: R0aTi(R1)(4-a)??Formula (1) a titanium chelate compound, and a hydrolyzable titanium dimer, and a silicon compound (B): R2a?R3bSi(R4)4-(a?+b)??Formula (2) a hydrolysis product, or a hydrolysis-condensation product of the mixture, wherein the number of moles of Ti atom is 50% to 90% relative to the total moles in terms of Ti atom and Si atoms in the composition.

Abstract: A silicon-on-diamond (SOD) transistor includes a silicon-based substrate, a diamond insulating layer over the silicon-based substrate, a silicon-based insulating layer directly over and in contact with the diamond insulating layer, a body over the silicon-based insulating layer, and a gate over the body. The structure of the SOD transistor provides improved drain induced barrier lowering (DIBL) in fully-depleted SOD transistors by using a second, silicon-based insulating layer.

Abstract: A method includes forming a first pattern having a first opening on a semiconductor substrate. The first opening is then filled. A second pattern of a first and second feature, interposed by the filled opening, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the filled opening, the first feature and the second feature. After forming the spacer elements, the material comprising first and second features is removed to form a second opening and a third opening. The filled opening, the second opening and the third opening are used as a masking element to etch a target layer of the substrate.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: The disclosure provides methods of manufacturing semiconductive structures using stamping and VLS techniques.

Abstract: Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

Abstract: A process for etching includes disposing an activating catalyst on a substrate; providing a vapor composition that includes an etchant oxidizer, an activatable etchant, or a combination thereof; contacting the activating catalyst with the etchant oxidizer; contacting the substrate with the activatable etchant; performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst and the vapor composition; forming an etchant product that includes a plurality of atoms from the substrate; and removing the etchant product from the substrate to etch the substrate.

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract: An etching method is provided that includes the steps of supplying an etching gas containing a fluorocarbon (CF) based gas into a processing chamber, generating a plasma from the etching gas, and etching a silicon oxide film through a polysilicon mask using the plasma. The polysilicon film has a predetermined pattern and is arranged on the silicon oxide film. The silicon oxide film has at least one of a silicon content per unit volume, a fluorine content per unit volume, and a volume density that varies in a depth direction.

Abstract: In one embodiment of the present invention, there is provided a method for etching a multilayer film formed by laminating a plurality of alternating layers of a first layer having a first dielectric constant and a second layer having a second dielectric constant. This method includes (a) a multilayer film etching step, in which an etchant gas is supplied into a processing chamber and a microwave is supplied into the processing chamber to excite a plasma of the etchant gas; and (b) a resist mask reducing step in which an oxygen-containing gas and a fluorocarbon-based gas are supplied to the processing chamber and a microwave is supplied into the processing chamber to excite a plasma of the oxygen-containing gas and the fluorocarbon-based gas. In this method, the steps (a) and (b) are alternately repeated.

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract: The disclosure relates generally to a method for fabricating a patterned medium. The method includes providing a substrate with an exterior layer under a lithographically patterned surface layer, the lithographically patterned surface layer comprising a first pattern in a first region and a second pattern in a second region, applying a first masking material over the first region, transferring the second pattern into the exterior layer in the second region, forming self-assembled block copolymer structures over the lithographically patterned surface layer, the self-assembled block copolymer structures aligning with the first pattern in the first region, applying a second masking material over the second region, transferring the polymer block pattern into the exterior layer in the first region, and etching the substrate according to the second pattern transferred to the exterior layer in the second region and the polymer block pattern transferred to the exterior layer in the first region.

Abstract: The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film of said electronic or photonic material on said substrate; and using a fluoropolymer to protect regions of said electronic or photonic material during a patterning process.

Abstract: Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element and remote plasma are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate.

Abstract: A substrate processing apparatus that can appropriately carry out desired plasma processing on a substrate. The substrate is accommodated in an accommodating chamber. An ion trap partitions the accommodating chamber into a plasma producing chamber and a substrate processing chamber. High-frequency antennas are disposed in the plasma producing chamber. A process gas is introduced into the plasma producing chamber. The substrate is mounted on a mounting stage disposed in the substrate processing chamber, and a bias voltage is applied to the mounting stage. The ion trap has grounded conductors and insulating materials covering surfaces of the conductors.

Abstract: Embodiments involve patterned mask formation. In one embodiment, a method involves depositing a CVD film over a semiconductor wafer; exposing the CVD film to e-beam or UV radiation, forming a pattern in the CVD film; and etching the pattern in the CVD film, forming features in areas not exposed to the e-beam or UV radiation. In one embodiment, a method involves depositing a CVD film over a semiconductor wafer; depositing a thin photo-sensitive CVD hardmask film over the CVD film; exposing the thin photo-sensitive CVD hardmask film to e-beam or UV radiation, forming a pattern in the thin photo-sensitive CVD hardmask film; etching the pattern in the thin photo-sensitive CVD hardmask film; etching the pattern into the CVD film through the patterned thin photo-sensitive CVD hardmask film; and removing the patterned thin photo-sensitive CVD hardmask film.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask.

Abstract: A method of forming a contact hole pattern, including: a block copolymer layer forming step in which a layer containing a block copolymer having a plurality of blocks bonded is formed on a substrate having on a surface thereof a thin film with a hole pattern formed, so as to cover the thin film; a phase separation step in which the layer containing the block copolymer is subjected to phase separation; a selective removing step in which phase of at least one block of the plurality of blocks constituting the block copolymer is removed, wherein hole diameter of the hole pattern formed on the thin film is 0.8 to 3.1 times period of the block copolymer, and in the layer forming step, thickness between upper face of the thin film and surface of the layer containing the block copolymer is 70% or less of thickness of the thin film.

Abstract: An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear structures, with mandrel pitch distances that are twice the desired linear structures' pitch distances. Mandrels for a first plurality of linear structures are shortened. A layer of spacer material is conformally formed over the mandrels and anisotropically etched back to form spacers on lateral surfaces of the mandrels. Spacers on the shortened mandrels are narrower than spacers on the unshortened mandrels as a result of the anisotropic etchback. The mandrels are removed, leaving the spacers in place to form a spacer-based etch mask for the linear structures. The layer of material for the linear structures is etched using the spacer-based etch mask to form the linear structures. The linear structures from the shortened mandrels have lower widths than the linear structures from the unshortened mandrels.

Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.

Abstract: There is provided a method of fabricating a semiconductor device, the method including: forming a semiconductor component portion at a first surface of a substrate; applying a grinding treatment to a second surface of the substrate that is opposite from the first surface to form a fracture surface; applying a fracture surface removal treatment to predetermined positions of the fracture surface of the second surface; and forming an electrode at the second surface.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.

Abstract: Techniques disclosed herein include methods for etching deep silicon features using a continuous gas pulsing process that etches high aspect ratio features having a relatively smooth profile. Such methods provide an etch rate faster than time-multiplexed etch-deposition processes. Techniques include using a continuous process that comprises a cyclic gas-pulsing process of alternating chemistries. One process gas mixture includes a halogen-containing silicon gas and oxygen that creates an oxide layer. A second process gas mixture includes a halogen-containing gas and a fluorocarbon gas that etches oxide and silicon.

Abstract: A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire photodetectors include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.

Abstract: A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.

Abstract: A method for trimming a carbon-containing film includes: (i) providing a substrate having a carbon-containing film formed thereon; (ii) supplying a trimming gas and a rare gas to the reaction space, which trimming gas includes an oxygen-containing gas; and (iii) applying RF power between the electrodes to generate a plasma using the trimming gas and the rare gas and to thereby trim the carbon-containing film while controlling a trimming rate at 55 nm/min or less as a function of at least one parameter selected from the group consisting of a flow rate of an oxygen-containing gas, a flow rate of nitrogen-containing gas to be added to the oxygen-containing gas, pressure in the reaction space, RF power, a duty cycle of RF power, a distance between the electrodes, and a temperature of a susceptor on which the substrate is placed.

Abstract: A method of producing a semiconductor device includes forming an insulating film on a substrate on which a semiconductor layer is formed; removing a part of the insulating film by etching to form an opening in the insulating film; supplying steam with a temperature greater than or equal to 200° C. and less than or equal to 600° C. to the opening formed in the insulating film; after supplying the steam, applying a solution including a silicon compound to a side surface or the insulating film defining the opening; and forming a hydrophobic film on the side surface of the insulating film defining the opening by polymerizing the silicon compound.

Abstract: In an imprint method of an embodiment, in the imprinting of an imprint shot including an outermost peripheral region of a substrate where resist is not desired to be entered at the time of imprinting, light curing the resist is applied to a light irradiation region with a predetermined width including a boundary between the outermost peripheral region and a pattern formation region more inside than the outermost peripheral region, whereby the resist which is to enter inside the outermost peripheral region is cured. Then, light curing the resist filled in a template pattern is applied onto a template.

Abstract: Damascene processes using physical vapor deposition (PVD) sputter carbon film as a chemical mechanical planarization (CMP) stop layer for forming a magnetic recording head are provided. In one embodiment, one such process includes providing an insulator, removing a portion of the insulator to form a trench within the insulator, depositing a carbon material on first portions of the insulator using a physical vapor deposition process, disposing at least one ferromagnetic material on second portions of the insulator to form a pole including a portion of the ferromagnetic material within the trench, and performing a chemical mechanical planarization on the at least one ferromagnetic material using at least a portion of the carbon material as a stop for the chemical mechanical planarization.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side. The semiconductor device structure also includes devices formed on the front side of the substrate and interconnect structures formed on the devices. The semiconductor device structure further includes a protection layer formed on the back side of the substrate, and the protection layer has a thickness over about 10 A.

Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom. The anti-reflective layers are removed using a fluid.

Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.