Coating Of Sidewall Patents (Class 438/696)
  • Patent number: 10720526
    Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting Ko, Han-Chi Lin, Chunyao Wang, Ching Yu Huang, Tze-Liang Lee, Yung-Chih Wang
  • Patent number: 10672612
    Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Gang-Yi Lin, Feng-Yi Chang, Ying-Chih Lin, Fu-Che Lee
  • Patent number: 10636657
    Abstract: A semiconductor pitch patterning can include a method comprising forming a first set of spacers on a surface of a substrate. The method can include directionally depositing a mask material on the first set of spacers and on the surface of the substrate. The method can include selectively depositing a second set of spacers on side surfaces of the first set of spacers and a portion of the mask material in contact with the surface of the substrate. The method can include removing portions of the mask material from the surface of the substrate.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 10559465
    Abstract: In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 11, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Yi Yang, Yihong Chen, Karthik Janakiraman, Abhijit Basu Mallick
  • Patent number: 10535646
    Abstract: Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10535520
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Ru-Gun Liu, Min Cao
  • Patent number: 10505018
    Abstract: A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10483119
    Abstract: The present disclosure relates to integrated circuit device manufacturing processes. A self-aligned double patterning method is provided. In the method, a lithography process for line cut that determines the locations of line termini is performed after forming a spacer layer alongside the mandrel and prior to stripping the mandrel. The lithographic mask for the line cut is aligned to the mandrel and the spacer layer using a mark made of the mandrel material and the spacer material. Compared to the previous approach where the line cut process is performed after the mandrel removal, in the disclosed approach, the line termini mask is made of the mandrel material and the spacer material, and is more distinguishable compared to a mark made of just the spacer material. Thereby, the methods provide robust photo alignment signal for the line cut photolithography and precise positioning of the line termini mask.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Yu Pan, Kuo-Chyuan Tzeng, Lee-Chuan Tseng, Ying-Hua Chen
  • Patent number: 10446406
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • Patent number: 10395985
    Abstract: A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10381233
    Abstract: A substrate processing method according to exemplary embodiments includes bringing removal solution obtained by mixing a nitric acid, a strong acid stronger than the nitric acid, and water into contact with a substrate in which a boron monofilm is formed on a film including a silicon-based film so as to remove the boron monofilm from the substrate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 13, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Kagawa, Syuhei Yonezawa, Kazuya Dobashi, Toshihide Takashima, Masaru Amai
  • Patent number: 10381217
    Abstract: In a method of deposition a thin film, a substrate having a pattern may be provided. A surface of the substrate may be treated using a deposition-suppressing gas to form a deposition-suppressing layer on the pattern. A process gas may be applied to the pattern to deposit the thin film. The deposition-suppressing gas may include fluorine.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 13, 2019
    Assignee: WONIK IPS CO., LTD.
    Inventors: Byung Chul Cho, Sang Jin Lee, In Hwan Yi, Kwang Seon Jin
  • Patent number: 10366917
    Abstract: Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xuelian Zhu, Jia Zeng, Chenchen Wang, Jongwook Kye
  • Patent number: 10319640
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10283362
    Abstract: A method of forming fine line patterns of semiconductor devices includes: forming a plurality of lower linear core structures on at least one lower hard mask layer disposed on a target layer; forming a spacer layer on the hard mask layer to cover the lower linear core structures; forming an upper hard mask layer on the spacer layer; thinning the upper hard mask layer to expose potions of the spacer layer; and removing the exposed portions of the spacer layer to form a plurality of line patterns on the lower hard mask layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: May 7, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10269578
    Abstract: An etching method of etching a processing target object is provided. The processing target object has a supporting base body and a processing target layer. The processing target layer is provided on a main surface of the supporting base body and includes protrusion regions. Each protrusion region is extended upwards from the main surface, and an end surface of each protrusion region is exposed when viewed from above the main surface. The etching method includes a first process of forming a film on the end surface of each protrusion region; a second process of selectively exposing one or more end surfaces by anisotropically etching the film formed through the first process; and a third process of anisotropically etching the one or more end surfaces exposed through the second process atomic layer by atomic layer. The processing target layer contains silicon nitride, and the film contains silicon oxide.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 23, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sho Kumakura, Masahiro Tabata
  • Patent number: 10256146
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 10163653
    Abstract: A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: December 25, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Keiji Kitagaito, Fumiya Kobayashi, Maju Tomura
  • Patent number: 10163885
    Abstract: Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10083864
    Abstract: A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10056258
    Abstract: A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Jhi Huang, Yu-Yu Chen
  • Patent number: 10037920
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Jian-An Ke
  • Patent number: 9991118
    Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 5, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Thomas Jongwan Kwon, Rui Cheng, Abhijit Basu Mallick, Er-Xuan Ping, Jaesoo Ahn
  • Patent number: 9911604
    Abstract: Disclosed are methods of using a lithography-lithography-etch (LLE) technique to form a sidewall spacer pattern for patterning a target layer. In the methods, a photoresist layer is patterned by performing multiple lithographic processes with different photomasks, including a first photomask with a first pattern of parallel bars separated by spaces and a second photomask with a second pattern of opening(s) oriented in an essentially perpendicular direction as compared to the bar(s). The photoresist layer is then developed, creating a third pattern. The third pattern is transferred into a mandrel layer below to form mandrels of different lengths. Then, sidewall spacers are formed on the mandrels and the mandrels are selectively removed to form the sidewall spacer pattern. This sidewall spacer pattern is subsequently used in a sidewall image transfer (SIT) process to pattern a target layer below.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Sun, Xunyuan Zhang, Ruilong Xie, Yulu Chen
  • Patent number: 9892977
    Abstract: A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsing Electronics Co., Ltd.
    Inventors: Sang Woo Pae, Hyun Chul Sagong, Jin Ju Kim, June Kyun Park
  • Patent number: 9882024
    Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 30, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Zuoguang Liu, Ruilong Xie, Tenko Yamashita
  • Patent number: 9812333
    Abstract: Provided is a nanoscale patterning method using self-assembly, wherein nanoscale patterns having desirable shapes such as a lamella shape, a cylinder shape, and the like, may be formed by using a self-assembly property of a block copolymer, and low segment interaction caused in a structure of 10 nm or less which is a disadvantage of the block copolymer may be prevented. In addition, even though single photolithography is used, pattern density may double as that of the existing nano patterns, and pitch and cycle of the patterns may be controlled to thereby be largely utilized for electronic apparatuses requiring high integration of circuits such as a semiconductor device, and the like.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: November 7, 2017
    Assignees: Korea Advanced Institute of Science and Technology, Institute for Basic Science
    Inventors: Sang Ouk Kim, Hyoung-Seok Moon
  • Patent number: 9780000
    Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate; depositing a layer comprising carbon, said layer being disposed distant from said transistor; modifying the protective layer to form a modified protective layer; forming a protective film on the layer comprising carbon; removing the protective film on surfaces of the protective film that are perpendicular to a main implantation direction; selectively removing the layer comprising carbon; and at least one step of selectively removing the modified protective layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Maxime Garcia-Barros
  • Patent number: 9741626
    Abstract: A method of forming a vertical transistor includes forming at least one fin on stacked layers. The stacked layers include a substrate, a doped silicon layer, and an intrinsic layer interposed between the pair of fins and the substrate. The method further includes forming a spacer hardmask over the pair of fins, and forming a bottom spacer. Forming the bottom spacer includes selective oxidation of the SiGe layer.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 9735140
    Abstract: The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9698157
    Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kono, Takaki Hashimoto, Yuji Setta, Toshiya Kotani, Chikaaki Kodama
  • Patent number: 9684236
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ken-Hsien Hsieh, Kuan-Hsin Lo, Shih-Ming Chang, Wei-Liang Lin, Joy Cheng, Chun-Kuang Chen, Ching-Yu Chang, Kuei-Shun Chen, Ru-Gun Liu, Tsai-Sheng Gau, Chin-Hsiang Lin
  • Patent number: 9659949
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Patent number: 9659816
    Abstract: A pattern forming method in an embodiment includes forming, on or above a substrate, a block copolymer layer containing a first polymer and a second polymer having lower surface energy than the first polymer, heat treating the block copolymer layer to separate the block copolymer layer into a first phase containing the first polymer and a second phase containing the second polymer, and using an atomic layer deposition process, selectively forming a metal layer on the first phase and selectively removing the second phase.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Hieno, Koji Asakawa
  • Patent number: 9634063
    Abstract: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: April 25, 2017
    Assignee: MICRON TECHNOLOGY, INC
    Inventors: Fabio Pellizzer, Antonino Rigano, Marcello Mariani, Augusto Benvenuti
  • Patent number: 9607811
    Abstract: Disclosed is a method of processing a workpiece including a mask. The processing method includes: a first process of generating plasma of a first gas containing a silicon halide gas in a processing container of a plasma processing apparatus that accommodates a workpiece having a mask, to form a reactive precursor; a second process of purging a space in the processing container; a third process of generating plasma of a second gas containing oxygen gas in the processing container to form a silicon oxide film; and a fourth process of purging the space in the processing container. In the processing method, a sequence including the first to fourth processes is repeated.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 28, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masanobu Honda
  • Patent number: 9598771
    Abstract: The present disclosure provides for methods of depositing a dielectric layer within a reaction chamber including a first electrode configured to support a substrate and a second electrode disposed above the first electrode and the substrate. A method includes flowing at least one reactant gas and at least one dilution gas into the reaction chamber, applying a first maximum low frequency radio frequency (LFRF) reflective power between the first and second electrodes to deposit a dielectric layer on the substrate, and applying a second maximum LFRF reflective power between the first and second electrodes during a termination operation, wherein the second maximum LFRF reflective power is less than the first maximum LFRF reflective power.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ji-Feng Liu
  • Patent number: 9564324
    Abstract: The inventive concepts provide methods of forming a pattern. In the method, a block copolymer layer may be formed on a neutral layer having an uneven structure and then phase separation is induced. The neutral layer may have an affinity for all of a hydrophilic polymer and a hydrophobic polymer, so that vertical cultivation of phases of the block copolymer may be realized on the uneven structure. Thus, a self-assembled phenomenon may be induced.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunsung Kim, Jaewoo Nam, Chulho Shin
  • Patent number: 9543158
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in substantial preservation of a mask layer on the substrate. The protective coating may be deposited using particular reactants and/or reaction conditions that are unlikely to damage the mask layer. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 10, 2017
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Nikhil Dole
  • Patent number: 9455200
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: September 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Jian-An Ke
  • Patent number: 9437479
    Abstract: Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern atop a substrate includes depositing a porous dielectric layer atop a cap layer and a plurality of spacers disposed atop the cap layer, wherein the cap layer is disposed atop a bulk dielectric layer and the bulk dielectric layer is disposed atop a substrate; removing a portion of the porous dielectric layer; removing the plurality of spacers to form features in the porous dielectric layer; and etching the cap layer to extend the features through the cap layer.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: September 6, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Suketu A. Parikh, Mehul Naik
  • Patent number: 9401310
    Abstract: Embodiments may include a method of semiconductor patterning including forming a first trench bordered by a first spacer material. The method may involve forming a second trench bordered by a second spacer material formed conformally around the first spacer material. The method may include filling the second trench with a semiconductor material.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 26, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Ying Zhang, Hua Chung
  • Patent number: 9331198
    Abstract: We have demonstrated controlled growth of epitaxial h-BN on a metal substrate using atomic layer deposition. This permits the fabrication of devices such as vertical graphene transistors, where the electron tunneling barrier, and resulting characteristics such as ON-OFF rate may be altered by varying the number of epitaxial layers of h-BN. Few layer graphene is grown on the h-BN opposite the metal substrate, with leads to provide a vertical graphene transistor that is intergratable with Si CMOS technology of today, and can be prepared in a scalable, low temperature process of high repeatability and reliability.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: May 3, 2016
    Assignee: UNIVERSITY OF NORTH TEXAS
    Inventor: Jeffry Kelber
  • Patent number: 9305822
    Abstract: A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Chang, Shyh-Fann Ting, Ching-Chun Wang, Dun-Nian Yaung
  • Patent number: 9245764
    Abstract: This semiconductor device manufacturing method is provided with: a film-forming step wherein a silicon nitride layer or a silicon oxide layer is formed such that a side wall portion of a silicon-containing layer, which is formed on a substrate and patterned, is covered with the silicon nitride layer or the silicon oxide layer; and a plasma etching step wherein the silicon-containing layer is selectively removed, and the silicon nitride layer or the silicon oxide layer formed on the side wall portion is left. In the plasma etching step, an etching gas containing SF6 gas is used.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: January 26, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Tadashi Kotsugi, Fumiko Yamashita, Kenji Adachi
  • Patent number: 9224833
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 9190291
    Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 17, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jui Liang, Po-Chao Tsao, Jun-Jie Wang, Chih-Sen Huang
  • Patent number: 9159578
    Abstract: A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the patterned line to the substrate.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 9147580
    Abstract: A plasma etching method for plasma etching, in a processing chamber, an antireflection film laminated on an organic film formed on a substrate by using an etching mask made of a resist film formed on the antireflection film, the plasma etching method includes: depositing a Si-containing compound on the etching mask made of the resist film by using plasma of Si-containing gas in the processing chamber; and etching the antireflection film in a state where the Si-containing compound is deposited on the etching mask.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 29, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Masanobu Honda, Hironobu Ichikawa, Jin Kudo
  • Patent number: 9142453
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chih Chiu, Ming-Chung Liang